coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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859 discussions

Patch merged into coreboot/master: cbfs: fix debug message
by gerrit＠coreboot.org 28 Sep '15

28 Sep '15

the following patch was just integrated into master: commit 9dcf4577075a7dea44fbfcefaa7555ac5ba5beb1 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Sep 23 13:01:14 2015 -0700 cbfs: fix debug message BUG=none BRANCH=tot TEST=built for Samus with debugging enabled Change-Id: I0b555d018f8c2eb1b51519a6227298c8d5d58a42 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5908e4b8ffc66e6ecc7cae78cf10055fbd727c81 Original-Change-Id: Ifd049111fee540789dabb1d7653568b80405b77d Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302131 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11713 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11713 for details. -gerrit

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Patch merged into coreboot/master: ec: superio: Report keyboard IRQ as wake capable
by gerrit＠coreboot.org 28 Sep '15

28 Sep '15

the following patch was just integrated into master: commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 21 15:00:20 2015 -0700 ec: superio: Report keyboard IRQ as wake capable In order to wake from S0ix the kernel needs to know that the keyboard interrupt is wake capable. Using IRQNoFlags does not allow the wake capability to be reported. For normal S3 this does not matter as the EC is the one handling the keyboard wake event. For S0ix the EC does not need to be involved in this particular wake event. BUG=chrome-os-partner:43079 BRANCH=none TEST=echo freeze > /sys/power/state and wake from keyboard Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373 Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/301441 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11712 for details. -gerrit

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Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Werner Zeh 28 Sep '15

28 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit 8cdec5d8c30aaa0cd3450f4aa8c6e1a5b6d4a0d1 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/fsp1_0/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..7e970c1 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +46,8 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ + && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +

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Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Werner Zeh 28 Sep '15

28 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit 66049bcb2ba5b65f59d93fa6d00b0792249af15c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/fsp1_0/Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..7e970c1 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +46,8 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ + && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +

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Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Werner Zeh 28 Sep '15

28 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit 162fb1e3e5ff356b576114540d8730cacb2fe50d Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..a1ce02b 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +46,7 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +

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Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Werner Zeh 28 Sep '15

28 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit 4880774a4320d4cec21b536f37f2bd6349a51a08 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..a1ce02b 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,8 +23,9 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) +cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc ifeq ($(CONFIG_HAVE_FSP_BIN),y) @@ -45,3 +46,7 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +

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Patch set updated for coreboot: intel/fsp1.0: Get size of microcode during build time
by Werner Zeh 28 Sep '15

28 Sep '15

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11709 -gerrit commit e51b062f2f02b33622abaecfae931a22a8deb762 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Sep 25 07:54:59 2015 +0200 intel/fsp1.0: Get size of microcode during build time Avoid specifying the size of the microcode in microcode_size.h. Instead, the size will be determined during build time and microcode_size.h will be generated. This way, the size does not need to be adjusted by hand. Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/arch/x86/Makefile.inc | 2 +- src/drivers/intel/fsp1_0/Makefile.inc | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 79b82e0..5dd7ff7 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -135,7 +135,7 @@ $(objgenerated)/romstage.inc: $$(crt0s) # the right order. Make sure the auto generated romstage.inc is a proper # dependency. romstage-y += romstage.S -$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc +$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc $$(FSP_MICROCODE_SIZE_HEADER) ifneq ($(CONFIG_ROMCC),y) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 11ff31a..3a81602 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -23,7 +23,7 @@ romstage-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated) cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc @@ -45,3 +45,8 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif + +export FSP_MICROCODE_SIZE_HEADER := $(objgenerated)/microcode_size.h +$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin + printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ +

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Patch set updated for coreboot: pcengines/apu1: Add CMOS/NVRAM support
by Maxime de Roucy 27 Sep '15

27 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730 -gerrit commit 989192df637b107c2f9e0e40fcf159acdaaad272 Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:45:35 2015 +0200 pcengines/apu1: Add CMOS/NVRAM support Inspired by the Sage code provided here : http://www.pcengines.ch/howto.php#CoreBoot Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 2 + src/mainboard/pcengines/apu1/cmos.default | 16 +++++++ src/mainboard/pcengines/apu1/cmos.layout | 77 +++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index b1b19c9..7ea1821 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default new file mode 100644 index 0000000..8022b63 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -0,0 +1,16 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +hw_scrubber=Disable +interleave_chip_selects=Disable +max_mem_clock=DDR3-1066 +multi_core=Enable +power_on_after_fail=Disable +debug_level=Emerg +boot_first=Network +boot_second=Network +boot_third=Network +slow_cpu=off +nmi=Disable +iommu=Disable diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout new file mode 100644 index 0000000..885bc63 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -0,0 +1,77 @@ +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 0 Emerg +6 1 Alert +6 2 Crit +6 3 Err +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +8 0 DDR3-1600 +8 1 DDR3-1333 +8 2 DDR3-1066 +8 3 DDR3-800 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984

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New patch to review for coreboot: coreinfo : reboot when done
by Maxime de Roucy 27 Sep '15

27 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11731 -gerrit commit 032859460d6951637a5edb930537adf89464d10f Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:53:40 2015 +0200 coreinfo : reboot when done Whithout this I got a "General Protection Fault Exception" when I leave coreinfo. http://www.coreboot.org/pipermail/coreboot/2015-September/080336.html Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- payloads/coreinfo/coreinfo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 5bd1068..df52056 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -301,6 +301,9 @@ int main(void) loop(); + /* reboot */ + outb(0x6, 0xcf9); + halt(); return 0; }

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New patch to review for coreboot: add cmos/nvram support for pcengines apu1
by Maxime de Roucy 27 Sep '15

27 Sep '15

Maxime de Roucy (maxime.deroucy(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11730 -gerrit commit ebe678d866fd38021c051dc634b1bb47d12d3604 Author: Maxime de Roucy <maxime.deroucy(a)gmail.com> Date: Sun Sep 27 15:45:35 2015 +0200 add cmos/nvram support for pcengines apu1 Inspired by the Sage code provided here : http://www.pcengines.ch/howto.php#CoreBoot Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 2 + src/mainboard/pcengines/apu1/cmos.default | 16 +++++++ src/mainboard/pcengines/apu1/cmos.layout | 79 +++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index b1b19c9..7ea1821 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default new file mode 100644 index 0000000..8022b63 --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -0,0 +1,16 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +hw_scrubber=Disable +interleave_chip_selects=Disable +max_mem_clock=DDR3-1066 +multi_core=Enable +power_on_after_fail=Disable +debug_level=Emerg +boot_first=Network +boot_second=Network +boot_third=Network +slow_cpu=off +nmi=Disable +iommu=Disable diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout new file mode 100644 index 0000000..2f8d26b --- /dev/null +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -0,0 +1,79 @@ +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 0 Emerg +6 1 Alert +6 2 Crit +6 3 Err +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +8 0 DDR3-1600 +8 1 DDR3-1333 +8 2 DDR3-1066 +8 3 DDR3-800 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + +

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coreboot-gerrit September 2015