coreboot-gerrit August 2015

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New patch to review for coreboot: skylake: provide native gpio functionality
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11174 -gerrit commit 954b710ab0bed71d1fd908574b735a7bf6f92d66 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 24 13:00:36 2015 -0500 skylake: provide native gpio functionality It's important to be able to configure the gpio pads at various stages instead of a single place using FSP. Without this support there is a lot of duplicated open-coded pad configuration taking place both within the SoC code and mainboards. Current limitation is that all GPIOs are in ACPI mode. i.e. The HostSW ownership register sets the pad configuration to only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The GPI_STS update is masked within the GPIO community registers. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289789 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/gpio.c | 347 +++++++++------- src/soc/intel/skylake/include/soc/gpio.h | 575 +++++--------------------- src/soc/intel/skylake/include/soc/gpio_defs.h | 479 +++++++++++++++++++++ src/soc/intel/skylake/include/soc/gpio_fsp.h | 512 +++++++++++++++++++++++ 5 files changed, 1285 insertions(+), 629 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e2c43f0..6c64cd9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS + select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 7967231..28ed07e 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -24,6 +24,201 @@ #include <soc/iomap.h> #include <soc/pm.h> + +/* There are 4 communities with 8 GPIO groups (GPP_[A:G] and GPD) */ +struct gpio_community { + int port_id; + /* Inclusive pads within the community. */ + gpio_t min; + gpio_t max; +}; + +/* This is ordered to match ACPI and OS driver. */ +static const struct gpio_community communities[] = { + { + .port_id = PID_GPIOCOM0, + .min = GPP_A0, + .max = GPP_B23, + }, + { + .port_id = PID_GPIOCOM1, + .min = GPP_C0, + .max = GPP_E23, + }, + { + .port_id = PID_GPIOCOM3, + .min = GPP_F0, + .max = GPP_G7, + }, + { + .port_id = PID_GPIOCOM2, + .min = GPD0, + .max = GPD11, + }, +}; + +static const struct gpio_community *gpio_get_community(gpio_t pad) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(communities); i++) { + const struct gpio_community *c = &communities[i]; + + if (pad >= c->min && pad <= c->max) + return c; + } + + return NULL; +} + +static void *gpio_dw_regs(gpio_t pad) +{ + const struct gpio_community *comm; + uint8_t *regs; + size_t pad_relative; + + comm = gpio_get_community(pad); + + if (comm == NULL) + return NULL; + + regs = pcr_port_regs(comm->port_id); + + pad_relative = pad - comm->min; + + /* DW0 and DW1 regs are 4 bytes each. */ + return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8]; +} + +static void *gpio_hostsw_reg(gpio_t pad, size_t *bit) +{ + const struct gpio_community *comm; + uint8_t *regs; + size_t pad_relative; + + comm = gpio_get_community(pad); + + if (comm == NULL) + return NULL; + + regs = pcr_port_regs(comm->port_id); + + pad_relative = pad - comm->min; + + /* Update the bit for this pad. */ + *bit = (pad_relative % HOSTSW_OWN_PADS_PER); + + /* HostSw regs are 4 bytes each. */ + regs = &regs[HOSTSW_OWN_REG_OFFSET]; + return &regs[(pad_relative / HOSTSW_OWN_PADS_PER) * 4]; +} + +static void gpio_handle_pad_mode(const struct pad_config *cfg) +{ + size_t bit; + uint32_t *hostsw_own_reg; + uint32_t reg; + + bit = 0; + hostsw_own_reg = gpio_hostsw_reg(cfg->pad, &bit); + + reg = read32(hostsw_own_reg); + reg &= ~(1U << bit); + + if ((cfg->attrs & PAD_FIELD(HOSTSW, GPIO)) == PAD_FIELD(HOSTSW, GPIO)) + reg |= (HOSTSW_GPIO << bit); + else + reg |= (HOSTSW_ACPI << bit); + + write32(hostsw_own_reg, reg); +} + +static void gpio_configure_pad(const struct pad_config *cfg) +{ + uint32_t *dw_regs; + uint32_t reg; + uint32_t termination; + const uint32_t termination_mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + + dw_regs = gpio_dw_regs(cfg->pad); + + if (dw_regs == NULL) + return; + + write32(&dw_regs[0], cfg->dw0); + reg = read32(&dw_regs[1]); + reg &= ~termination_mask; + termination = cfg->attrs; + termination &= termination_mask; + reg |= termination; + write32(&dw_regs[1], reg); + + gpio_handle_pad_mode(cfg); +} + +void gpio_configure_pads(const struct pad_config *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + gpio_configure_pad(&cfgs[i]); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, 5K_PD, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input_pullup(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, 5K_PU, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_output(gpio_t gpio, int value) +{ + struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); + gpio_configure_pad(&cfg); +} + +int gpio_get(gpio_t gpio_num) +{ + uint32_t *dw_regs; + uint32_t reg; + + dw_regs = gpio_dw_regs(gpio_num); + + if (dw_regs == NULL) + return -1; + + reg = read32(&dw_regs[0]); + + return (reg >> GPIORXSTATE_SHIFT) & GPIORXSTATE_MASK; +} + +void gpio_set(gpio_t gpio_num, int value) +{ + uint32_t *dw_regs; + uint32_t reg; + + dw_regs = gpio_dw_regs(gpio_num); + + if (dw_regs == NULL) + return; + + reg = read32(&dw_regs[0]); + reg |= PAD_FIELD_VAL(GPIOTXSTATE, value); + write32(&dw_regs[0], reg); + /* GPIO port ids support posted write semantics. */ +} + /* Keep the ordering intact GPP_A ~ G, GPD. * As the gpio/smi functions gpio_get_smi_status() and * gpio_enable_groupsmi() depends on this ordering. @@ -85,7 +280,7 @@ static const GPIO_GROUP_INFO gpio_group_info[] = { .smistsoffset = NO_REGISTER_PROPERTY, .smienoffset = NO_REGISTER_PROPERTY, }, - /* GPP_H */ + /* GPD */ { .community = PID_GPIOCOM2, .padcfgoffset = R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET, @@ -95,156 +290,6 @@ static const GPIO_GROUP_INFO gpio_group_info[] = { }, }; -/* - * SPT has 7 GPIO communities named as GPP_A to GPP_G. - * Each community has 24 GPIO PIN. - * Below formula to calculate GPIO Pin from GPIO PAD. - * PIN# = GROUP_PAD# + GROUP# * 24 - * ==================================== - * Community || Group# - * ==================================== - * GPP_A || 0 - * GPP_B || 1 - * GPP_C || 2 - * GPP_D || 3 - * GPP_E || 4 - * GPP_F || 5 - * GPP_G || 6 - */ -static u32 get_padnumber_from_gpiopad(GPIO_PAD gpiopad) -{ - return (u32) GPIO_GET_PAD_NUMBER(gpiopad); -} - -static u32 get_groupindex_from_gpiopad(GPIO_PAD gpiopad) -{ - return (u32) GPIO_GET_GROUP_INDEX_FROM_PAD(gpiopad); -} - -static int read_write_gpio_pad_reg(u32 gpiopad, u8 dwreg, u32 mask, int write, - u32 *readwriteval) -{ - u32 padcfgreg; - u32 gpiogroupinfolength; - u32 groupindex; - u32 padnumber; - - groupindex = get_groupindex_from_gpiopad(gpiopad); - padnumber = get_padnumber_from_gpiopad(gpiopad); - - gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO); - - /* Check if group argument exceeds GPIO GROUP INFO array */ - if ((u32) groupindex >= gpiogroupinfolength) - return -1; - /* Check if legal pin number */ - if (padnumber >= gpio_group_info[groupindex].padpergroup) - return -1; - /* Create Pad Configuration register offset */ - padcfgreg = 0x8 * padnumber + gpio_group_info[groupindex].padcfgoffset; - if (dwreg == 1) - padcfgreg += 0x4; - if (write) { - pcr_andthenor32(gpio_group_info[groupindex].community, - padcfgreg, (u32) (~mask), - (u32) (*readwriteval & mask)); - } else { - pcr_read32(gpio_group_info[groupindex].community, padcfgreg, - readwriteval); - *readwriteval &= mask; - } - - return 0; -} - -static int convert_gpio_num_to_pad(gpio_t gpionum) -{ - int group_pad_num = 0; - int gpio_group = 0; - u32 gpio_pad = 0; - - group_pad_num = (gpionum % MAX_GPIO_PIN_PER_GROUP); - gpio_group = (gpionum / MAX_GPIO_PIN_PER_GROUP); - - switch (gpio_group) { - case GPIO_LP_GROUP_A: - gpio_pad = GPIO_LP_GROUP_GPP_A; - break; - - case GPIO_LP_GROUP_B: - gpio_pad = GPIO_LP_GROUP_GPP_B; - break; - - case GPIO_LP_GROUP_C: - gpio_pad = GPIO_LP_GROUP_GPP_C; - break; - - case GPIO_LP_GROUP_D: - gpio_pad = GPIO_LP_GROUP_GPP_D; - break; - - case GPIO_LP_GROUP_E: - gpio_pad = GPIO_LP_GROUP_GPP_E; - break; - - case GPIO_LP_GROUP_F: - gpio_pad = GPIO_LP_GROUP_GPP_F; - break; - - case GPIO_LP_GROUP_G: - gpio_pad = GPIO_LP_GROUP_GPP_G; - break; - default: - return -1; - break; - } - gpio_pad = (gpio_pad << GPIO_GROUP_SHIFT) + group_pad_num; - - return gpio_pad; -} - -int gpio_get(gpio_t gpio_num) -{ - u32 gpiopad = 0; - u32 outputvalue = 0; - int status = 0; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; - - gpiopad = convert_gpio_num_to_pad(gpio_num); - if (gpiopad < 0) - return -1; - - status = read_write_gpio_pad_reg(gpiopad, - 0, - B_PCH_GPIO_TX_STATE, - READ, &outputvalue); - outputvalue >>= N_PCH_GPIO_TX_STATE; - return outputvalue; -} - -void gpio_set(gpio_t gpio_num, int value) -{ - int status = 0; - u32 gpiopad = 0; - u32 outputvalue = 0; - - if (gpio_num > MAX_GPIO_NUMBER) - return; - - gpiopad = convert_gpio_num_to_pad(gpio_num); - if (gpiopad < 0) - return; - - outputvalue = value; - - status = read_write_gpio_pad_reg(gpiopad, - 0, - B_PCH_GPIO_TX_STATE, - WRITE, &outputvalue); -} - void gpio_clear_all_smi(void) { u32 gpiogroupinfolength; diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index e8438ff..a7d9158 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -22,11 +22,14 @@ #define _SOC_GPIO_H_ #include <stdint.h> +#include <stddef.h> +#include <soc/gpio_defs.h> +#include <soc/gpio_fsp.h> /* SOC has 8 GPIO communities GPP A~G, GPD */ #define GPIO_COMMUNITY_MAX 8 -typedef int gpio_t; +typedef uint32_t gpio_t; /* Clear GPIO SMI Status */ void gpio_clear_all_smi(void); @@ -40,490 +43,106 @@ void gpio_enable_all_smi(void); /* Enable GPIO individual Group SMI */ void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); -/* - * GPP_Ax to GPP_Gx; - * where x=24 [between GPIO Community A to F] - * = 7 [only for GPIO Community G] - */ -#define MAX_GPIO_NUMBER 151 /* zero based */ -#define GPIO_LIST_END 0xffffffff - -/* - * Skylake LP GPIO PIN to Pad Mapping - */ -#define GPIO_LP_GROUP_A 0x0 -#define GPIO_LP_GROUP_B 0x1 -#define GPIO_LP_GROUP_C 0x2 -#define GPIO_LP_GROUP_D 0x3 -#define GPIO_LP_GROUP_E 0x4 -#define GPIO_LP_GROUP_F 0x5 -#define GPIO_LP_GROUP_G 0x6 - -#define GPIO_LP_GROUP_GPP_A 0x0200 -#define GPIO_LP_GROUP_GPP_B 0x0201 -#define GPIO_LP_GROUP_GPP_C 0x0202 -#define GPIO_LP_GROUP_GPP_D 0x0203 -#define GPIO_LP_GROUP_GPP_E 0x0204 -#define GPIO_LP_GROUP_GPP_F 0x0205 -#define GPIO_LP_GROUP_GPP_G 0x0206 - -#define GPIO_GROUP_SHIFT 16 -#define MAX_GPIO_PIN_PER_GROUP 24 - -/* GPIO TX STATE */ -#define B_PCH_GPIO_TX_STATE 0x0001 -#define N_PCH_GPIO_TX_STATE 0 - -/* Interrupt number */ -#define B_PCH_GPIO_INTSEL 0x7F -#define N_PCH_GPIO_INTSEL 0 - -/* Structure for storing information about registers offset, community, - * maximal pad number, smi status and smi enable for available groups - */ -typedef struct { - u32 community; - u32 padcfgoffset; - u32 padpergroup; - u32 smistsoffset; - u32 smienoffset; -} GPIO_GROUP_INFO; - -/* - * GPIO Community 0 Registers are for GPP_A and GPP_B groups - */ -#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 - -/* - * GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups - */ -#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 -#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 -#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 -#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 - -/* - * GPIO Community 3 Registers are for GPP_F and GPP_G groups - */ -#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 - -/* - * GPIO Community 2 Registers are for GPP_DSW - */ -#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 - -#define READ 0 -#define WRITE 1 - -/* If in GPIO_GROUP_INFO structure certain register doesn't exist - * it will have value equal to NO_REGISTER_PROPERTY - */ -#define NO_REGISTER_PROPERTY (~0u) +/* Configure the pads according to the pad_config array. */ +struct pad_config; +void gpio_configure_pads(const struct pad_config *cfgs, size_t num); -#define V_PCH_GPIO_GPP_A_PAD_MAX 24 -#define V_PCH_GPIO_GPP_B_PAD_MAX 24 -#define V_PCH_GPIO_GPP_C_PAD_MAX 24 -#define V_PCH_GPIO_GPP_D_PAD_MAX 24 -#define V_PCH_GPIO_GPP_E_PAD_MAX 24 -#define V_PCH_GPIO_GPP_F_PAD_MAX 24 -#define V_PCH_GPIO_GPP_G_PAD_MAX 8 -#define V_PCH_GPIO_GPD_PAD_MAX 12 +#define PAD_FIELD_VAL(field_, val_) \ + (((val_) & field_ ## _MASK) << field_ ## _SHIFT) -#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) -#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ - GPIO_GET_GROUP_INDEX((pad >> 16))) -#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) - -/* Number of pins used by SerialIo controllers */ -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 - -/* Below defines are based on GPIO_CONFIG structure fields */ -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 - -/* GPIO Pad Mode */ -#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) -#define N_PCH_GPIO_PAD_MODE 10 - -/* For any GpioPad usage in code use GPIO_PAD type*/ -typedef u32 GPIO_PAD; - -/* For any GpioGroup usage in code use GPIO_GROUP type */ -typedef u32 GPIO_GROUP; - -/* - * GPIO configuration structure used for pin programming. - * Structure contains fields that can be used to configure pad. - */ -typedef struct { - /* - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction, OutputState, Interrupt is unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - */ - u32 PadMode : 4; - /* - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - */ - u32 HostSoftPadOwn : 2; - /* - GPIO Direction - Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d - isabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - */ - u32 Direction : 5; - /* - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - */ - u32 OutputState : 2; - /* - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO - A is in input mode. - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Refer to definition of GPIO_INT_CONFIG for supported settings. - */ - u32 InterruptConfig : 8; - /* - GPIO Power Configuration. - This setting controls Pad Reset Configuration and Power Rail Type. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - */ - u32 PowerConfig : 4; - /* - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - */ - u32 ElectricalConfig : 7; - /* - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - */ - u32 LockConfig : 3; - /* - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - */ - u32 OtherSettings : 2; - u32 RsvdBits : 27; -} GPIO_CONFIG; - -typedef struct { - GPIO_PAD GpioPad; - GPIO_CONFIG GpioConfig; -} GPIO_INIT_CONFIG; - -typedef enum { - GpioHardwareDefault = 0x0 -} GPIO_HARDWARE_DEFAULT; - -/* GPIO Pad Mode */ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, -} GPIO_PAD_MODE; - -/* Host Software Pad Ownership modes */ -typedef enum { - GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ - GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ - GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ -} GPIO_HOSTSW_OWN; - -/* GPIO Direction */ -typedef enum { - GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ - GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ - GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ - GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ - GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ - GpioDirOut = 0x5, /* Set pad for output only */ - GpioDirNone = 0x7 /* Disable both output and input */ -} GPIO_DIRECTION; - -/* GPIO Output State */ -typedef enum { - GpioOutDefault = 0x0, - GpioOutLow = 0x1, - GpioOutHigh = 0x3 -} GPIO_OUTPUT_STATE; +#define PAD_FIELD(field_, setting_) \ + PAD_FIELD_VAL(field_, field_ ## _ ## setting_) /* - * GPIO interrupt configuration - * This setting is applicable only if GPIO is in input mode. - * GPIO_INT_CONFIG allows to choose which interrupt is generted - * (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). - * Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to - * GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel - * If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - * Not all GPIO are capable of generating an SMI or NMI interrupt - */ -typedef enum { - GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ - GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ - GpioIntNmi = 0x3, /* Enable NMI interrupt only */ - GpioIntSmi = 0x5, /* Enable SMI interrupt only */ - GpioIntSci = 0x9, /* Enable SCI interrupt only */ - GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ - GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ - GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ - GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ - GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ -} GPIO_INT_CONFIG; + * This encodes all the fields found within the dw0 register for each + * pad. It directly follows the register specification: + * rst - reset type when pad configuration is reset + * rxst - native function routing: raw buffer or internal buffer + * rxraw1 - drive fixed '1' for Rx buffer + * rxev - event filtering for pad value: level, edge, drive '0' + * rxgf - glitch filter enable + * rxinv - invert the internal pad state + * gpiioapic - route to IOxAPIC + * gpisci - route for SCI + * gpismi - route for SMI + * gpinmi - route for NMI + * mode - GPIO vs native function + * rxdis - disable Rx buffer + * txdis - disable Tx buffer + */ +#define _DW0_VALS(rst, rxst, rxraw1, rxev, rxgf, rxinv, gpiioapic, gpisci, \ + gpismi, gpinmi, mode, rxdis, txdis) \ + (PAD_FIELD(PADRSTCFG, rst) | \ + PAD_FIELD(RXPADSTSEL, rxst) | \ + PAD_FIELD(RXRAW1, rxraw1) | \ + PAD_FIELD(RXEVCFG, rxev) | \ + PAD_FIELD(PREGFRXSEL, rxgf) | \ + PAD_FIELD(RXINV, rxinv) | \ + PAD_FIELD(GPIROUTIOXAPIC, gpiioapic) | \ + PAD_FIELD(GPIROUTSCI, gpisci) | \ + PAD_FIELD(GPIROUTSMI, gpismi) | \ + PAD_FIELD(GPIROUTNMI, gpinmi) | \ + PAD_FIELD(PMODE, mode) | \ + PAD_FIELD(GPIORXDIS, rxdis) | \ + PAD_FIELD(GPIOTXDIS, txdis)) + +#define _PAD_CFG_ATTRS(pad_, term_, dw0_, attrs_) \ + { \ + .pad = pad_, \ + .attrs = PAD_FIELD(PAD_TERM, term_) | attrs_, \ + .dw0 = dw0_, \ + } + +#define _PAD_CFG(pad_, term_, dw0_) _PAD_CFG_ATTRS(pad_, term_, dw0_, 0) + +/* Native Function - No Rx buffer manipulation */ +#define PAD_CFG_NF(pad_, term_, rst_, func_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) + +/* General purpose output. By default no termination. */ +#define PAD_CFG_GPO(pad_, val_, rst_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \ + | PAD_FIELD_VAL(GPIOTXSTATE, val_)) + +/* General purpose input with no special IRQ routing. */ +#define PAD_CFG_GPI(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES)) + +/* General purpose input passed through to IOxAPIC. Assume APIC logic can + * handle polarity/edge/level constraints. */ +#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES)) + +/* General purpose input routed to SCI. This assumes edge triggered events. */ +#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ + NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) + +/* General purpose input routed to SMI. This assumes edge triggered events. */ +#define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ + NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) /* - * GPIO Power Configuration - * GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified - * Pad Register fields). + * The 'attrs' field carries the termination in bits 13:10 to match up with + * thd DW1 pad configuration register. Additionally, other attributes can + * be applied such as the ones below. Bit allocation matters. */ -typedef enum { - GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ - GpioResetPwrGood = 0x1, /* Powergood reset */ - GpioResetDeep = 0x3, /* Deep GPIO Reset */ - GpioResetNormal = 0x5, /* GPIO Reset */ - GpioResetResume = 0x7 /* Resume Reset */ -} GPIO_RESET_CONFIG; +#define HOSTSW_SHIFT 0 +#define HOSTSW_MASK 1 +#define HOSTSW_ACPI HOSTSW_OWN_ACPI +#define HOSTSW_GPIO HOSTSW_OWN_GPIO -/* - * GPIO Electrical Configuration - * Set GPIO termination and Pad Tolerance (applicable only for some pads) - * Field from GpioTermDefault to GpioTermNative can be OR'ed with - * GpioTolerance1v8. - */ -typedef enum { - GpioTermDefault = 0x0, /* Leave termination setting unmodified */ - GpioTermNone = 0x1, /* none */ - GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ - GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ - GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ - GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ - GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ - GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ - GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ - GpioTermNative = 0x1F, /* Native function for pads termination */ - GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ - GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ -} GPIO_ELECTRICAL_CONFIG; - -/* - * GPIO LockConfiguration - * Set GPIO configuration lock and output state lock - * GpioLockPadConfig and GpioLockOutputState can be OR'ed - */ -typedef enum { - GpioLockDefault = 0x0, /* Leave lock setting unmodified */ - GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ - GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ -} GPIO_LOCK_CONFIG; - -/* - * Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often - * settings and for future extensions Supported settings: - * - RX raw override to '1' - allows to override input value to '1' - * This is applicable only if in input mode (both in GPIO and native usage) - * The override takes place at the internal pad state directly from buffer - * and before the RXINV. - */ -typedef enum { - GpioRxRaw1Default = 0x0, /* Use default input override value */ - GpioRxRaw1Dis = 0x1, /* Don't override input */ - GpioRxRaw1En = 0x3 /* Override input to '1' */ -} GPIO_OTHER_CONFIG; - -/* - * LP GPIO pins: Use below for functions from PCH GPIO Lib which - * require GpioPad as argument. Encoding used here - * has all information required by library functions - */ -#define GPIO_LP_GPP_A0 0x02000000 -#define GPIO_LP_GPP_A1 0x02000001 -#define GPIO_LP_GPP_A2 0x02000002 -#define GPIO_LP_GPP_A3 0x02000003 -#define GPIO_LP_GPP_A4 0x02000004 -#define GPIO_LP_GPP_A5 0x02000005 -#define GPIO_LP_GPP_A6 0x02000006 -#define GPIO_LP_GPP_A7 0x02000007 -#define GPIO_LP_GPP_A8 0x02000008 -#define GPIO_LP_GPP_A9 0x02000009 -#define GPIO_LP_GPP_A10 0x0200000A -#define GPIO_LP_GPP_A11 0x0200000B -#define GPIO_LP_GPP_A12 0x0200000C -#define GPIO_LP_GPP_A13 0x0200000D -#define GPIO_LP_GPP_A14 0x0200000E -#define GPIO_LP_GPP_A15 0x0200000F -#define GPIO_LP_GPP_A16 0x02000010 -#define GPIO_LP_GPP_A17 0x02000011 -#define GPIO_LP_GPP_A18 0x02000012 -#define GPIO_LP_GPP_A19 0x02000013 -#define GPIO_LP_GPP_A20 0x02000014 -#define GPIO_LP_GPP_A21 0x02000015 -#define GPIO_LP_GPP_A22 0x02000016 -#define GPIO_LP_GPP_A23 0x02000017 -#define GPIO_LP_GPP_B0 0x02010000 -#define GPIO_LP_GPP_B1 0x02010001 -#define GPIO_LP_GPP_B2 0x02010002 -#define GPIO_LP_GPP_B3 0x02010003 -#define GPIO_LP_GPP_B4 0x02010004 -#define GPIO_LP_GPP_B5 0x02010005 -#define GPIO_LP_GPP_B6 0x02010006 -#define GPIO_LP_GPP_B7 0x02010007 -#define GPIO_LP_GPP_B8 0x02010008 -#define GPIO_LP_GPP_B9 0x02010009 -#define GPIO_LP_GPP_B10 0x0201000A -#define GPIO_LP_GPP_B11 0x0201000B -#define GPIO_LP_GPP_B12 0x0201000C -#define GPIO_LP_GPP_B13 0x0201000D -#define GPIO_LP_GPP_B14 0x0201000E -#define GPIO_LP_GPP_B15 0x0201000F -#define GPIO_LP_GPP_B16 0x02010010 -#define GPIO_LP_GPP_B17 0x02010011 -#define GPIO_LP_GPP_B18 0x02010012 -#define GPIO_LP_GPP_B19 0x02010013 -#define GPIO_LP_GPP_B20 0x02010014 -#define GPIO_LP_GPP_B21 0x02010015 -#define GPIO_LP_GPP_B22 0x02010016 -#define GPIO_LP_GPP_B23 0x02010017 -#define GPIO_LP_GPP_C0 0x02020000 -#define GPIO_LP_GPP_C1 0x02020001 -#define GPIO_LP_GPP_C2 0x02020002 -#define GPIO_LP_GPP_C3 0x02020003 -#define GPIO_LP_GPP_C4 0x02020004 -#define GPIO_LP_GPP_C5 0x02020005 -#define GPIO_LP_GPP_C6 0x02020006 -#define GPIO_LP_GPP_C7 0x02020007 -#define GPIO_LP_GPP_C8 0x02020008 -#define GPIO_LP_GPP_C9 0x02020009 -#define GPIO_LP_GPP_C10 0x0202000A -#define GPIO_LP_GPP_C11 0x0202000B -#define GPIO_LP_GPP_C12 0x0202000C -#define GPIO_LP_GPP_C13 0x0202000D -#define GPIO_LP_GPP_C14 0x0202000E -#define GPIO_LP_GPP_C15 0x0202000F -#define GPIO_LP_GPP_C16 0x02020010 -#define GPIO_LP_GPP_C17 0x02020011 -#define GPIO_LP_GPP_C18 0x02020012 -#define GPIO_LP_GPP_C19 0x02020013 -#define GPIO_LP_GPP_C20 0x02020014 -#define GPIO_LP_GPP_C21 0x02020015 -#define GPIO_LP_GPP_C22 0x02020016 -#define GPIO_LP_GPP_C23 0x02020017 -#define GPIO_LP_GPP_D0 0x02030000 -#define GPIO_LP_GPP_D1 0x02030001 -#define GPIO_LP_GPP_D2 0x02030002 -#define GPIO_LP_GPP_D3 0x02030003 -#define GPIO_LP_GPP_D4 0x02030004 -#define GPIO_LP_GPP_D5 0x02030005 -#define GPIO_LP_GPP_D6 0x02030006 -#define GPIO_LP_GPP_D7 0x02030007 -#define GPIO_LP_GPP_D8 0x02030008 -#define GPIO_LP_GPP_D9 0x02030009 -#define GPIO_LP_GPP_D10 0x0203000A -#define GPIO_LP_GPP_D11 0x0203000B -#define GPIO_LP_GPP_D12 0x0203000C -#define GPIO_LP_GPP_D13 0x0203000D -#define GPIO_LP_GPP_D14 0x0203000E -#define GPIO_LP_GPP_D15 0x0203000F -#define GPIO_LP_GPP_D16 0x02030010 -#define GPIO_LP_GPP_D17 0x02030011 -#define GPIO_LP_GPP_D18 0x02030012 -#define GPIO_LP_GPP_D19 0x02030013 -#define GPIO_LP_GPP_D20 0x02030014 -#define GPIO_LP_GPP_D21 0x02030015 -#define GPIO_LP_GPP_D22 0x02030016 -#define GPIO_LP_GPP_D23 0x02030017 -#define GPIO_LP_GPP_E0 0x02040000 -#define GPIO_LP_GPP_E1 0x02040001 -#define GPIO_LP_GPP_E2 0x02040002 -#define GPIO_LP_GPP_E3 0x02040003 -#define GPIO_LP_GPP_E4 0x02040004 -#define GPIO_LP_GPP_E5 0x02040005 -#define GPIO_LP_GPP_E6 0x02040006 -#define GPIO_LP_GPP_E7 0x02040007 -#define GPIO_LP_GPP_E8 0x02040008 -#define GPIO_LP_GPP_E9 0x02040009 -#define GPIO_LP_GPP_E10 0x0204000A -#define GPIO_LP_GPP_E11 0x0204000B -#define GPIO_LP_GPP_E12 0x0204000C -#define GPIO_LP_GPP_E13 0x0204000D -#define GPIO_LP_GPP_E14 0x0204000E -#define GPIO_LP_GPP_E15 0x0204000F -#define GPIO_LP_GPP_E16 0x02040010 -#define GPIO_LP_GPP_E17 0x02040011 -#define GPIO_LP_GPP_E18 0x02040012 -#define GPIO_LP_GPP_E19 0x02040013 -#define GPIO_LP_GPP_E20 0x02040014 -#define GPIO_LP_GPP_E21 0x02040015 -#define GPIO_LP_GPP_E22 0x02040016 -#define GPIO_LP_GPP_E23 0x02040017 -#define GPIO_LP_GPP_F0 0x02050000 -#define GPIO_LP_GPP_F1 0x02050001 -#define GPIO_LP_GPP_F2 0x02050002 -#define GPIO_LP_GPP_F3 0x02050003 -#define GPIO_LP_GPP_F4 0x02050004 -#define GPIO_LP_GPP_F5 0x02050005 -#define GPIO_LP_GPP_F6 0x02050006 -#define GPIO_LP_GPP_F7 0x02050007 -#define GPIO_LP_GPP_F8 0x02050008 -#define GPIO_LP_GPP_F9 0x02050009 -#define GPIO_LP_GPP_F10 0x0205000A -#define GPIO_LP_GPP_F11 0x0205000B -#define GPIO_LP_GPP_F12 0x0205000C -#define GPIO_LP_GPP_F13 0x0205000D -#define GPIO_LP_GPP_F14 0x0205000E -#define GPIO_LP_GPP_F15 0x0205000F -#define GPIO_LP_GPP_F16 0x02050010 -#define GPIO_LP_GPP_F17 0x02050011 -#define GPIO_LP_GPP_F18 0x02050012 -#define GPIO_LP_GPP_F19 0x02050013 -#define GPIO_LP_GPP_F20 0x02050014 -#define GPIO_LP_GPP_F21 0x02050015 -#define GPIO_LP_GPP_F22 0x02050016 -#define GPIO_LP_GPP_F23 0x02050017 -#define GPIO_LP_GPP_G0 0x02060000 -#define GPIO_LP_GPP_G1 0x02060001 -#define GPIO_LP_GPP_G2 0x02060002 -#define GPIO_LP_GPP_G3 0x02060003 -#define GPIO_LP_GPP_G4 0x02060004 -#define GPIO_LP_GPP_G5 0x02060005 -#define GPIO_LP_GPP_G6 0x02060006 -#define GPIO_LP_GPP_G7 0x02060007 -#define GPIO_LP_GPD0 0x02070000 -#define GPIO_LP_GPD1 0x02070001 -#define GPIO_LP_GPD2 0x02070002 -#define GPIO_LP_GPD3 0x02070003 -#define GPIO_LP_GPD4 0x02070004 -#define GPIO_LP_GPD5 0x02070005 -#define GPIO_LP_GPD6 0x02070006 -#define GPIO_LP_GPD7 0x02070007 -#define GPIO_LP_GPD8 0x02070008 -#define GPIO_LP_GPD9 0x02070009 -#define GPIO_LP_GPD10 0x0207000A -#define GPIO_LP_GPD11 0x0207000B +struct pad_config { + uint16_t pad; + uint16_t attrs; + uint32_t dw0; +}; -#define END_OF_GPIO_TABLE 0xFFFFFFFF #endif diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h new file mode 100644 index 0000000..61d80bd --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -0,0 +1,479 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_GPIO_DEFS_H_ +#define _SOC_GPIO_DEFS_H_ + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group C */ +#define GPP_C0 48 +#define GPP_C1 49 +#define GPP_C2 50 +#define GPP_C3 51 +#define GPP_C4 52 +#define GPP_C5 53 +#define GPP_C6 54 +#define GPP_C7 55 +#define GPP_C8 56 +#define GPP_C9 57 +#define GPP_C10 58 +#define GPP_C11 59 +#define GPP_C12 60 +#define GPP_C13 61 +#define GPP_C14 62 +#define GPP_C15 63 +#define GPP_C16 64 +#define GPP_C17 65 +#define GPP_C18 66 +#define GPP_C19 67 +#define GPP_C20 68 +#define GPP_C21 69 +#define GPP_C22 70 +#define GPP_C23 71 +/* Group D */ +#define GPP_D0 72 +#define GPP_D1 73 +#define GPP_D2 74 +#define GPP_D3 75 +#define GPP_D4 76 +#define GPP_D5 77 +#define GPP_D6 78 +#define GPP_D7 79 +#define GPP_D8 80 +#define GPP_D9 81 +#define GPP_D10 82 +#define GPP_D11 83 +#define GPP_D12 84 +#define GPP_D13 85 +#define GPP_D14 86 +#define GPP_D15 87 +#define GPP_D16 88 +#define GPP_D17 89 +#define GPP_D18 90 +#define GPP_D19 91 +#define GPP_D20 92 +#define GPP_D21 93 +#define GPP_D22 94 +#define GPP_D23 95 +/* Group E */ +#define GPP_E0 96 +#define GPP_E1 97 +#define GPP_E2 98 +#define GPP_E3 99 +#define GPP_E4 100 +#define GPP_E5 101 +#define GPP_E6 102 +#define GPP_E7 103 +#define GPP_E8 104 +#define GPP_E9 105 +#define GPP_E10 106 +#define GPP_E11 107 +#define GPP_E12 108 +#define GPP_E13 109 +#define GPP_E14 110 +#define GPP_E15 111 +#define GPP_E16 112 +#define GPP_E17 113 +#define GPP_E18 114 +#define GPP_E19 115 +#define GPP_E20 116 +#define GPP_E21 117 +#define GPP_E22 118 +#define GPP_E23 119 +/* Group F */ +#define GPP_F0 120 +#define GPP_F1 121 +#define GPP_F2 122 +#define GPP_F3 123 +#define GPP_F4 124 +#define GPP_F5 125 +#define GPP_F6 126 +#define GPP_F7 127 +#define GPP_F8 128 +#define GPP_F9 129 +#define GPP_F10 130 +#define GPP_F11 131 +#define GPP_F12 132 +#define GPP_F13 133 +#define GPP_F14 134 +#define GPP_F15 135 +#define GPP_F16 136 +#define GPP_F17 137 +#define GPP_F18 138 +#define GPP_F19 139 +#define GPP_F20 140 +#define GPP_F21 141 +#define GPP_F22 142 +#define GPP_F23 143 +/* Group G */ +#define GPP_G0 144 +#define GPP_G1 145 +#define GPP_G2 146 +#define GPP_G3 147 +#define GPP_G4 148 +#define GPP_G5 149 +#define GPP_G6 150 +#define GPP_G7 151 +/* Group GPD */ +#define GPD0 152 +#define GPD1 153 +#define GPD2 154 +#define GPD3 155 +#define GPD4 156 +#define GPD5 157 +#define GPD6 158 +#define GPD7 159 +#define GPD8 160 +#define GPD9 161 +#define GPD10 162 +#define GPD11 163 + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x1a +#define GPP_A3_IRQ 0x1b +#define GPP_A4_IRQ 0x1c +#define GPP_A5_IRQ 0x1d +#define GPP_A6_IRQ 0x1e +#define GPP_A7_IRQ 0x1f +#define GPP_A8_IRQ 0x20 +#define GPP_A9_IRQ 0x21 +#define GPP_A10_IRQ 0x22 +#define GPP_A11_IRQ 0x23 +#define GPP_A12_IRQ 0x24 +#define GPP_A13_IRQ 0x25 +#define GPP_A14_IRQ 0x26 +#define GPP_A15_IRQ 0x27 +#define GPP_A16_IRQ 0x28 +#define GPP_A17_IRQ 0x29 +#define GPP_A18_IRQ 0x2a +#define GPP_A19_IRQ 0x2b +#define GPP_A20_IRQ 0x2c +#define GPP_A21_IRQ 0x2d +#define GPP_A22_IRQ 0x2e +#define GPP_A23_IRQ 0x2f +/* Group B */ +#define GPP_B0_IRQ 0x30 +#define GPP_B1_IRQ 0x31 +#define GPP_B2_IRQ 0x32 +#define GPP_B3_IRQ 0x33 +#define GPP_B4_IRQ 0x34 +#define GPP_B5_IRQ 0x35 +#define GPP_B6_IRQ 0x36 +#define GPP_B7_IRQ 0x37 +#define GPP_B8_IRQ 0x38 +#define GPP_B9_IRQ 0x39 +#define GPP_B10_IRQ 0x3a +#define GPP_B11_IRQ 0x3b +#define GPP_B12_IRQ 0x3c +#define GPP_B13_IRQ 0x3d +#define GPP_B14_IRQ 0x3e +#define GPP_B15_IRQ 0x3f +#define GPP_B16_IRQ 0x40 +#define GPP_B17_IRQ 0x41 +#define GPP_B18_IRQ 0x42 +#define GPP_B19_IRQ 0x43 +#define GPP_B20_IRQ 0x44 +#define GPP_B21_IRQ 0x45 +#define GPP_B22_IRQ 0x46 +#define GPP_B23_IRQ 0x47 +/* Group C */ +#define GPP_C0_IRQ 0x48 +#define GPP_C1_IRQ 0x49 +#define GPP_C2_IRQ 0x4a +#define GPP_C3_IRQ 0x4b +#define GPP_C4_IRQ 0x4c +#define GPP_C5_IRQ 0x4d +#define GPP_C6_IRQ 0x4e +#define GPP_C7_IRQ 0x4f +#define GPP_C8_IRQ 0x50 +#define GPP_C9_IRQ 0x51 +#define GPP_C10_IRQ 0x52 +#define GPP_C11_IRQ 0x53 +#define GPP_C12_IRQ 0x54 +#define GPP_C13_IRQ 0x55 +#define GPP_C14_IRQ 0x56 +#define GPP_C15_IRQ 0x57 +#define GPP_C16_IRQ 0x58 +#define GPP_C17_IRQ 0x59 +#define GPP_C18_IRQ 0x5a +#define GPP_C19_IRQ 0x5b +#define GPP_C20_IRQ 0x5c +#define GPP_C21_IRQ 0x5d +#define GPP_C22_IRQ 0x5e +#define GPP_C23_IRQ 0x5f +/* Group D */ +#define GPP_D0_IRQ 0x60 +#define GPP_D1_IRQ 0x61 +#define GPP_D2_IRQ 0x62 +#define GPP_D3_IRQ 0x63 +#define GPP_D4_IRQ 0x64 +#define GPP_D5_IRQ 0x65 +#define GPP_D6_IRQ 0x66 +#define GPP_D7_IRQ 0x67 +#define GPP_D8_IRQ 0x68 +#define GPP_D9_IRQ 0x69 +#define GPP_D10_IRQ 0x6a +#define GPP_D11_IRQ 0x6b +#define GPP_D12_IRQ 0x6c +#define GPP_D13_IRQ 0x6d +#define GPP_D14_IRQ 0x6e +#define GPP_D15_IRQ 0x6f +#define GPP_D16_IRQ 0x70 +#define GPP_D17_IRQ 0x71 +#define GPP_D18_IRQ 0x72 +#define GPP_D19_IRQ 0x73 +#define GPP_D20_IRQ 0x74 +#define GPP_D21_IRQ 0x75 +#define GPP_D22_IRQ 0x76 +#define GPP_D23_IRQ 0x77 +/* Group E */ +#define GPP_E0_IRQ 0x18 +#define GPP_E1_IRQ 0x19 +#define GPP_E2_IRQ 0x1a +#define GPP_E3_IRQ 0x1b +#define GPP_E4_IRQ 0x1c +#define GPP_E5_IRQ 0x1d +#define GPP_E6_IRQ 0x1e +#define GPP_E7_IRQ 0x1f +#define GPP_E8_IRQ 0x20 +#define GPP_E9_IRQ 0x21 +#define GPP_E10_IRQ 0x22 +#define GPP_E11_IRQ 0x23 +#define GPP_E12_IRQ 0x24 +#define GPP_E13_IRQ 0x25 +#define GPP_E14_IRQ 0x26 +#define GPP_E15_IRQ 0x27 +#define GPP_E16_IRQ 0x28 +#define GPP_E17_IRQ 0x29 +#define GPP_E18_IRQ 0x2a +#define GPP_E19_IRQ 0x2b +#define GPP_E20_IRQ 0x2c +#define GPP_E21_IRQ 0x2d +#define GPP_E22_IRQ 0x2e +#define GPP_E23_IRQ 0x2f +/* Group F */ +#define GPP_F0_IRQ 0x30 +#define GPP_F1_IRQ 0x31 +#define GPP_F2_IRQ 0x32 +#define GPP_F3_IRQ 0x33 +#define GPP_F4_IRQ 0x34 +#define GPP_F5_IRQ 0x35 +#define GPP_F6_IRQ 0x36 +#define GPP_F7_IRQ 0x37 +#define GPP_F8_IRQ 0x38 +#define GPP_F9_IRQ 0x39 +#define GPP_F10_IRQ 0x3a +#define GPP_F11_IRQ 0x3b +#define GPP_F12_IRQ 0x3c +#define GPP_F13_IRQ 0x3d +#define GPP_F14_IRQ 0x3e +#define GPP_F15_IRQ 0x3f +#define GPP_F16_IRQ 0x40 +#define GPP_F17_IRQ 0x41 +#define GPP_F18_IRQ 0x42 +#define GPP_F19_IRQ 0x43 +#define GPP_F20_IRQ 0x44 +#define GPP_F21_IRQ 0x45 +#define GPP_F22_IRQ 0x46 +#define GPP_F23_IRQ 0x47 +/* Group G */ +#define GPP_G0_IRQ 0x48 +#define GPP_G1_IRQ 0x49 +#define GPP_G2_IRQ 0x4a +#define GPP_G3_IRQ 0x4b +#define GPP_G4_IRQ 0x4c +#define GPP_G5_IRQ 0x4d +#define GPP_G6_IRQ 0x4e +#define GPP_G7_IRQ 0x4f +/* Group GPD */ +#define GPD0_IRQ 0x50 +#define GPD1_IRQ 0x51 +#define GPD2_IRQ 0x52 +#define GPD3_IRQ 0x53 +#define GPD4_IRQ 0x54 +#define GPD5_IRQ 0x55 +#define GPD6_IRQ 0x56 +#define GPD7_IRQ 0x57 +#define GPD8_IRQ 0x58 +#define GPD9_IRQ 0x59 +#define GPD10_IRQ 0x5a +#define GPD11_IRQ 0x5b + +/* Register defines. */ +#define PAD_OWN_REG_OFFSET 0x20 +#define PAD_OWN_PADS_PER 8 +#define PAD_OWN_WIDTH_PER 4 +#define PAD_OWN_MASK 0x03 +#define PAD_OWN_HOST 0x00 +#define PAD_OWN_ME 0x01 +#define PAD_OWN_ISH 0x02 +#define HOSTSW_OWN_REG_OFFSET 0xd0 +#define HOSTSW_OWN_PADS_PER 24 +#define HOSTSW_OWN_ACPI 0 +#define HOSTSW_OWN_GPIO 1 +#define PAD_CFG_DW_OFFSET 0x400 + /* PADRSTCFG - when to reset the pad config */ +#define PADRSTCFG_SHIFT 30 +#define PADRSTCFG_MASK 0x3 +#define PADRSTCFG_DSW_PWROK 0 +#define PADRSTCFG_DEEP 1 +#define PADRSTCFG_PLTRST 2 +#define PADRSTCFG_RSMRST 3 + /* RXPADSTSEL - raw signal or internal state */ +#define RXPADSTSEL_SHIFT 29 +#define RXPADSTSEL_MASK 0x1 +#define RXPADSTSEL_RAW 0 +#define RXPADSTSEL_INTERNAL 1 + /* RXRAW1 - drive 1 instead instead of pad value */ +#define RXRAW1_SHIFT 28 +#define RXRAW1_MASK 0x1 +#define RXRAW1_NO 0 +#define RXRAW1_YES 1 + /* RXEVCFG - Interrupt and wake types */ +#define RXEVCFG_SHIFT 25 +#define RXEVCFG_MASK 0x3 +#define RXEVCFG_LEVEL 0 +#define RXEVCFG_EDGE 1 +#define RXEVCFG_DRIVE0 2 + /* PREGFRXSEL - use filtering on Rx pad */ +#define PREGFRXSEL_SHIFT 24 +#define PREGFRXSEL_MASK 0x1 +#define PREGFRXSEL_NO 0 +#define PREGFRXSEL_YES 1 + /* RXINV - invert signal to SMI, SCI, NMI, or IRQ routing. */ +#define RXINV_SHIFT 23 +#define RXINV_MASK 0x1 +#define RXINV_NO 0 +#define RXINV_YES 1 + /* GPIROUTIOXAPIC - route to io-xapic or not */ +#define GPIROUTIOXAPIC_SHIFT 20 +#define GPIROUTIOXAPIC_MASK 0x1 +#define GPIROUTIOXAPIC_NO 0 +#define GPIROUTIOXAPIC_YES 1 + /* GPIROUTSCI - route to SCI */ +#define GPIROUTSCI_SHIFT 19 +#define GPIROUTSCI_MASK 0x1 +#define GPIROUTSCI_NO 0 +#define GPIROUTSCI_YES 1 + /* GPIROUTSMI - route to SMI */ +#define GPIROUTSMI_SHIFT 18 +#define GPIROUTSMI_MASK 0x1 +#define GPIROUTSMI_NO 0 +#define GPIROUTSMI_YES 1 + /* GPIROUTNMI - route to NMI */ +#define GPIROUTNMI_SHIFT 17 +#define GPIROUTNMI_MASK 0x1 +#define GPIROUTNMI_NO 0 +#define GPIROUTNMI_YES 1 + /* PMODE - mode of pad */ +#define PMODE_SHIFT 10 +#define PMODE_MASK 0x3 +#define PMODE_GPIO 0 +#define PMODE_NF1 1 +#define PMODE_NF2 2 +#define PMODE_NF3 3 + /* GPIORXDIS - Disable Rx */ +#define GPIORXDIS_SHIFT 9 +#define GPIORXDIS_MASK 0x1 +#define GPIORXDIS_NO 0 +#define GPIORXDIS_YES 1 + /* GPIOTXDIS - Disable Tx */ +#define GPIOTXDIS_SHIFT 8 +#define GPIOTXDIS_MASK 0x1 +#define GPIOTXDIS_NO 0 +#define GPIOTXDIS_YES 1 + /* GPIORXSTATE - Internal state after glitch filter */ +#define GPIORXSTATE_SHIFT 1 +#define GPIORXSTATE_MASK 0x1 + /* GPIOTXSTATE - Drive value onto pad */ +#define GPIOTXSTATE_SHIFT 0 +#define GPIOTXSTATE_MASK 0x1 +#define PAD_CFG_DW_OFFSET 0x400 + /* TERM - termination control */ +#define PAD_TERM_SHIFT 10 +#define PAD_TERM_MASK 0xf +#define PAD_TERM_NONE 0 +#define PAD_TERM_5K_PD 2 +#define PAD_TERM_1K_PU 9 +#define PAD_TERM_2K_PU 11 +#define PAD_TERM_5K_PU 10 +#define PAD_TERM_20K_PU 12 +#define PAD_TERM_667_PU 13 +#define PAD_TERM_NATIVE 15 + +#endif /* _SOC_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/gpio_fsp.h b/src/soc/intel/skylake/include/soc/gpio_fsp.h new file mode 100644 index 0000000..cedbf82 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_fsp.h @@ -0,0 +1,512 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_GPIO_FSP_H_ +#define _SOC_GPIO_FSP_H_ + +#include <stdint.h> + +/* + * GPP_Ax to GPP_Gx; + * where x=24 [between GPIO Community A to F] + * = 7 [only for GPIO Community G] + */ +#define MAX_GPIO_NUMBER 151 /* zero based */ +#define GPIO_LIST_END 0xffffffff + +/* + * Skylake LP GPIO PIN to Pad Mapping + */ +#define GPIO_LP_GROUP_A 0x0 +#define GPIO_LP_GROUP_B 0x1 +#define GPIO_LP_GROUP_C 0x2 +#define GPIO_LP_GROUP_D 0x3 +#define GPIO_LP_GROUP_E 0x4 +#define GPIO_LP_GROUP_F 0x5 +#define GPIO_LP_GROUP_G 0x6 + +#define GPIO_LP_GROUP_GPP_A 0x0200 +#define GPIO_LP_GROUP_GPP_B 0x0201 +#define GPIO_LP_GROUP_GPP_C 0x0202 +#define GPIO_LP_GROUP_GPP_D 0x0203 +#define GPIO_LP_GROUP_GPP_E 0x0204 +#define GPIO_LP_GROUP_GPP_F 0x0205 +#define GPIO_LP_GROUP_GPP_G 0x0206 + +#define GPIO_GROUP_SHIFT 16 +#define MAX_GPIO_PIN_PER_GROUP 24 + +/* GPIO TX STATE */ +#define B_PCH_GPIO_TX_STATE 0x0001 +#define N_PCH_GPIO_TX_STATE 0 + +/* Interrupt number */ +#define B_PCH_GPIO_INTSEL 0x7F +#define N_PCH_GPIO_INTSEL 0 + +/* Structure for storing information about registers offset, community, + * maximal pad number, smi status and smi enable for available groups + */ +typedef struct { + u32 community; + u32 padcfgoffset; + u32 padpergroup; + u32 smistsoffset; + u32 smienoffset; +} GPIO_GROUP_INFO; + +/* + * GPIO Community 0 Registers are for GPP_A and GPP_B groups + */ +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 + +/* + * GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups + */ +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 + +/* + * GPIO Community 3 Registers are for GPP_F and GPP_G groups + */ +#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 + +/* + * GPIO Community 2 Registers are for GPP_DSW + */ +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 + +#define READ 0 +#define WRITE 1 + +/* If in GPIO_GROUP_INFO structure certain register doesn't exist + * it will have value equal to NO_REGISTER_PROPERTY + */ +#define NO_REGISTER_PROPERTY (~0u) + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ + GPIO_GET_GROUP_INDEX((pad >> 16))) +#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) + +/* Number of pins used by SerialIo controllers */ +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 + +/* Below defines are based on GPIO_CONFIG structure fields */ +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 + +/* GPIO Pad Mode */ +#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) +#define N_PCH_GPIO_PAD_MODE 10 + +/* For any GpioPad usage in code use GPIO_PAD type*/ +typedef u32 GPIO_PAD; + +/* For any GpioGroup usage in code use GPIO_GROUP type */ +typedef u32 GPIO_GROUP; + +/* + * GPIO configuration structure used for pin programming. + * Structure contains fields that can be used to configure pad. + */ +typedef struct { + /* + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction, OutputState, Interrupt is unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + */ + u32 PadMode : 4; + /* + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + */ + u32 HostSoftPadOwn : 2; + /* + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d + isabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + */ + u32 Direction : 5; + /* + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + */ + u32 OutputState : 2; + /* + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO + A is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + */ + u32 InterruptConfig : 8; + /* + GPIO Power Configuration. + This setting controls Pad Reset Configuration and Power Rail Type. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + */ + u32 PowerConfig : 4; + /* + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + */ + u32 ElectricalConfig : 7; + /* + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + */ + u32 LockConfig : 3; + /* + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + */ + u32 OtherSettings : 2; + u32 RsvdBits : 27; +} GPIO_CONFIG; + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; + +typedef enum { + GpioHardwareDefault = 0x0 +} GPIO_HARDWARE_DEFAULT; + +/* GPIO Pad Mode */ +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9, +} GPIO_PAD_MODE; + +/* Host Software Pad Ownership modes */ +typedef enum { + GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ + GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ + GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ +} GPIO_HOSTSW_OWN; + +/* GPIO Direction */ +typedef enum { + GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ + GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ + GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ + GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ + GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ + GpioDirOut = 0x5, /* Set pad for output only */ + GpioDirNone = 0x7 /* Disable both output and input */ +} GPIO_DIRECTION; + +/* GPIO Output State */ +typedef enum { + GpioOutDefault = 0x0, + GpioOutLow = 0x1, + GpioOutHigh = 0x3 +} GPIO_OUTPUT_STATE; + +/* + * GPIO interrupt configuration + * This setting is applicable only if GPIO is in input mode. + * GPIO_INT_CONFIG allows to choose which interrupt is generted + * (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). + * Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to + * GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel + * If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + * Not all GPIO are capable of generating an SMI or NMI interrupt + */ +typedef enum { + GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ + GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ + GpioIntNmi = 0x3, /* Enable NMI interrupt only */ + GpioIntSmi = 0x5, /* Enable SMI interrupt only */ + GpioIntSci = 0x9, /* Enable SCI interrupt only */ + GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ + GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ + GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ + GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ + GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ +} GPIO_INT_CONFIG; + +/* + * GPIO Power Configuration + * GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified + * Pad Register fields). + */ +typedef enum { + GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ + GpioResetPwrGood = 0x1, /* Powergood reset */ + GpioResetDeep = 0x3, /* Deep GPIO Reset */ + GpioResetNormal = 0x5, /* GPIO Reset */ + GpioResetResume = 0x7 /* Resume Reset */ +} GPIO_RESET_CONFIG; + +/* + * GPIO Electrical Configuration + * Set GPIO termination and Pad Tolerance (applicable only for some pads) + * Field from GpioTermDefault to GpioTermNative can be OR'ed with + * GpioTolerance1v8. + */ +typedef enum { + GpioTermDefault = 0x0, /* Leave termination setting unmodified */ + GpioTermNone = 0x1, /* none */ + GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ + GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ + GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ + GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ + GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ + GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ + GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ + GpioTermNative = 0x1F, /* Native function for pads termination */ + GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ + GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ +} GPIO_ELECTRICAL_CONFIG; + +/* + * GPIO LockConfiguration + * Set GPIO configuration lock and output state lock + * GpioLockPadConfig and GpioLockOutputState can be OR'ed + */ +typedef enum { + GpioLockDefault = 0x0, /* Leave lock setting unmodified */ + GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ + GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ +} GPIO_LOCK_CONFIG; + +/* + * Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often + * settings and for future extensions Supported settings: + * - RX raw override to '1' - allows to override input value to '1' + * This is applicable only if in input mode (both in GPIO and native usage) + * The override takes place at the internal pad state directly from buffer + * and before the RXINV. + */ +typedef enum { + GpioRxRaw1Default = 0x0, /* Use default input override value */ + GpioRxRaw1Dis = 0x1, /* Don't override input */ + GpioRxRaw1En = 0x3 /* Override input to '1' */ +} GPIO_OTHER_CONFIG; + +/* + * LP GPIO pins: Use below for functions from PCH GPIO Lib which + * require GpioPad as argument. Encoding used here + * has all information required by library functions + */ +#define GPIO_LP_GPP_A0 0x02000000 +#define GPIO_LP_GPP_A1 0x02000001 +#define GPIO_LP_GPP_A2 0x02000002 +#define GPIO_LP_GPP_A3 0x02000003 +#define GPIO_LP_GPP_A4 0x02000004 +#define GPIO_LP_GPP_A5 0x02000005 +#define GPIO_LP_GPP_A6 0x02000006 +#define GPIO_LP_GPP_A7 0x02000007 +#define GPIO_LP_GPP_A8 0x02000008 +#define GPIO_LP_GPP_A9 0x02000009 +#define GPIO_LP_GPP_A10 0x0200000A +#define GPIO_LP_GPP_A11 0x0200000B +#define GPIO_LP_GPP_A12 0x0200000C +#define GPIO_LP_GPP_A13 0x0200000D +#define GPIO_LP_GPP_A14 0x0200000E +#define GPIO_LP_GPP_A15 0x0200000F +#define GPIO_LP_GPP_A16 0x02000010 +#define GPIO_LP_GPP_A17 0x02000011 +#define GPIO_LP_GPP_A18 0x02000012 +#define GPIO_LP_GPP_A19 0x02000013 +#define GPIO_LP_GPP_A20 0x02000014 +#define GPIO_LP_GPP_A21 0x02000015 +#define GPIO_LP_GPP_A22 0x02000016 +#define GPIO_LP_GPP_A23 0x02000017 +#define GPIO_LP_GPP_B0 0x02010000 +#define GPIO_LP_GPP_B1 0x02010001 +#define GPIO_LP_GPP_B2 0x02010002 +#define GPIO_LP_GPP_B3 0x02010003 +#define GPIO_LP_GPP_B4 0x02010004 +#define GPIO_LP_GPP_B5 0x02010005 +#define GPIO_LP_GPP_B6 0x02010006 +#define GPIO_LP_GPP_B7 0x02010007 +#define GPIO_LP_GPP_B8 0x02010008 +#define GPIO_LP_GPP_B9 0x02010009 +#define GPIO_LP_GPP_B10 0x0201000A +#define GPIO_LP_GPP_B11 0x0201000B +#define GPIO_LP_GPP_B12 0x0201000C +#define GPIO_LP_GPP_B13 0x0201000D +#define GPIO_LP_GPP_B14 0x0201000E +#define GPIO_LP_GPP_B15 0x0201000F +#define GPIO_LP_GPP_B16 0x02010010 +#define GPIO_LP_GPP_B17 0x02010011 +#define GPIO_LP_GPP_B18 0x02010012 +#define GPIO_LP_GPP_B19 0x02010013 +#define GPIO_LP_GPP_B20 0x02010014 +#define GPIO_LP_GPP_B21 0x02010015 +#define GPIO_LP_GPP_B22 0x02010016 +#define GPIO_LP_GPP_B23 0x02010017 +#define GPIO_LP_GPP_C0 0x02020000 +#define GPIO_LP_GPP_C1 0x02020001 +#define GPIO_LP_GPP_C2 0x02020002 +#define GPIO_LP_GPP_C3 0x02020003 +#define GPIO_LP_GPP_C4 0x02020004 +#define GPIO_LP_GPP_C5 0x02020005 +#define GPIO_LP_GPP_C6 0x02020006 +#define GPIO_LP_GPP_C7 0x02020007 +#define GPIO_LP_GPP_C8 0x02020008 +#define GPIO_LP_GPP_C9 0x02020009 +#define GPIO_LP_GPP_C10 0x0202000A +#define GPIO_LP_GPP_C11 0x0202000B +#define GPIO_LP_GPP_C12 0x0202000C +#define GPIO_LP_GPP_C13 0x0202000D +#define GPIO_LP_GPP_C14 0x0202000E +#define GPIO_LP_GPP_C15 0x0202000F +#define GPIO_LP_GPP_C16 0x02020010 +#define GPIO_LP_GPP_C17 0x02020011 +#define GPIO_LP_GPP_C18 0x02020012 +#define GPIO_LP_GPP_C19 0x02020013 +#define GPIO_LP_GPP_C20 0x02020014 +#define GPIO_LP_GPP_C21 0x02020015 +#define GPIO_LP_GPP_C22 0x02020016 +#define GPIO_LP_GPP_C23 0x02020017 +#define GPIO_LP_GPP_D0 0x02030000 +#define GPIO_LP_GPP_D1 0x02030001 +#define GPIO_LP_GPP_D2 0x02030002 +#define GPIO_LP_GPP_D3 0x02030003 +#define GPIO_LP_GPP_D4 0x02030004 +#define GPIO_LP_GPP_D5 0x02030005 +#define GPIO_LP_GPP_D6 0x02030006 +#define GPIO_LP_GPP_D7 0x02030007 +#define GPIO_LP_GPP_D8 0x02030008 +#define GPIO_LP_GPP_D9 0x02030009 +#define GPIO_LP_GPP_D10 0x0203000A +#define GPIO_LP_GPP_D11 0x0203000B +#define GPIO_LP_GPP_D12 0x0203000C +#define GPIO_LP_GPP_D13 0x0203000D +#define GPIO_LP_GPP_D14 0x0203000E +#define GPIO_LP_GPP_D15 0x0203000F +#define GPIO_LP_GPP_D16 0x02030010 +#define GPIO_LP_GPP_D17 0x02030011 +#define GPIO_LP_GPP_D18 0x02030012 +#define GPIO_LP_GPP_D19 0x02030013 +#define GPIO_LP_GPP_D20 0x02030014 +#define GPIO_LP_GPP_D21 0x02030015 +#define GPIO_LP_GPP_D22 0x02030016 +#define GPIO_LP_GPP_D23 0x02030017 +#define GPIO_LP_GPP_E0 0x02040000 +#define GPIO_LP_GPP_E1 0x02040001 +#define GPIO_LP_GPP_E2 0x02040002 +#define GPIO_LP_GPP_E3 0x02040003 +#define GPIO_LP_GPP_E4 0x02040004 +#define GPIO_LP_GPP_E5 0x02040005 +#define GPIO_LP_GPP_E6 0x02040006 +#define GPIO_LP_GPP_E7 0x02040007 +#define GPIO_LP_GPP_E8 0x02040008 +#define GPIO_LP_GPP_E9 0x02040009 +#define GPIO_LP_GPP_E10 0x0204000A +#define GPIO_LP_GPP_E11 0x0204000B +#define GPIO_LP_GPP_E12 0x0204000C +#define GPIO_LP_GPP_E13 0x0204000D +#define GPIO_LP_GPP_E14 0x0204000E +#define GPIO_LP_GPP_E15 0x0204000F +#define GPIO_LP_GPP_E16 0x02040010 +#define GPIO_LP_GPP_E17 0x02040011 +#define GPIO_LP_GPP_E18 0x02040012 +#define GPIO_LP_GPP_E19 0x02040013 +#define GPIO_LP_GPP_E20 0x02040014 +#define GPIO_LP_GPP_E21 0x02040015 +#define GPIO_LP_GPP_E22 0x02040016 +#define GPIO_LP_GPP_E23 0x02040017 +#define GPIO_LP_GPP_F0 0x02050000 +#define GPIO_LP_GPP_F1 0x02050001 +#define GPIO_LP_GPP_F2 0x02050002 +#define GPIO_LP_GPP_F3 0x02050003 +#define GPIO_LP_GPP_F4 0x02050004 +#define GPIO_LP_GPP_F5 0x02050005 +#define GPIO_LP_GPP_F6 0x02050006 +#define GPIO_LP_GPP_F7 0x02050007 +#define GPIO_LP_GPP_F8 0x02050008 +#define GPIO_LP_GPP_F9 0x02050009 +#define GPIO_LP_GPP_F10 0x0205000A +#define GPIO_LP_GPP_F11 0x0205000B +#define GPIO_LP_GPP_F12 0x0205000C +#define GPIO_LP_GPP_F13 0x0205000D +#define GPIO_LP_GPP_F14 0x0205000E +#define GPIO_LP_GPP_F15 0x0205000F +#define GPIO_LP_GPP_F16 0x02050010 +#define GPIO_LP_GPP_F17 0x02050011 +#define GPIO_LP_GPP_F18 0x02050012 +#define GPIO_LP_GPP_F19 0x02050013 +#define GPIO_LP_GPP_F20 0x02050014 +#define GPIO_LP_GPP_F21 0x02050015 +#define GPIO_LP_GPP_F22 0x02050016 +#define GPIO_LP_GPP_F23 0x02050017 +#define GPIO_LP_GPP_G0 0x02060000 +#define GPIO_LP_GPP_G1 0x02060001 +#define GPIO_LP_GPP_G2 0x02060002 +#define GPIO_LP_GPP_G3 0x02060003 +#define GPIO_LP_GPP_G4 0x02060004 +#define GPIO_LP_GPP_G5 0x02060005 +#define GPIO_LP_GPP_G6 0x02060006 +#define GPIO_LP_GPP_G7 0x02060007 +#define GPIO_LP_GPD0 0x02070000 +#define GPIO_LP_GPD1 0x02070001 +#define GPIO_LP_GPD2 0x02070002 +#define GPIO_LP_GPD3 0x02070003 +#define GPIO_LP_GPD4 0x02070004 +#define GPIO_LP_GPD5 0x02070005 +#define GPIO_LP_GPD6 0x02070006 +#define GPIO_LP_GPD7 0x02070007 +#define GPIO_LP_GPD8 0x02070008 +#define GPIO_LP_GPD9 0x02070009 +#define GPIO_LP_GPD10 0x0207000A +#define GPIO_LP_GPD11 0x0207000B + +#define END_OF_GPIO_TABLE 0xFFFFFFFF +#endif

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New patch to review for coreboot: libpayload: usb: don't prematurely free the usb device
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11173 -gerrit commit 3568d444941ddf0fd066755f7bbe344790273aa8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 31 17:08:00 2015 -0500 libpayload: usb: don't prematurely free the usb device Before the controller's destroy_device() could interrogate the usbdev_t object usb_detach_device() was freeing and NULLing out the pointer. That results in all callers who needed that object to start accessing random bits of memory. This eventually led into free()ing memory it shouldn't which corrupted the allocator's state. Eventually, all forward progress was lost by way of a single ended linked list turning into a circular list. The culprit seems to be a bad merge in commit e00ba21. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can boot into OS now w/o "hanging" on glados. Original-Change-Id: I86dcaa1dbaf112ac6782e90dad40f0932f273a1f Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290048 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9135eb0f798bf7dbeccc7a033c3f8471720a0de5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/drivers/usb/usb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 69d1c39..ffbe005 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -605,10 +605,12 @@ usb_detach_device(hci_t *controller, int devno) been called yet by the usb class driver */ if (controller->devices[devno]) { controller->devices[devno]->destroy (controller->devices[devno]); - free(controller->devices[devno]); - controller->devices[devno] = NULL; if (controller->destroy_device) controller->destroy_device(controller, devno); + /* Tear down the device itself *after* destroy_device() + * has had a chance to interoogate it. */ + free(controller->devices[devno]); + controller->devices[devno] = NULL; } }

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New patch to review for coreboot: skylake: fix serial port with new code base
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11172 -gerrit commit 67beeef7cc61f2617a691bf87a2f103edc77a16f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 16:52:56 2015 -0500 skylake: fix serial port with new code base Many Kconfig options changed in coreboot.org since skylake was first started. Fix Kconfig option name changes, and also provide a common option, UART_DEBUG that can be selected to select all the necessary options. Note: It's still a requirement to manually unset the 8250IO option because that's unconditionally set. BUG=chrome-os-partner:43419 BUG=chrome-os-partner:43463 BRANCH=None TEST=Built glados. Booted into kernel. Kernel reboots somewhere. Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289951 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 12 ++++++--- src/soc/intel/skylake/Makefile.inc | 3 +++ src/soc/intel/skylake/include/soc/iomap.h | 3 +++ src/soc/intel/skylake/romstage/romstage.c | 2 +- src/soc/intel/skylake/romstage/uart.c | 11 ++++++--- src/soc/intel/skylake/uart.c | 9 ++++--- src/soc/intel/skylake/uart_debug.c | 41 +++++++++++++++++++++++++++++++ 7 files changed, 69 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 92bae39..e2c43f0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -188,12 +188,16 @@ config SMM_TSEG_SIZE hex default 0x800000 -config TTYS0_BASE - hex - default 0xfe034000 - config VGA_BIOS_ID string default "8086,0406" +config UART_DEBUG + bool "Enable UART debug port." + default y if CONSOLE_SERIAL + default n + select DRIVERS_UART + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index af299c3..9fa9503 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-y += smbus_common.c romstage-y += tsc_freq.c +romstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c @@ -46,6 +47,7 @@ ramstage-y += smmrelocate.c ramstage-y += systemagent.c ramstage-y += tsc_freq.c ramstage-y += uart.c +ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += xhci.c smm-y += cpu_info.c @@ -57,6 +59,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c smm-y += tsc_freq.c +smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/arch/x86/include/ CPPFLAGS_common += -I$(src)/soc/intel/skylake diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c478daf..764e966 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -27,6 +27,9 @@ #define PCH_PCR_BASE_ADDRESS 0xfd000000 #define PCH_BCR_BASE_SIZE 0x1000000 +#define UART_DEBUG_BASE_ADDRESS 0xfe034000 +#define UART_DEBUG_BASE_SIZE 0x1000 + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 04ffa3e..af9c78b 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,7 +50,7 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32)) + if (IS_ENABLED(CONFIG_UART_DEBUG)) pch_uart_init(); } diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index afc8c63..4dad8f6 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <console/uart.h> #include <device/pci_def.h> #include <stdint.h> #include <soc/pci_devs.h> @@ -33,7 +34,7 @@ void pch_uart_init(void) { device_t dev = PCH_DEV_UART2; u32 tmp; - u8 *base = (u8 *)CONFIG_TTYS0_BASE; + u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE); /* Set configured UART2 base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); @@ -49,7 +50,11 @@ void pch_uart_init(void) SIO_REG_PPR_RESETS_IDMA; write32(base + SIO_REG_PPR_RESETS, tmp); - /* Set M and N divisor inputs and enable clock */ + /* + * Set M and N divisor inputs and enable clock. + * Main reference frequency to UART is: + * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz + */ tmp = read32(base + SIO_REG_PPR_CLOCK); tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | (SIO_REG_PPR_CLOCK_N_DIV << 16) | @@ -57,7 +62,7 @@ void pch_uart_init(void) write32(base + SIO_REG_PPR_CLOCK, tmp); /* Put UART2 in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32)) + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 9304118..c93f5c0 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -18,11 +18,11 @@ * Foundation, Inc. */ -#include <console/uart.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <stdlib.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -36,10 +36,11 @@ static void pch_uart_read_resources(struct device *dev) pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) && - pch_uart_is_debug(dev)) { + if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - res->size = 0x1000; + /* Need to set the base and size for the resource allocator. */ + res->base = UART_DEBUG_BASE_ADDRESS; + res->size = UART_DEBUG_BASE_SIZE; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c new file mode 100644 index 0000000..0328507 --- /dev/null +++ b/src/soc/intel/skylake/uart_debug.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stddef.h> +#include <console/uart.h> +#include <soc/iomap.h> +#include <soc/serialio.h> + +unsigned int uart_platform_refclk(void) +{ + /* + * Set M and N divisor inputs and enable clock. + * Main reference frequency to UART is: + * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz + * The different order below is to handle integer math overflow. + */ + return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV; +} + +uintptr_t uart_platform_base(int idx) +{ + /* Same base address for all debug port usage. In reality UART2 + * is currently only supported. */ + return UART_DEBUG_BASE_ADDRESS; +}

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New patch to review for coreboot: glados: Enable wake from EC via LAN_WAKE#
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11171 -gerrit commit 5ed9cafcc55c15afd18079e762215935c7bf3dd3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jul 24 15:39:31 2015 -0700 glados: Enable wake from EC via LAN_WAKE# Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#. Report the EC wake pin LAN_WAKE as GPE[112]. BUG=chrome-os-partner:43079 BRANCH=none TEST=suspend/resume on glados with wake from keyboard Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288921 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 3 +++ src/mainboard/google/glados/devicetree.cb | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index 7c26e42..53001e4 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -29,6 +29,9 @@ Scope (\_SB) { Return (\_SB.PCI0.LPCB.EC0.LIDS) } + + /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ + Name (_PRW, Package(){ 112, 5 }) /* LAN_WAKE_EN */ } Device (PWRB) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 6f89063..b48556f 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -3,6 +3,7 @@ chip soc/intel/skylake # Enable deep Sx states register "deep_s3_enable" = "1" register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \

1 0

New patch to review for coreboot: skylake: Add Deep Sx configuration for wake pins
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11170 -gerrit commit 2ca454a325c3b094d29e6a4e0efc22221985988d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jul 24 15:37:13 2015 -0700 skylake: Add Deep Sx configuration for wake pins Add support for enabling various pins in Deep Sx by setting a register in the mainboard devicetree. BUG=chrome-os-partner:43079 BRANCH=none TEST=build and boot on glados Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288920 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/chip.h | 9 +++++++++ src/soc/intel/skylake/include/soc/pmc.h | 5 +++++ src/soc/intel/skylake/pmc.c | 12 ++++++++++++ 3 files changed, 26 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d397c4e..c04e9f8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -21,6 +21,7 @@ #include <stdint.h> #include <soc/pci_devs.h> +#include <soc/pmc.h> #include <soc/serialio.h> #ifndef _SOC_CHIP_H_ @@ -112,6 +113,14 @@ struct soc_intel_skylake_config { int deep_s3_enable; int deep_s5_enable; + /* + * Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin + */ + uint32_t deep_sx_config; + /* TCC activation offset */ int tcc_offset; diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 699e795..5b5d663 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -55,6 +55,11 @@ #define S5_PWRGATE_POL 0x30 #define S5DC_GATE_SUS (1 << 15) #define S5AC_GATE_SUS (1 << 14) +#define DSX_CFG 0x34 +#define DSX_CFG_MASK 0x7 +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_EN_AC_PRESENT_PIN (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) #define GBLRST_CAUSE0 0x124 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 934c130..b95441c 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -217,6 +217,17 @@ static void config_deep_s3(int on) config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS | S3AC_GATE_SUS, 3, on); } +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + static void pmc_init(struct device *dev) { config_t *config = dev->chip_info; @@ -231,6 +242,7 @@ static void pmc_init(struct device *dev) config_deep_s3(config->deep_s3_enable); config_deep_s5(config->deep_s5_enable); + config_deep_sx(config->deep_sx_config); } static struct device_operations device_ops = {

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New patch to review for coreboot: uart8250mem: provide uart_fill_lb()
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11169 -gerrit commit 38e8404c5b5acc4af54dd76f393223ddb9653c50 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 16:47:18 2015 -0500 uart8250mem: provide uart_fill_lb() There was no implementation for uart_fill_lb() in the 8250mem driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are employed then the build doesn't fail. BUG=chrome-os-partner:43419 BRANCH=None TEST=Built with glados using 8250MEM Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289899 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Change-Id: I972b069a4def666f509268816de91ed6c0f655d9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/uart/uart8250mem.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index d276fd0..fb7327e 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -19,9 +19,11 @@ */ #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <console/uart.h> #include <device/device.h> #include <delay.h> +#include <rules.h> #include <stdint.h> #include "uart8250reg.h" @@ -146,3 +148,20 @@ void uart_tx_flush(int idx) return; uart8250_mem_tx_flush(base); } + +#if ENV_RAMSTAGE +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) + serial.regwidth = sizeof(uint32_t); + else + serial.regwidth = sizeof(uint8_t); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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New patch to review for coreboot: skylake: remove CBFS_SIZE option in SoC directory
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11168 -gerrit commit cdc6c5a5e6b99789329361bfbc009264a301fee8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 13:34:29 2015 -0500 skylake: remove CBFS_SIZE option in SoC directory CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. Remove from the soc Kconfig and add a default Kconfig for SOC_INTEL_SKYLAKE. BUG=chrome-os-partner:43419 BRANCH=None TEST=built glados Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289833 Original-Reviewed-by: Martin Roth <martinroth(a)google.com> Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 11 ----------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 8078a76..9c01687 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -353,6 +353,7 @@ config CBFS_SIZE NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL + default 0x200000 if SOC_INTEL_SKYLAKE default ROM_SIZE help This is the part of the ROM actually managed by CBFS, located at the diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d21fe3a..92bae39 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -70,17 +70,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "soc/intel/skylake/bootblock/pch.c" -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - default 0x200000 - help - The firmware image has to store more than just coreboot, including: - - a firmware descriptor - - Intel Management Engine firmware - - MRC cache information - This option allows to limit the size of the CBFS portion in the - firmware image. - config CPU_ADDR_BITS int default 36

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New patch to review for coreboot: skylake: fix garbled patch from upstream
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11167 -gerrit commit ee0f6ee6cc1b49cca37ab1043c13d4f5746e1b9f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 10:36:34 2015 -0500 skylake: fix garbled patch from upstream In the review process for http://review.coreboot.org/#/c/11052/ the code was mangled and the result was unbuildable code. Fix this. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can actually build bootblock. Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289788 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/bootblock/cpu.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 2e3e000..6c5ab4f 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -178,8 +178,16 @@ static void check_for_clean_reset(void) soft_reset(); } -static int need_microcode_update(void) +static void patch_microcode(void) { + const struct microcode *patch; + u32 current_rev; + msr_t msr; + + patch = intel_microcode_find(); + + current_rev = read_microcode_rev(); + /* If PRMRR/SGX is supported the FIT microcode load step will set * msr 0x08b with the Patch revision id one less than the id in the * microcode binary. The PRMRR support is indicated in the MSR @@ -187,24 +195,15 @@ static int need_microcode_update(void) * same microcode during early cpu initialization. */ msr = rdmsr(MTRRcap_MSR); - return (msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1); + if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) + intel_update_microcode_from_cbfs(); } static void bootblock_cpu_init(void) { - const struct microcode *patch; - u32 current_rev; - msr_t msr; - /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - if (need_microcode_update()) - intel_update_microcode_from_cbfs(); + patch_microcode(); }

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New patch to review for coreboot: x86: parameterize asl_template for CBFS inclusion
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11166 -gerrit commit 8b2f34e544d89b1d29ff57f4fddea58a98fee13f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 12:44:58 2015 -0500 x86: parameterize asl_template for CBFS inclusion The asl_template previously unconditionally included dsdt.aml. However, COMPILE_IN_DSDT=y results in the dsdt.aml being linked directly into ramstage. Thus the information is duplicated. The inclusion of this file unconditionally throws some errors as certain assets need to be included in CBFS. However, as there isn't fine-grained ordering control in how files are added fixed resource requirements for other assets collide result in failure to build. To remedy both things, provide a 2nd argument to asl_template which defaults to 'y' for CBFS addition. In the COMPILE_IN_DSDT=y case pass 'n' so that dsdt.aml is no longer added. BUG=chrome-os-partner:43419 BRANCH=None TEST=For glados: Built with COMPILE_IN_DSDT=y. dsdt.aml not included. Built with COMPILE_IN_DSDT=n. dsdt.aml was included. Original-Change-Id: I4767e5be2915c1732251fe415017f30314c5efc9 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289840 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id1828627ba0a034eb05b2fe23be76e19f3040444 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 4 +++- src/arch/x86/Makefile.inc | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index ef9b522..c789721 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -188,11 +188,13 @@ endef ####################################################################### # Add handler to compile ACPI's ASL +# arg1: base file name +# arg2: y or n for including in cbfs. defaults to y define asl_template $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-file = $(obj)/$(1).aml $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-type = raw $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-compression = none -cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml +cbfs-files-$(if $(2),$(2),y) += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d5b320f..d0b276d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -283,7 +283,11 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c +ifeq ($(CONFIG_COMPILE_IN_DSDT),y) +$(eval $(call asl_template,dsdt,n)) +else $(eval $(call asl_template,dsdt)) +endif ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c endif

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New patch to review for coreboot: soc/common/intel: Reset is not dependend upon FSP
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11165 -gerrit commit 4ac986a2509a55364115ed3c421d1bc65d1f871a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 20 17:24:44 2015 -0700 soc/common/intel: Reset is not dependend upon FSP Remove dependency of common reset code on FSP BRANCH=none BUG=None TEST=Build and run on Braswell and Skylake Original-Change-Id: I00052f29326f691b6d56d2349f99815cafff5848 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286932 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7f59f0aad7dfae92df28cf20fff2d5a684795d22 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/common/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 68d3f5e..dfbc6bb 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -66,7 +66,6 @@ config SOC_INTEL_COMMON_FSP_ROMSTAGE config SOC_INTEL_COMMON_RESET bool default n - depends on PLATFORM_USES_FSP1_1 config SOC_INTEL_COMMON_STACK bool

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coreboot-gerrit August 2015