coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: libpayload: usb: xhci: Fix list of cleared port change bits
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11194 -gerrit commit 7c4fdfc9f24f1ada3c9abf7dffb1d699a48febee Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 7 15:29:41 2015 -0700 libpayload: usb: xhci: Fix list of cleared port change bits The xhci_rh_port_status_changed() function tries to always clear all port status bits, even though most of them don't interest us. This is generally a smart thing to do since not clearing a status bit may cause the controller to not generate any more Port Status Change Events. However, the bitmask we currently use doesn't cover bit 23 (Port Config Error Change) and instead covers bit 16 (Port Link State Write Strobe) which is not really related to this and not a W1C bit. Probably a typo, so let's fix that. BRANCH=None BUG=None TEST=Plugged/unplugged a bunch of USB devices on an XHCI Falco. Original-Change-Id: Ia83f5b72cce094859c0f0e730752d7b5cfa6e1c6 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291842 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I11f5fe38cb70055daf6e866a8ee84ca80488e3bf Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index bcb01ac..d7ba82c 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -53,7 +53,7 @@ xhci_rh_port_status_changed(usbdev_t *const dev, const int port) const int changed = !!(*portsc & (PORTSC_CSC | PORTSC_PRC)); /* always clear all the status change bits */ - *portsc = (*portsc & PORTSC_RW_MASK) | 0x00ef0000; + *portsc = (*portsc & PORTSC_RW_MASK) | 0x00fe0000; return changed; }

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New patch to review for coreboot: fsp1_1: fsp_relocate: use struct region_device and struct prog
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11193 -gerrit commit f8407a9806f1821bd032542123e5b0bd9c792035 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 10:17:33 2015 -0500 fsp1_1: fsp_relocate: use struct region_device and struct prog Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin(a)chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin(a)chroumium.org> --- src/drivers/intel/fsp1_1/fsp_relocate.c | 28 +++++++++++++++++++++++----- src/drivers/intel/fsp1_1/fsp_util.h | 9 ++++++--- src/soc/intel/common/fsp_ramstage.c | 20 +++++++++++--------- 3 files changed, 40 insertions(+), 17 deletions(-) diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c index 08e1eb8..3e52608 100644 --- a/src/drivers/intel/fsp1_1/fsp_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -482,15 +482,33 @@ static FSP_INFO_HEADER *fsp_relocate_in_place(void *fsp, size_t size) return relocate_remaining_items(fsp, size, fih_offset); } -FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size) +int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src) { void *new_loc; + void *fih; + size_t size = region_device_sz(fsp_src); new_loc = cbmem_add(CBMEM_ID_REFCODE, size); + if (new_loc == NULL) { - printk(BIOS_ERR, "Unable to load FSP into memory.\n"); - return NULL; + printk(BIOS_ERR, "ERROR: Unable to load FSP into memory.\n"); + return -1; } - memcpy(new_loc, fsp_src, size); - return fsp_relocate_in_place(new_loc, size); + + if (rdev_readat(fsp_src, new_loc, 0, size) != size) { + printk(BIOS_ERR, "ERROR: Can't read FSP's region device.\n"); + return -1; + } + + fih = fsp_relocate_in_place(new_loc, size); + + if (fih == NULL) { + printk(BIOS_ERR, "ERROR: FSP relocation faiulre.\n"); + return -1; + } + + prog_set_area(fsp_relocd, new_loc, size); + prog_set_entry(fsp_relocd, fih, NULL); + + return 0; } diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h index 618317b..fba9116 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.h +++ b/src/drivers/intel/fsp1_1/fsp_util.h @@ -24,6 +24,8 @@ #include <types.h> #include <arch/cpu.h> #include <fsp_gop.h> +#include <program_loading.h> +#include <region.h> /* * The following are functions with prototypes defined in the EDK2 headers. The @@ -63,10 +65,11 @@ void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid, void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_resource_hob(const EFI_GUID *guid); /* - * Relocate FSP entire binary into ram. Returns NULL on error. Otherwise the - * FSP_INFO_HEADER pointer to the relocated FSP. + * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success. + * The FSP source is pointed to by region_device and the relocation information + * is encoded in a struct prog with its entry point set to the FSP info header. */ -FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size); +int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src); /* Additional HOB types not included in the FSP: * #define EFI_HOB_TYPE_HANDOFF 0x0001 diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index 5ccc4ee..1c3c38a 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -286,20 +286,22 @@ static void fsp_cache_save(void) static int fsp_find_and_relocate(void) { - void *fih; - void *data; - size_t length; + struct prog fsp_prog = PROG_INIT(ASSET_REFCODE, "fsp.bin"); + struct region_device fsp_rdev; + uint32_t type = CBFS_TYPE_FSP; - data = cbfs_boot_map_with_leak("fsp.bin", CBFS_TYPE_FSP, &length); - - if (data == NULL) { - printk(BIOS_ERR, "Couldn't find fsp.bin in CBFS.\n"); + if (cbfs_boot_locate(&fsp_rdev, prog_name(&fsp_prog), &type)) { + printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n"); return -1; } - fih = fsp_relocate(data, length); + if (fsp_relocate(&fsp_prog, &fsp_rdev)) { + printk(BIOS_ERR, "ERROR: FSP relocation failed.\n"); + return -1; + } - fsp_update_fih(fih); + /* FSP_INFO_HEADER is set as the program entry. */ + fsp_update_fih(prog_entry(&fsp_prog)); return 0; }

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New patch to review for coreboot: stage_cache: make prog const in stage_cache_add()
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11192 -gerrit commit f135dd7f77c1d49df96c9c96654dea459662a2d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 00:52:13 2015 -0500 stage_cache: make prog const in stage_cache_add() The stage_cache_add() function should not be manipulating the struct prog argument in anyway. Therefore, mark it as const. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4509e478d3c98247b9d776f6534b949d9ba6282c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290721 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ibadc00a9e1cbbf12119def92d77a79077625fb85 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/stage_cache.h | 2 +- src/lib/cbmem_stage_cache.c | 2 +- src/lib/ext_stage_cache.c | 2 +- src/lib/prog_loaders.c | 3 ++- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 5a4c16a..68cfdb7 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -30,7 +30,7 @@ enum { }; /* Cache the loaded stage provided according to the parameters. */ -void stage_cache_add(int stage_id, struct prog *stage); +void stage_cache_add(int stage_id, const struct prog *stage); /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 4a11443..eb5e2b3 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -23,7 +23,7 @@ #include <string.h> /* Stage cache uses cbmem. */ -void stage_cache_add(int stage_id, struct prog *stage) +void stage_cache_add(int stage_id, const struct prog *stage) { struct stage_cache *meta; void *c; diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 4e588f1..bbadb70 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -62,7 +62,7 @@ static void stage_cache_recover(void) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } -void stage_cache_add(int stage_id, struct prog *stage) +void stage_cache_add(int stage_id, const struct prog *stage) { struct imd *imd; const struct imd_entry *e; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 7c00aba..2f4a2c1 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -60,7 +60,8 @@ fail: halt(); } -void __attribute__((weak)) stage_cache_add(int stage_id, struct prog *stage) {} +void __attribute__((weak)) stage_cache_add(int stage_id, + const struct prog *stage) {} void __attribute__((weak)) stage_cache_load_stage(int stage_id, struct prog *stage) {} void __attribute__((weak)) ramstage_cache_invalid(void) {}

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New patch to review for coreboot: Skylake: Add ASL code to enable GPIO controller
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11191 -gerrit commit f8154f312127d624d3b640de6145f8a486f1816a Author: Archana Patni <archana.patni(a)intel.com> Date: Sat Jul 4 00:56:32 2015 +0530 Skylake: Add ASL code to enable GPIO controller This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni(a)intel.com> Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> --- src/soc/intel/skylake/acpi/gpio.asl | 147 +++++++++----------------- src/soc/intel/skylake/include/soc/gpio_defs.h | 5 + src/soc/intel/skylake/include/soc/iomap.h | 6 +- src/soc/intel/skylake/include/soc/irq.h | 2 + 4 files changed, 57 insertions(+), 103 deletions(-) diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 69ee721..3b4740b 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -18,46 +18,64 @@ * Foundation, Inc. */ -Device (GPIO) +#include <soc/irq.h> +#include <soc/iomap.h> +#include <soc/pcr.h> +#include <soc/gpio_defs.h> + +/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */ +Method (PCRR, 2, Serialized) { - // GPIO Controller - Method (_HID) + Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0) + Add (PCH_PCR_BASE_ADDRESS, Local0, Local0) + OperationRegion (PCR0, SystemMemory, Local0, 0x4) + + Field(PCR0, DWordAcc, Lock, Preserve) { - //Sunrisepoint-LP PCH - Return ("INT344B") + Offset(0x00), + DAT0, 32 } + Return (DAT0) +} + +Device (GPIO) +{ + /* GPIO Controller */ + Name (_HID, "INT344B") Name (_UID, 1) Name (RBUF, ResourceTemplate() { - DWordIo (ResourceProducer, - MinFixed, // IsMinFixed - MaxFixed, // IsMaxFixed - PosDecode, // Decode - EntireRange, // ISARanges - 0x00000000, // AddressGranularity - 0x00000000, // AddressMinimum - 0x00000000, // AddressMaximum - 0x00000000, // AddressTranslation - 0x00000000, // RangeLength - , // ResourceSourceIndex - , // ResourceSource - BAR0) - // Disabled due to IRQ storm: http://crosbug.com/p/29548 - //Interrupt (ResourceConsumer, - // Level, ActiveHigh, Shared, , , ) {14} + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0) + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1) + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4) + { + GPIO_IRQ14, + } }) - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, NotSerialized) /* _CRS: Current Resource Settings */ { - CreateDwordField (^RBUF, ^BAR0._MIN, BMIN) - CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) - CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - - Store (GPIO_BASE_SIZE, BLEN) - Store (GPIO_BASE_ADDRESS, BMIN) - Store (Subtract (Add (GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE), 1), BMAX) + CreateDWordField (^RBUF, ^_R0._BAS, COM0) + CreateDWordField (^RBUF, ^_R1._BAS, COM1) + CreateDWordField (^RBUF, ^_R3._BAS, COM3) + CreateDWordField (^RBUF, ^_R4._INT, IRQN) + + Store (Add (PCH_PCR_BASE_ADDRESS, + ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0) + Store (Add (PCH_PCR_BASE_ADDRESS, + ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1) + Store (Add (PCH_PCR_BASE_ADDRESS, + ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3) + Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET), + GPIO_DRIVER_IRQ_ROUTE_MASK), Local0) + + If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { + Store (GPIO_IRQ14, IRQN) + } Else { + Store (GPIO_IRQ15, IRQN) + } Return (RBUF) } @@ -66,73 +84,4 @@ Device (GPIO) { Return (0xF) } - - // GWAK: Setup GPIO as ACPI GPE for Wake - // Arg0: GPIO Number - Method (GWAK, 1, NotSerialized) - { - // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) - - // Local1 = BANK, Local2 = OFFSET - Divide (Arg0, 32, Local2, Local1) - - // - // Set OWNER to ACPI - // - - // Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) - - // GPIO_OWN(BANK) - OperationRegion (IOWN, SystemIO, Local3, 4) - Field (IOWN, AnyAcc, NoLock, Preserve) { - GOWN, 32, - } - - // GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) - - // - // Set ROUTE to SCI - // - - // Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) - - // GPIO_ROUTE(BANK) - OperationRegion (IROU, SystemIO, Local3, 4) - Field (IROU, AnyAcc, NoLock, Preserve) { - GROU, 32, - } - - // GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) - - // - // Set GPnCONFIG to GPIO|INPUT|INVERT - // - - // Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) - - // GPnCONFIG(GPIO) - OperationRegion (GPNC, SystemIO, Local3, 8) - Field (GPNC, AnyAcc, NoLock, Preserve) { - GMOD, 1, // MODE: 0=NATIVE 1=GPIO - , 1, - GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT - GINV, 1, // INVERT: 0=NORMAL 1=INVERT - GLES, 1, // LxEB: 0=EDGE 1=LEVEL - , 24, - ILVL, 1, // INPUT: 0=LOW 1=HIGH - OLVL, 1, // OUTPUT: 0=LOW 1=HIGH - GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID - ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE - } - - Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT - } } diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 61d80bd..625acdb 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -476,4 +476,9 @@ #define PAD_TERM_667_PU 13 #define PAD_TERM_NATIVE 15 +#define MISCCFG_OFFSET 0x10 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 + #endif /* _SOC_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c56b8e4..916719d 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -57,6 +57,8 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +#define GPIO_BASE_SIZE 0x10000 + /* * I/O port address space */ @@ -66,10 +68,6 @@ #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 -/* FIXME: not applicable as there is no I/O space for gpio access. */ -#define GPIO_BASE_ADDRESS 0x1400 -#define GPIO_BASE_SIZE 0x400 - #define TCO_BASE_ADDDRESS 0x400 #define TCO_BASE_SIZE 0x20 diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h index 7f3fd65..430a13c 100644 --- a/src/soc/intel/skylake/include/soc/irq.h +++ b/src/soc/intel/skylake/include/soc/irq.h @@ -17,6 +17,8 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 #define LPSS_I2C0_IRQ 16 #define LPSS_I2C1_IRQ 17 #define LPSS_I2C2_IRQ 18

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New patch to review for coreboot: intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11190 -gerrit commit 55f3a55e100056ff26fcf697529f99199be6fc1a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 23:59:43 2015 -0500 intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/fsp_ramstage.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index b85591d..5ccc4ee 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -18,15 +18,16 @@ * Foundation, Inc. */ +#include <arch/acpi.h> #include <cbmem.h> #include <cbfs.h> #include <console/console.h> #include <fsp_util.h> #include <lib.h> -#include <romstage_handoff.h> #include <soc/intel/common/memmap.h> #include <soc/intel/common/ramstage.h> #include <stage_cache.h> +#include <string.h> #include <timestamp.h> /* SOC initialization after FSP silicon init */ @@ -176,7 +177,7 @@ static FSP_INFO_HEADER *soc_restore_support_code(void) return header->fih; } -static void fsp_run_silicon_init(struct romstage_handoff *handoff) +static void fsp_run_silicon_init(int is_s3_wakeup) { FSP_INFO_HEADER *fsp_info_header; FSP_SILICON_INIT fsp_silicon_init; @@ -209,7 +210,7 @@ static void fsp_run_silicon_init(struct romstage_handoff *handoff) /* Locate VBT and pass to FSP GOP */ if (IS_ENABLED(CONFIG_GOP_SUPPORT)) - load_vbt(handoff->s3_resume, &silicon_init_params); + load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); /* Display the UPD data */ @@ -305,11 +306,9 @@ static int fsp_find_and_relocate(void) void intel_silicon_init(void) { - struct romstage_handoff *handoff; + int is_s3_wakeup = acpi_is_wakeup_s3(); - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff != NULL && handoff->s3_resume) { + if (is_s3_wakeup) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); fsp_update_fih(soc_restore_support_code()); } else { @@ -318,7 +317,7 @@ void intel_silicon_init(void) fsp_cache_save(); } - fsp_run_silicon_init(handoff); + fsp_run_silicon_init(is_s3_wakeup); } /* Initialize the UPD parameters for SiliconInit */

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New patch to review for coreboot: libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11189 -gerrit commit f827e9b800463597b3dafdd0b2edbb0573ad640c Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 7 13:14:20 2015 -0700 libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1 The 1.1 revision of the XHCI specification added an extra 5 bits to the Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use of. Not honoring these bits means we're not allocating as many scratchpad buffers as the controller expects, which means it will interpret some uninitialized values from the end of the pointer array as scratchpad buffer pointers, which obviously doesn't end well. Let's fix that. BRANCH=none BUG=chrome-os-partner:42279 TEST=Makes a USB-related memory corruption issue disappear. Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291681 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci.c | 6 ++++-- payloads/libpayload/drivers/usb/xhci_private.h | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 315efb7..71272c7 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -227,7 +227,8 @@ xhci_init (unsigned long physical_bar) * Let dcbaa[0] point to another array of pointers, sp_ptrs. * The pointers therein point to scratchpad buffers (pages). */ - const size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs; + const size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 | + xhci->capreg->Max_Scratchpad_Bufs_Lo; xhci_debug("max scratchpad bufs: 0x%zx\n", max_sp_bufs); if (max_sp_bufs) { const size_t sp_ptrs_size = max_sp_bufs * sizeof(u64); @@ -417,7 +418,8 @@ xhci_shutdown(hci_t *const controller) #endif if (xhci->sp_ptrs) { - const size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs; + size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 | + xhci->capreg->Max_Scratchpad_Bufs_Lo; for (i = 0; i < max_sp_bufs; ++i) { if (xhci->sp_ptrs[i]) free(phys_to_virt(xhci->sp_ptrs[i])); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 05cf195..f644425 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -348,9 +348,10 @@ typedef struct xhci { struct { unsigned long IST:4; unsigned long ERST_Max:4; - unsigned long:18; + unsigned long:13; + unsigned long Max_Scratchpad_Bufs_Hi:5; unsigned long SPR:1; - unsigned long Max_Scratchpad_Bufs:5; + unsigned long Max_Scratchpad_Bufs_Lo:5; } __attribute__ ((packed)); } __attribute__ ((packed)); union {

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New patch to review for coreboot: libpayload: Do not gate USB_DWC2 on USB_HID
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11188 -gerrit commit b63c4c9e8fe525d5577e0f4fa584c558890cec1c Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 6 14:08:55 2015 -0700 libpayload: Do not gate USB_DWC2 on USB_HID This forward-ports the change from CL:277155 since the Kconfig file was renamed from Config.in. BUG=chrome-os-partner:41416 BRANCH=none TEST=built and booted on Mickey, keyboard works at dev screen Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Ibffa5188df51ecd7b8bdd631d4b767ec64130819 Original-Reviewed-on: https://chromium-review.googlesource.com/291138 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Iebb1da6ec8c7886a6eb9ebcc67b59d617496c555 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- payloads/libpayload/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 5da4f92..64289b3 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -514,7 +514,7 @@ config USB_XHCI_MTK_QUIRK config USB_DWC2 bool "Support for USB DesignWare HCD controllers" - depends on USB && !USB_HID + depends on USB help Select this option if you want to use DesignWare USB 2.0 host controller

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New patch to review for coreboot: libpayload: usb: dwc2: fix short patket transfer
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11187 -gerrit commit 62edd32c8a5d39b6bd99c68221b2a430443cf351 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Fri Jul 24 16:12:42 2015 +0800 libpayload: usb: dwc2: fix short patket transfer If short packet detected, stop this transfer and return the actual transferred size BUG=chrome-os-partner:42817 TEST=Netboot could run well BRANCH=None Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288215 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba) Original-Reviewed-on: https://chromium-review.googlesource.com/291064 Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> --- payloads/libpayload/drivers/usb/dwc2.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index a3979e5..267dea7 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -174,8 +174,6 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) return -HCSTAT_BABBLE; else if (hcint.stall) return -HCSTAT_STALL; - else if (hcint.ack) - return -HCSTAT_ACK; else if (hcint.nyet) return -HCSTAT_NYET; else @@ -209,7 +207,7 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) static int dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, - uint32_t ch_num, u8 *data_buf) + uint32_t ch_num, u8 *data_buf, int *short_pkt) { uint32_t do_copy; int ret; @@ -277,6 +275,10 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, if (do_copy && (dir == EPDIR_IN)) memcpy(data_buf, aligned_buf, transferred); + + if ((short_pkt != NULL) && (dir == EPDIR_IN)) + *short_pkt = (ret > 0) ? 1 : 0; + } /* Save data toggle */ @@ -292,7 +294,8 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, static int dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, - uint32_t ch_num, u8 *data_buf, split_info_t *split) + uint32_t ch_num, u8 *data_buf, split_info_t *split, + int *short_pkt) { dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); hfnum_t hfnum; @@ -311,7 +314,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, /* Handle Start-Split */ ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num, - data_buf); + data_buf, NULL); if (ret < 0) goto out; @@ -326,7 +329,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, /* Handle Complete-Split */ do { ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle, - dir, ch_num, data_buf); + dir, ch_num, data_buf, short_pkt); } while (ret == -HCSTAT_NYET); if (dir == EPDIR_IN) @@ -360,15 +363,17 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, u8 *src, uint8_t skip_nak) { split_info_t split; - int ret, transferred = 0, timeout = 3000; + int ret, short_pkt, transferred = 0, timeout = 3000; ep->toggle = pid; do { + short_pkt = 0; if (dwc2_need_split(ep->dev, &split)) { nak_retry: - ret = dwc2_split_transfer(ep, size, ep->toggle, dir, 0, - src, &split); + ret = dwc2_split_transfer(ep, MIN(ep->maxpacketsize, + size), ep->toggle, dir, 0, src, &split, + &short_pkt); /* * dwc2_split_transfer() waits for the next FullSpeed @@ -380,7 +385,8 @@ nak_retry: goto nak_retry; } } else { - ret = dwc2_do_xfer(ep, size, pid, dir, 0, src); + ret = dwc2_do_xfer(ep, MIN(DMA_SIZE, size), pid, dir, 0, + src, &short_pkt); } if (ret < 0) @@ -389,7 +395,8 @@ nak_retry: size -= ret; src += ret; transferred += ret; - } while (size > 0); + + } while (size > 0 && !short_pkt); return transferred; }

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New patch to review for coreboot: skylake: clear write-1-to-clear fields in power regs
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11186 -gerrit commit 12d7149cc793f3800723d990682cfe26d9db9fcb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 21:04:02 2015 -0500 skylake: clear write-1-to-clear fields in power regs Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/pmc.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index a97f751..2c794ca 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -51,23 +51,25 @@ static const struct reg_script pch_pmc_misc_init_script[] = { REG_SCRIPT_END }; +static const struct reg_script pmc_write1_to_clear_script[] = { + REG_PCI_OR32(GEN_PMCON_A, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), + REG_SCRIPT_END +}; + static void pch_pmc_add_mmio_resources(device_t dev) { struct resource *res; - const u32 default_decode_base = PCH_PCR_BASE_ADDRESS; - /* - * Till PCI enumeration happens we need to allocate the PMC base - * statically. Above the PCR base. - */ - if (PCH_PWRM_BASE_ADDRESS < default_decode_base) { - res = new_resource(dev, PWRMBASE); - res->base = PCH_PWRM_BASE_ADDRESS; - /* 64KB PMC size */ - res->size = 0x10000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; - } + /* Memory-mmapped I/O registers. */ + res = new_resource(dev, PWRMBASE); + res->base = PCH_PWRM_BASE_ADDRESS; + res->size = PCH_PWRM_BASE_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; } static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) @@ -248,6 +250,9 @@ static void pmc_init(struct device *dev) config_deep_s3(config->deep_s3_enable); config_deep_s5(config->deep_s5_enable); config_deep_sx(config->deep_sx_config); + + /* Clear registers that contain write-1-to-clear bits. */ + reg_script_run_on_dev(dev, pmc_write1_to_clear_script); } static struct device_operations device_ops = {

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New patch to review for coreboot: skylake: fix invalid GNVS base address
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11185 -gerrit commit cec20ffb42baf4963b74144a2aec5035a6e9ba9c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 15:33:23 2015 -0500 skylake: fix invalid GNVS base address Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/globalnvs.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 3df40cd..5d07be7 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name (\PICM, 0) // IOAPIC/8259 * we have to fix it up in coreboot's ACPI creation phase. */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */

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coreboot-gerrit August 2015