coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: skylake: enumerate the SMI status fields
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11184 -gerrit commit 9ebd0338c102ad6fd098de865312f5b863b7aa0e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 10:20:53 2015 -0500 skylake: enumerate the SMI status fields Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/pm.h | 24 ++++++++++++++++++ src/soc/intel/skylake/smihandler.c | 45 +++++++++------------------------- 2 files changed, 35 insertions(+), 34 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 0475e20..9409ba2 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -72,6 +72,30 @@ #define EOS (1 << 1) #define GBL_SMI_EN (1 << 0) #define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define SERIAL_IO_SMI_STS_BIT 29 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define UPWRC 0x3c #define UPWRC_WS (1 << 8) #define UPWRC_WE (1 << 1) diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index dddba56..6c95955 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -474,39 +474,16 @@ static void southbridge_smi_monitor(void) typedef void (*smi_handler_t)(void); -static smi_handler_t southbridge_smi[32] = { - NULL, /* [0] reserved */ - NULL, /* [1] reserved */ - NULL, /* [2] BIOS_STS */ - NULL, /* [3] LEGACY_USB_STS */ - southbridge_smi_sleep, /* [4] SLP_SMI_STS */ - southbridge_smi_apmc, /* [5] APM_STS */ - NULL, /* [6] SWSMI_TMR_STS */ - NULL, /* [7] reserved */ - southbridge_smi_pm1, /* [8] PM1_STS */ - southbridge_smi_gpe0, /* [9] GPE0_STS */ - southbridge_smi_gpi, /* [10] GPI_STS */ - southbridge_smi_mc, /* [11] MCSMI_STS */ - NULL, /* [12] DEVMON_STS */ - southbridge_smi_tco, /* [13] TCO_STS */ - southbridge_smi_periodic, /* [14] PERIODIC_STS */ - NULL, /* [15] SERIRQ_SMI_STS */ - NULL, /* [16] SMBUS_SMI_STS */ - NULL, /* [17] LEGACY_USB2_STS */ - NULL, /* [18] INTEL_USB2_STS */ - NULL, /* [19] reserved */ - NULL, /* [20] PCI_EXP_SMI_STS */ - southbridge_smi_monitor, /* [21] MONITOR_STS */ - NULL, /* [22] reserved */ - NULL, /* [23] reserved */ - NULL, /* [24] reserved */ - NULL, /* [25] EL_SMI_STS */ - NULL, /* [26] SPI_STS */ - NULL, /* [27] reserved */ - NULL, /* [28] reserved */ - NULL, /* [29] reserved */ - NULL, /* [30] reserved */ - NULL /* [31] reserved */ +static smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [SMI_ON_SLP_EN_STS_BIT] = southbridge_smi_sleep, + [APM_STS_BIT] = southbridge_smi_apmc, + [PM1_STS_BIT] = southbridge_smi_pm1, + [GPE0_STS_BIT] = southbridge_smi_gpe0, + [GPIO_STS_BIT] = southbridge_smi_gpi, + [MCSMI_STS_BIT] = southbridge_smi_mc, + [TCO_STS_BIT] = southbridge_smi_tco, + [PERIODIC_STS_BIT] = southbridge_smi_periodic, + [MONITOR_STS_BIT] = southbridge_smi_monitor, }; /* @@ -524,7 +501,7 @@ void southbridge_smi_handler(void) smi_sts = clear_smi_status(); /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { + for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) { southbridge_smi[i]();

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New patch to review for coreboot: skylake: set DISB in GEN_PMCON_A register properly
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11183 -gerrit commit f6814c72d765fafafd9759d1077313a0b04436d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 14:04:47 2015 -0500 skylake: set DISB in GEN_PMCON_A register properly DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index b62a288..a97f751 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -47,7 +47,7 @@ static const struct reg_script pch_pmc_misc_init_script[] = { /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), /* Indicate DRAM init done for MRC */ - REG_PCI_OR8(GEN_PMCON_A, DISB), + REG_PCI_OR32(GEN_PMCON_A, DISB), REG_SCRIPT_END };

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New patch to review for coreboot: skylake: fill out gen_pmcon_* bitfields
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11182 -gerrit commit d21947ea0d6f5e6bc178a442de21fe3204a5e9ef Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 14:02:54 2015 -0500 skylake: fill out gen_pmcon_* bitfields Open coding bitfields is really annoying as no one knows what they are unless you have a doc in front of you. Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290336 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/pmc.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/skylake/pmc.c | 13 +++++++++---- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 5b5d663..5774d46 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -32,12 +32,41 @@ #define SCIS_IRQ23 7 #define PWRMBASE 0x48 #define GEN_PMCON_A 0xa0 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define DISB (1 << 23) +#define MEM_SR (1 << 21) +#define MS4V (1 << 18) +#define GBL_RST_STS (1 << 16) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 15) +#define MPHY_CRICLK_GATE_OVER (1 << 14) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 13) +#define ALLOW_SPXB_CG_INC0 (1 << 12) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define ALLOW_L1LOW_C0 (1 << 7) +#define ALLOW_L1LOW_OPI_ON (1 << 6) #define SMI_LOCK (1 << 4) #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) #define SUS_PWR_FLR (1 << 14) +#define WOL_EN_OVRD (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) #define HOST_RST_STS (1 << 9) +#define S4MAW_MASK (0x3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) #define RTC_BATTERY_DEAD (1 << 2) #define PWR_FLR (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index b95441c..b62a288 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -39,12 +39,15 @@ #endif static const struct reg_script pch_pmc_misc_init_script[] = { - /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ - REG_PCI_RMW16(GEN_PMCON_B, ~((3 << 4)|(1 << 10)), - (1 << 3)|(1 << 11)|(1 << 12)), + /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ + REG_PCI_RMW16(GEN_PMCON_B, + ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), + S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | + DIS_SLP_X_STRCH_SUS_UP), + /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), /* Indicate DRAM init done for MRC */ - REG_PCI_OR8(GEN_PMCON_A, (1 << 23)), + REG_PCI_OR8(GEN_PMCON_A, DISB), REG_SCRIPT_END }; @@ -237,6 +240,8 @@ static void pmc_init(struct device *dev) /* Initialize power management */ pch_power_options(); + /* Note that certain bits may be cleared from running script as + * certain bit fields are write 1 to clear. */ reg_script_run_on_dev(dev, pch_pmc_misc_init_script); pch_set_acpi_mode();

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New patch to review for coreboot: glados: enable SMBus device
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11181 -gerrit commit 7e059158139e5c54a448441a52593338300292ac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 11:03:00 2015 -0500 glados: enable SMBus device In order to run with the debug FSP the SMBus device needs to be enabled. Additionally, the TCO block lives within the SMBus device so if TCO is to be employed then the SMBus device needs to be enabled as a prerequisite. BUG=chrome-os-partner:42407 BRANCH=None TEST=Buit and booted into kernel. Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290364 Original-Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index b48556f..2e1cae7 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/skylake register "IshEnable" = "0" register "XdciEnable" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "0" + register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -102,7 +102,7 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio - device pci 1f.4 off end # SMBus Controller + device pci 1f.4 on end # SMBus Controller device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE Controller end

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New patch to review for coreboot: skylake: do not overlap resources
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11180 -gerrit commit 55508b038c7c324498c9f191d7069f63e322ca7e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 10:58:32 2015 -0500 skylake: do not overlap resources FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/iomap.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 764e966..c56b8e4 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -21,6 +21,9 @@ #ifndef _SOC_IOMAP_H_ #define _SOC_IOMAP_H_ +/* + * Memory-mapped I/O registers. + */ #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define MCFG_BASE_SIZE 0x4000000 @@ -54,13 +57,20 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 +/* FIXME: not applicable as there is no I/O space for gpio access. */ #define GPIO_BASE_ADDRESS 0x1400 #define GPIO_BASE_SIZE 0x400 -#define SMBUS_BASE_ADDRESS 0x0400 -#define SMBUS_BASE_SIZE 0x10 +#define TCO_BASE_ADDDRESS 0x400 +#define TCO_BASE_SIZE 0x20 #endif

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New patch to review for coreboot: libpayload: usb: Fixup wrong use of config
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11179 -gerrit commit d2f88af048574da98f2e77fb3d7afa061bbc52fe Author: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Date: Tue Aug 4 14:33:58 2015 +0800 libpayload: usb: Fixup wrong use of config replace CONFIG_LP_XHCI_MTK_QUIRK by CONFIG_LP_USB_XHCI_MTK_QUIRK BRANCH=none BUG=none TEST=Rev0-oak Original-Change-Id: I68f58ed3b02caa7cef8f0f60a4a8f5e9755c97a7 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290522 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I316712e99e0b44d292dab27cf66e26837dc2e957 Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> --- payloads/libpayload/drivers/usb/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index f336f4d..315efb7 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -538,7 +538,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, cur_length = length; packets = 0; length = 0; - } else if (!IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { + } else if (!IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { packets -= (residue + cur_length) / mps; residue = (residue + cur_length) % mps; length -= cur_length; @@ -551,7 +551,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets)); TRB_SET(CH, trb, 1); - if (length && IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { + if (length && IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { /* * For MTK's xHCI controller, TDS defines a number of * packets that remain to be transferred for a TD after

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New patch to review for coreboot: libpayload: xhci: Carry over fixes from Chromium tree
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11178 -gerrit commit 3d675015214d02ca933073fda5165a4748828f55 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 3 14:21:07 2015 -0700 libpayload: xhci: Carry over fixes from Chromium tree This patch re-adds a few fixes that originally went into the chromeos-2013.04 tree. I kinda seem to have slipped them into the backport of Nico's original XHCI patch (crosreview.com/168097) instead of making a new change, which was not very clever and caused them to be forgotten in the later upstreaming wave. Changing internal XHCI error numbers is just a cosmetic change to make them uniquely identifyable in debug output. Bumping the timeout to 3 seconds is an actually important fix since we have seen mass storage devices needing that much in the past. BRANCH=None BUG=None TEST=Diffed payloads/libpayload/drivers/usb between chromeos-2013.04 and chromeos-2015.07, confirmed that no serious differences remain. Original-Change-Id: I03d865dbe536072d23374a49a0136e9f28568f8e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290423 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I5d773d3a23683fb2164916cc046f4a711b8d259e Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci_events.c | 14 +++++++------- payloads/libpayload/drivers/usb/xhci_private.h | 11 ++++++----- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c index 391ebf6..dacb5d86 100644 --- a/payloads/libpayload/drivers/usb/xhci_events.c +++ b/payloads/libpayload/drivers/usb/xhci_events.c @@ -311,15 +311,15 @@ int xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id) { xhci_spew("Waiting for transfer on ID %d EP %d\n", slot_id, ep_id); - /* 2s for all types of transfers */ /* TODO: test, wait longer? */ - unsigned long timeout_us = 2 * 1000 * 1000; - int cc = TIMEOUT; + /* 3s for all types of transfers */ /* TODO: test, wait longer? */ + unsigned long timeout_us = 3 * 1000 * 1000; + int ret = TIMEOUT; while (xhci_wait_for_event_type(xhci, TRB_EV_TRANSFER, &timeout_us)) { if (TRB_GET(ID, xhci->er.cur) == slot_id && TRB_GET(EP, xhci->er.cur) == ep_id) { - cc = -TRB_GET(CC, xhci->er.cur); - if (cc == -CC_SUCCESS || cc == -CC_SHORT_PACKET) - cc = TRB_GET(EVTL, xhci->er.cur); + ret = -TRB_GET(CC, xhci->er.cur); + if (ret == -CC_SUCCESS || ret == -CC_SHORT_PACKET) + ret = TRB_GET(EVTL, xhci->er.cur); xhci_advance_event_ring(xhci); break; } @@ -329,5 +329,5 @@ xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id) if (!timeout_us) xhci_debug("Warning: Timed out waiting for TRB_EV_TRANSFER.\n"); xhci_update_event_dq(xhci); - return cc; + return ret; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 26f7666..05cf195 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -46,11 +46,12 @@ #define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit)) -#define TIMEOUT -1 -#define CONTROLLER_ERROR -2 -#define COMMUNICATION_ERROR -3 -#define OUT_OF_MEMORY -4 -#define DRIVER_ERROR -5 +/* Make these high enough to not collide with negative XHCI CCs */ +#define TIMEOUT -65 +#define CONTROLLER_ERROR -66 +#define COMMUNICATION_ERROR -67 +#define OUT_OF_MEMORY -68 +#define DRIVER_ERROR -69 #define CC_SUCCESS 1 #define CC_TRB_ERROR 5

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New patch to review for coreboot: cbfs: fix printf for 64bit architectures
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11177 -gerrit commit 4c35252717231035a1b8555f1265f72ad554d8d8 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Jul 28 09:21:08 2015 -0700 cbfs: fix printf for 64bit architectures BUG=none BRANCH=smaug TEST=Built for Smaug Original-Change-Id: I7ff577f97252265ca6c96963ca44a6fbd0de9f7a Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290049 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit 9cff308653766ea81978214e99a3d740aff4dbbe) Original-Reviewed-on: https://chromium-review.googlesource.com/290116 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Change-Id: I5dcc17e0a42b46350fe6c398767f8155bdd0fd9d Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- payloads/libpayload/libcbfs/cbfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 9d7d2f1..3e614b6 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -194,8 +194,8 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { void *address = buffer->buffer + buffer->allocated;; - DEBUG("simple_buffer_map(offset=%d, count=%d): " - "allocated=%d, size=%d, last_allocate=%d\n", + DEBUG("simple_buffer_map(offset=%zu, count=%zu): " + "allocated=%zu, size=%zu, last_allocate=%zu\n", offset, count, buffer->allocated, buffer->size, buffer->last_allocate); if (buffer->allocated + count >= buffer->size) @@ -215,7 +215,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // TODO Add simple buffer management so we can free more than last // allocated one. DEBUG("simple_buffer_unmap(address=0x%p): " - "allocated=%d, size=%d, last_allocate=%d\n", + "allocated=%zu, size=%zu, last_allocate=%zu\n", address, buffer->allocated, buffer->size, buffer->last_allocate); if ((buffer->buffer + buffer->allocated - buffer->last_allocate) ==

1 0

New patch to review for coreboot: skylake: use native gpio configuration for uart
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11176 -gerrit commit 7db1b1041456522b565b8aa4568e8d83099df5b3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 24 13:13:46 2015 -0500 skylake: use native gpio configuration for uart Instead of open coding the UART2 gpio configuration use the support library. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289801 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/romstage/uart.c | 63 ++++------------------------------- 1 file changed, 6 insertions(+), 57 deletions(-) diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 4dad8f6..d0d5ada 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -28,7 +28,11 @@ #include <soc/serialio.h> #include <gpio.h> -static void uartgpioinit(u8 hwflowcontrol); +/* UART2 pad configuration. Support RXD and TXD for now. */ +static const struct pad_config uart2_pads[] = { +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; void pch_uart_init(void) { @@ -66,60 +70,5 @@ void pch_uart_init(void) pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); - /* Configure GPIO for UART2 in native mode*/ - uartgpioinit(FALSE); -} - -/* - * GPIO modes - */ -typedef struct { - GPIO_PAD pad; - GPIO_PAD_MODE mode; -} GPIO_PAD_NATIVE_FUNCTION; - -/* - * GPP_C Community for UART2 GPIO - * pin order RXD/TXD/RTSB/CTSB - */ -static const GPIO_PAD_NATIVE_FUNCTION uartgpio[] = { - {GPIO_LP_GPP_C20, GpioPadModeNative1}, - {GPIO_LP_GPP_C21, GpioPadModeNative1}, - {GPIO_LP_GPP_C22, GpioPadModeNative1}, - {GPIO_LP_GPP_C23, GpioPadModeNative1} -}; - -/* - * GPIO config registers - */ -static const GPIO_GROUP_INFO gpio_group_info = { - PID_GPIOCOM1, - R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, - V_PCH_GPIO_GPP_C_PAD_MAX, - R_PCH_PCR_GPIO_GPP_C_SMI_STS, - R_PCH_PCR_GPIO_GPP_C_SMI_EN -}; - -static void uartgpioinit(u8 hwflowcontrol) -{ - u32 index, pinsused, dw0reg, dw0regmask, padcfgreg, padnumber; - - if (hwflowcontrol) - pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER; - else - pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL; - - for (index = 0; index < pinsused; index++) { - padnumber = GPIO_GET_PAD_NUMBER(uartgpio[index].pad); - padcfgreg = 0x8 * padnumber + gpio_group_info.padcfgoffset; - dw0regmask = (uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) - >> GPIO_CONF_PAD_MODE_BIT_POS; - dw0regmask = (GpioHardwareDefault == dw0regmask) ? - 0x0 : B_PCH_GPIO_PAD_MODE; - dw0reg = (((uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) >> - (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); - - pcr_andthenor32(gpio_group_info.community, padcfgreg, - ~(u32)dw0regmask, (u32)dw0reg); - } + gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); }

1 0

New patch to review for coreboot: glados: move to native gpio configuration
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11175 -gerrit commit 7fc91536555ae37b2acda4083ee0978b39e8e178 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 24 13:06:12 2015 -0500 glados: move to native gpio configuration Instead of relying on FSP to do gpio configuration in one place use the native support in coreboot. This also removes the open coded configuration of the memory configuration ids. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289800 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/gpio.h | 448 ++++++++++++-------------------- src/mainboard/google/glados/mainboard.c | 4 + src/mainboard/google/glados/ramstage.c | 2 - src/mainboard/google/glados/spd/spd.c | 45 +--- 4 files changed, 178 insertions(+), 321 deletions(-) diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index 0b18222..dc58e9a 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,293 +22,176 @@ #include <soc/gpio.h> -const GPIO_INIT_CONFIG mainboard_gpio_table[] = { -/* RCIN# */ -{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* LAD0 */ -{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* LAD1 */ -{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioTermNone}}, -/* LAD2 */ -{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* LAD3 */ -{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* LFRAME# */ -{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SERIRQ */ -{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* CLKRUN# */ -{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* CLKOUT_LPC0 */ -{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SUSWARN# tied to SUSACK# */ -{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SUS_STAT# TP27 */ -{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SUSACK# tied to SUSWARN# */ -{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_1P8_SEL */ -{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_PWR_EN# */ -{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* TRACKPAD_INT_L */ -{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, - GpioTermNone}}, -/* SRCCLKREQ1# / WLAN_PCIE_CLKREQ_L */ -{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* SRCCLKREQ2# / KEPLER_PCIE_CLKREQ_L */ -{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* EXT_PWR_GATE# */ -{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* SLP_S0# */ -{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* PLTRST# */ -{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* WLAN_PCIE_WAKE_L */ -{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* SMBCLK (XDP) */ -{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SMBDATA (XDP) */ -{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EC_IN_RW */ -{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, -/* EN_PP3300_KEPLER */ -{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -/* PCH_MEM_CONFIG[0] */ -{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* PCH_MEM_CONFIG[1] */ -{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* PCH_MEM_CONFIG[2] */ -{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* PCH_MEM_CONFIG[3] */ -{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C0_SDA */ -{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C0_SCL */ -{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C1 SDA */ -{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C1 SDA */ -{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* UART2_RXD */ -{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* UART2_TXD */ -{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EN_PP3300_DX_TOUCHSCREEN */ -{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -/* PCH_WP */ -{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, -/* EN_PP3300_DX_EMMC */ -{GPIO_LP_GPP_D5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EN_PP1800_DX_EMMC */ -{GPIO_LP_GPP_D6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* USBA_1_ILIM_SEL_L */ -{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* USBA_2_ILIM_SEL_L */ -{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EN_PP3300_DX_CAM */ -{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* DMIC_CLK1 */ -{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* DMIC_DATA1 */ -{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* DMIC_CLK0 */ -{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* DMIC_DATA0 */ -{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2S_MCLK */ -{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* TPM_PIRQ_L */ -{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* TOUCHSCREEN_INT_L */ -{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, - GpioTermNone}}, -/* USB2_OC0# */ -{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* USB2_OC1# */ -{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* USB2_OC2# */ -{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* USB2_OC3# */ -{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* DDPB_HPD0 */ -{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* DDPC_HPD1 */ -{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* EC_SMI_L */ -{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* EC_SCI_L */ -{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* EDP_HPD */ -{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ /* GPP_A7 */ +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* CLKOUT_LPC1 */ /* GPP_A10 */ +/* PME# */ /* GPP_A11 */ +/* BM_BUSY# */ /* GPP_A12 */ +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ /* GPP_A18 */ +/* ISH_GP1 */ /* GPP_A19 */ +/* ISH_GP2 */ /* GPP_A20 */ +/* ISH_GP3 */ /* GPP_A21 */ +/* ISH_GP4 */ /* GPP_A22 */ +/* ISH_GP5 */ /* GPP_A23 */ +/* CORE_VID0 */ /* GPP_B0 */ +/* CORE_VID1 */ /* GPP_B1 */ +/* VRALERT# */ /* GPP_B2 */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */ +/* CPU_GP3 */ /* GPP_B4 */ +/* SRCCLKREQ0# */ /* GPP_B5 */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* SRCCLKREQ3# */ /* GPP_B8 */ +/* SRCCLKREQ4# */ /* GPP_B9 */ +/* SRCCLKREQ5# */ /* GPP_B10 */ +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ /* GPP_B14 */ +/* GSPI0_CS# */ /* GPP_B15 */ +/* GSPI0_CLK */ PAD_CFG_GPI_APIC(GPP_B16, NONE, DEEP), /* WLAN WAKE */ +/* GSPI0_MISO */ /* GPP_B17 */ +/* GSPI0_MOSI */ /* GPP_B18 */ +/* GSPI1_CS# */ /* GPP_B19 */ +/* GSPI1_CLK */ /* GPP_B20 */ +/* GSPI1_MISO */ /* GPP_B21 */ +/* GSPI1_MOSI */ /* GPP_B22 */ +/* SM1ALERT# */ /* GPP_B23 */ +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ +/* SMBALERT# */ /* GPP_C2 */ +/* SML0CLK */ /* GPP_C3 */ +/* SML0DATA */ /* GPP_C4 */ +/* SML0ALERT# */ /* GPP_C5 */ +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ /* GPP_C7 */ +/* UART0_RXD */ /* GPP_C8 */ +/* UART0_TXD */ /* GPP_C9 */ +/* UART0_RTS# */ /* GPP_C10 */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ + /* GPP_D0 */ + /* GPP_D1 */ + /* GPP_D2 */ + /* GPP_D3 */ +/* FASHTRIG */ /* GPP_D4 */ +/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ +/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ +/* ISH_I2C1_SDA */ /* GPP_D7 */ +/* ISH_I2C1_SCL */ /* GPP_D8 */ + /* GPP_D9 */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* USBA_2_ILIM_SEL_L */ + PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ /* GPP_D13 */ +/* ISH_UART0_TXD */ /* GPP_D14 */ +/* ISH_UART0_RTS# */ /* GPP_D15 */ +/* ISH_UART0_CTS# */ /* GPP_D16 */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 */ + /* GPP_D22 */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ /* GPP_E1 */ +/* SATAXPCIE2 */ /* GPP_E2 */ +/* CPU_GP0 */ /* GPP_E3 */ +/* SATA_DEVSLP0 */ /* GPP_E4 */ +/* SATA_DEVSLP1 */ /* GPP_E5 */ +/* SATA_DEVSLP2 */ /* GPP_E6 */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ +/* SATALED# */ /* GPP_E8 */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* DDPD_HPD2 */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), +/* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ /* GPP_E18 */ +/* DDPB_CTRLDATA */ /* GPP_E19 */ +/* DDPC_CTRLCLK */ /* GPP_E20 */ +/* DDPC_CTRLDATA */ /* GPP_E21 */ + /* GPP_E22 */ + /* GPP_E23 */ /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these * gpio inupts. */ -/* I2S2_SCLK */ -{GPIO_LP_GPP_F0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2S2_SFRM */ -{GPIO_LP_GPP_F1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2S2_TXD */ -{GPIO_LP_GPP_F2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2S2_RXD */ -{GPIO_LP_GPP_F3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C4_SDA */ -{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* I2C4_SCL */ -{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* MIC_INT_L */ -{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, (GpioIntApic | GpioIntEdge), GpioResetDeep, - GpioTermNone}}, -/* EMMC_CMD */ -{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA0 */ -{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA1 */ -{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA2 */ -{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA3 */ -{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA4 */ -{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA5 */ -{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA6 */ -{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_DATA7 */ -{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_RCLK */ -{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_CLK */ -{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* EMMC_CMD */ -{GPIO_LP_GPP_F23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_CMD */ -{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_DATA0 */ -{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_DATA1 */ -{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_DATA2 */ -{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_DATA3 */ -{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_CD# */ -{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SD_CLK# */ -{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* SD_WP# */ -{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* ACPRESENT# */ -{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* EC_PCH_WAKE_L */ -{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -/* PWRBTN# */ -{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -/* SLP_S3# */ -{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SLP_S4# */ -{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SUSCLK */ -{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, -/* SLP_S5# */ -{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ /* GPP_F4 */ +/* I2C2_SCL */ /* GPP_F5 */ +/* I2C3_SDA */ /* GPP_F6 */ +/* I2C3_SCL */ /* GPP_F7 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SCL */ /* GPP_F11 */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* GPP_F23 */ +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* BATLOW# */ /* GPD0 */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ /* GPD9 */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ /* GPD11 */ }; #endif diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 26b622a..61a5485 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -20,10 +20,14 @@ */ #include <device/device.h> +#include <stdlib.h> #include "ec.h" +#include "gpio.h" static void mainboard_init(device_t dev) { + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) mainboard_ec_init(); } diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c index f31511e..8801380 100644 --- a/src/mainboard/google/glados/ramstage.c +++ b/src/mainboard/google/glados/ramstage.c @@ -19,9 +19,7 @@ */ #include <soc/ramstage.h> -#include "gpio.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - params->GpioTablePtr = (UINT32 *)mainboard_gpio_table; } diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 1882fa7..d5d96b6 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -21,10 +21,9 @@ #include <arch/byteorder.h> #include <cbfs.h> #include <console/console.h> +#include <gpio.h> #include <string.h> -#include <soc/gpio.h> #include <soc/pei_data.h> -#include <soc/pcr.h> #include <soc/romstage.h> #include "spd.h" @@ -85,42 +84,16 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) char *spd_file; size_t spd_file_len; int spd_index; - int spd_gpio[4]; - - /************************************************************* - * FIXME: Remove when real GPIO support is ready. - */ - GPIO_PAD gpio_set[4] = { - GPIO_LP_GPP_C12, /* PCH_MEM_CONFIG[0] */ - GPIO_LP_GPP_C13, /* PCH_MEM_CONFIG[1] */ - GPIO_LP_GPP_C14, /* PCH_MEM_CONFIG[2] */ - GPIO_LP_GPP_C15, /* PCH_MEM_CONFIG[3] */ - }; - int index; - - for (index = 0; index < ARRAY_SIZE(gpio_set); index++) { - u32 number = GPIO_GET_PAD_NUMBER(gpio_set[index]); - u32 cfgreg = 8 * number + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET; - /* - * Set GPIO mode and enable input - * Clear PMODE0 | PMODE1 | GPIORXDIS - */ - u32 dw0mask = (1 << 10) | (1 << 11) | (1 << 9); - u32 dw0reg = 0; - pcr_andthenor32(PID_GPIOCOM1, cfgreg, ~dw0mask, dw0reg); - - /* Read current input value */ - pcr_read32(PID_GPIOCOM1, cfgreg, &dw0reg); - spd_gpio[index] = !!(dw0reg & (1 << 1)); - } - /*************************************************************/ - spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | - (spd_gpio[1] << 1) | spd_gpio[0]; + gpio_t spd_gpios[] = { + GPP_C12, /* PCH_MEM_CONFIG[0] */ + GPP_C13, /* PCH_MEM_CONFIG[1] */ + GPP_C14, /* PCH_MEM_CONFIG[2] */ + GPP_C15, /* PCH_MEM_CONFIG[3] */ + }; - printk(BIOS_DEBUG, - "SPD: index %d (GPP_C15=%d GPP_C14=%d GPP_C13=%d GPP_C12=%d)\n", - spd_index, spd_gpio[3], spd_gpio[2], spd_gpio[1], spd_gpio[0]); + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_ERR, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,

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coreboot-gerrit August 2015