coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

New patch to review for coreboot: cbfstool: allow passing a precalculated header size into cbfs_add_entry()
by Patrick Georgi 12 Aug '15

12 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11213 -gerrit commit 2aedc88b9e64ecca4462d609daf8c43eb822e82e Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Aug 11 14:54:24 2015 +0200 cbfstool: allow passing a precalculated header size into cbfs_add_entry() This is in preparation of creating the cbfs_file header much earlier in the process. For now, size is enough because lots of things need to move before it makes sense to deal with cbfs_file at a higher level. Change-Id: I47589247c3011cb828170eaa10ef4a1e0f85ab84 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/cbfstool/cbfs_image.c | 8 +++++--- util/cbfstool/cbfs_image.h | 3 ++- util/cbfstool/cbfstool.c | 6 +++--- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index e095187..e78ee40 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -533,7 +533,8 @@ static int cbfs_add_entry_at(struct cbfs_image *image, } int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, - const char *name, uint32_t type, uint32_t content_offset) + const char *name, uint32_t type, uint32_t content_offset, + uint32_t header_size) { assert(image); assert(buffer); @@ -544,9 +545,10 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, uint32_t entry_type; uint32_t addr, addr_next; struct cbfs_file *entry, *next; - uint32_t header_size, need_size, new_size; + uint32_t need_size, new_size; - header_size = cbfs_calculate_file_header_size(name); + if (header_size == 0) + header_size = cbfs_calculate_file_header_size(name); need_size = header_size + buffer->size; DEBUG("cbfs_add_entry('%s'@0x%x) => need_size = %u+%zu=%u\n", diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index cb2935b..907be61 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -93,7 +93,8 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, * Never pass this function a top-aligned address: convert it to an offset. * Returns 0 on success, otherwise non-zero. */ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, - const char *name, uint32_t type, uint32_t content_offset); + const char *name, uint32_t type, uint32_t content_offset, + uint32_t header_size); /* Removes an entry from CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_remove_entry(struct cbfs_image *image, const char *name); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 6a89476..80e3895 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -150,8 +150,8 @@ static int cbfs_add_integer_component(const char *name, offset = convert_to_from_top_aligned(param.image_region, -offset); - if (cbfs_add_entry(&image, &buffer, name, CBFS_COMPONENT_RAW, offset) != - 0) { + if (cbfs_add_entry(&image, &buffer, name, CBFS_COMPONENT_RAW, + offset, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; @@ -211,7 +211,7 @@ static int cbfs_add_component(const char *filename, offset = convert_to_from_top_aligned(param.image_region, -offset); - if (cbfs_add_entry(&image, &buffer, name, type, offset) != 0) { + if (cbfs_add_entry(&image, &buffer, name, type, offset, 0) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); buffer_delete(&buffer); return 1;

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New patch to review for coreboot: cbfstool: test for duplicate files earlier
by Patrick Georgi 12 Aug '15

12 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11212 -gerrit commit 748c6fa16cd256662f0eee9b1dc5d52541cb6291 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Aug 11 14:35:39 2015 +0200 cbfstool: test for duplicate files earlier No need to read the file before bailing out. Change-Id: Ida7226c6ec227e1105724cdb1e5a0927217a69c7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/cbfstool/cbfstool.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index b6a486f..6a89476 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -190,6 +190,11 @@ static int cbfs_add_component(const char *filename, if (cbfs_image_from_buffer(&image, param.image_region, headeroffset)) return 1; + if (cbfs_get_entry(&image, name)) { + ERROR("'%s' already in ROM image.\n", name); + return 1; + } + struct buffer buffer; if (buffer_from_file(&buffer, filename) != 0) { ERROR("Could not load file '%s'.\n", filename); @@ -202,12 +207,6 @@ static int cbfs_add_component(const char *filename, return 1; } - if (cbfs_get_entry(&image, name)) { - ERROR("'%s' already in ROM image.\n", name); - buffer_delete(&buffer); - return 1; - } - if (IS_TOP_ALIGNED_ADDRESS(offset)) offset = convert_to_from_top_aligned(param.image_region, -offset);

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Patch set updated for coreboot: cbfstool: add cbfs file attribute structure
by Patrick Georgi 12 Aug '15

12 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10937 -gerrit commit 99c3e63cf39af1d5db0e5b5c5a52c15a2cd069f3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jul 22 21:32:03 2015 +0200 cbfstool: add cbfs file attribute structure This is a generic structure, not unlike the cbtables design, based on which we can build specialized TLV data structures. Change-Id: I98a75eef19f049ad67d46cdc2790949dcd155797 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index f63b881..064d3e7 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -85,6 +85,12 @@ struct cbfs_file { _Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); +struct cbfs_file_attribute { + uint32_t tag; + uint32_t len; + uint8_t data[]; +} __PACKED; + struct cbfs_stage { uint32_t compression; uint64_t entry;

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New patch to review for coreboot: cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11211 -gerrit commit 20e5eecea1b40651b69d5c934344f1cb8f5d98db Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Aug 12 11:19:10 2015 -0500 cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled In the wake of the recent Intel APIC SMM exploit a code review of the AMD SMM code was undertaken. Native Family 10h initialization does not require SMM to function, and the SMM memory range initialization should only be executed if SMM will be used on the target platform. Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/model_10xxx_init.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c17f335..f74a01c 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -99,15 +99,19 @@ static void model_10xxx_init(device_t dev) msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(SMM_MASK_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + printk(BIOS_DEBUG, "Initializing SMM\n"); + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(SMM_MASK_MSR); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(SMM_MASK_MSR, msr); + } /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR);

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New patch to review for coreboot: glados: make EC_SCI_L work
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11210 -gerrit commit 89ff61709fbad0450ef94a1f9bd1a68b16171a29 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 9 14:45:02 2015 -0500 glados: make EC_SCI_L work In order for the EC_SCI_L to work the GPE0 route needs to be set along w/ the GPE event for the EC. As the GPE0 route is dynamic the EC_SCI_GPI needs to be set along with the route so everything lines up. In this case, the GPE0 route is set to the defaults such that GPP_C, GPP_D, and GPP_E are routed to GPE0 block 0, 1, and 2, respectively. This works out for glados because the EC_SCI_L is connected to GPP_E16. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts is incrementing as well as /sys/firmware/acpi/interrupts/gpe50. Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292011 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/devicetree.cb | 8 ++++++++ src/mainboard/google/glados/ec.h | 6 ++++-- src/mainboard/google/glados/gpio.h | 2 +- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2e1cae7..6f2b2a7 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,6 +49,14 @@ chip soc/intel/skylake register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits are also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # Embedded Controller host command window register "gen1_dec" = "0x00fc0801" diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index f42e4c7..d43b57c 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -24,8 +24,10 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/gpio.h> -/* GPP_E16 is EC_SCI_L */ -#define EC_SCI_GPI 16 /* TODO: Update this */ +/* GPP_E16 is EC_SCI_L, however the EC_SCI_GPI needs to be a bit + * number relative to the GPE0 block. GPP_E is routed as the dword 2 + * in the GPE0 block. Therefore, 16 + 2 * 32 = 80. */ +#define EC_SCI_GPI 80 #define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \ diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index ebbee20..c7cd5ae 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */

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New patch to review for coreboot: glados: make EC_SMI_L functional
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11209 -gerrit commit 0317609d6692fa2277c33cbe4adabc20519500c3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:25:21 2015 -0500 glados: make EC_SMI_L functional Set the EC_SMI_GPI define to be GPP_E15 and route that GPIO for SMI generation. Also, the mainboard_smi_gpi_handler() was introduced on skylake in order to process any GPI that could generate an SMI. Switch to this handler so one can process the appropriate events. BUG=chrome-os-partner:43778 BRANCH=None TEST=Used 'lidclose' on EC command line during depthcharge to confirm EC_SMI_L generates SMI and shutdown happens. Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291934 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/ec.h | 4 ++-- src/mainboard/google/glados/gpio.h | 2 +- src/mainboard/google/glados/smihandler.c | 5 ++--- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index 9da9d9f..f42e4c7 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -22,11 +22,11 @@ #define MAINBOARD_EC_H #include <ec/google/chromeec/ec_commands.h> +#include <soc/gpio.h> /* GPP_E16 is EC_SCI_L */ #define EC_SCI_GPI 16 /* TODO: Update this */ -/* GPP_E15 is EC_SMI_L */ -#define EC_SMI_GPI 15 /* TODO: Update this */ +#define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index dc58e9a..ebbee20 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -134,7 +134,7 @@ static const struct pad_config gpio_table[] = { /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), +/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ /* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 164bd8e..f9f4707 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -74,10 +74,9 @@ static u8 mainboard_smi_ec(void) return cmd; } -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) +void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { + if (gpi_status_get(sts, EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ;

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New patch to review for coreboot: skylake: fix SMI GPI status handling
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11208 -gerrit commit c6de95c4c23cb1ae328145e17f8e9c48b31b74ad Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:11:32 2015 -0500 skylake: fix SMI GPI status handling The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/gpio.c | 245 +++++++++++++++---------------- src/soc/intel/skylake/include/soc/gpio.h | 21 +-- src/soc/intel/skylake/include/soc/pm.h | 4 - src/soc/intel/skylake/include/soc/smm.h | 5 + src/soc/intel/skylake/pmutil.c | 48 ------ src/soc/intel/skylake/smihandler.c | 10 +- 6 files changed, 140 insertions(+), 193 deletions(-) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 6a904bd..5493cbd 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <gpio.h> @@ -57,6 +58,36 @@ static const struct gpio_community communities[] = { }, }; +static const char *gpio_group_names[GPIO_NUM_GROUPS] = { + "GPP_A", + "GPP_B", + "GPP_C", + "GPP_D", + "GPP_E", + "GPP_F", + "GPP_G", + "GPD", +}; + +static inline size_t gpios_in_community(const struct gpio_community *comm) +{ + /* max is inclusive */ + return comm->max - comm->min + 1; +} + +static inline size_t groups_in_community(const struct gpio_community *comm) +{ + size_t n = gpios_in_community(comm) + GPIO_MAX_NUM_PER_GROUP - 1; + return n / GPIO_MAX_NUM_PER_GROUP; +} + +static inline int gpio_index_gpd(gpio_t gpio) +{ + if (gpio >= GPD0 && gpio <= GPD11) + return 1; + return 0; +} + static const struct gpio_community *gpio_get_community(gpio_t pad) { size_t i; @@ -71,6 +102,90 @@ static const struct gpio_community *gpio_get_community(gpio_t pad) return NULL; } +static size_t community_clr_get_smi_sts(const struct gpio_community *comm, + uint32_t *sts) +{ + uint8_t *regs; + size_t i; + uint32_t *gpi_status_reg; + uint32_t *gpi_en_reg; + const size_t num_grps = groups_in_community(comm); + + /* Not all groups can be routed to SMI. However, the registers + * read as 0. In order to simplify the logic read everything from + * each community. */ + regs = pcr_port_regs(comm->port_id); + gpi_status_reg = (void *)&regs[GPI_SMI_STS_OFFSET]; + gpi_en_reg = (void *)&regs[GPI_SMI_EN_OFFSET]; + for (i = 0; i < num_grps; i++) { + sts[i] = read32(gpi_status_reg + i) & read32(gpi_en_reg + i); + /* Clear the enabled and set status bits. */ + write32(gpi_status_reg + i, sts[i]); + } + + return num_grps; +} + +static void print_gpi_status(uint32_t status, const char *grp_name) +{ + int i; + + if (!status) + return; + + for (i = 31; i >= 0; i--) { + if (status & (1 << i)) + printk(BIOS_DEBUG, "%s%d ", grp_name, i); + } +} + +void gpi_clear_get_smi_status(struct gpi_status *sts) +{ + int i; + int do_print; + size_t sts_index = 0; + + for (i = 0; i < ARRAY_SIZE(communities); i++) { + const struct gpio_community *comm = &communities[i]; + sts_index += community_clr_get_smi_sts(comm, + &sts->grp[sts_index]); + } + + do_print = 0; + for (i = 0; i < ARRAY_SIZE(sts->grp); i++) { + if (sts->grp[i] == 0) + continue; + do_print = 1; + break; + } + + if (!do_print) + return; + + printk(BIOS_DEBUG, "GPI_SMI_STS: "); + for (i = 0; i < ARRAY_SIZE(sts->grp); i++) + print_gpi_status(sts->grp[i], gpio_group_names[i]); + printk(BIOS_DEBUG, "\n"); +} + +int gpi_status_get(const struct gpi_status *sts, gpio_t gpi) +{ + const uint32_t *gpi_sts; + + /* Check if valid gpi */ + if (gpio_get_community(gpi) == NULL) + return 0; + + /* If not in GPD group the index is a linear function based on + * GPI number and GPIO_MAX_NUM_PER_GROUP. */ + if (gpio_index_gpd(gpi)) + gpi_sts = &sts->grp[GPD]; + else + gpi_sts = &sts->grp[gpi / GPIO_MAX_NUM_PER_GROUP]; + + return !!(*gpi_sts & (1 << (gpi % GPIO_MAX_NUM_PER_GROUP))); +} + void gpio_route_gpe(uint16_t gpe0_route) { int i; @@ -272,133 +387,3 @@ void gpio_set(gpio_t gpio_num, int value) write32(&dw_regs[0], reg); /* GPIO port ids support posted write semantics. */ } - -/* Keep the ordering intact GPP_A ~ G, GPD. - * As the gpio/smi functions gpio_get_smi_status() and - * gpio_enable_groupsmi() depends on this ordering. - */ -static const GPIO_GROUP_INFO gpio_group_info[] = { - /* GPP_A */ - { - .community = PID_GPIOCOM0, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_A_PAD_MAX, - .smistsoffset = R_PCH_PCR_GPIO_GPP_A_SMI_STS, - .smienoffset = R_PCH_PCR_GPIO_GPP_A_SMI_EN, - }, - /* GPP_B */ - { - .community = PID_GPIOCOM0, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_B_PAD_MAX, - .smistsoffset = R_PCH_PCR_GPIO_GPP_B_SMI_STS, - .smienoffset = R_PCH_PCR_GPIO_GPP_B_SMI_EN, - }, - /* GPP_C */ - { - .community = PID_GPIOCOM1, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_C_PAD_MAX, - .smistsoffset = R_PCH_PCR_GPIO_GPP_C_SMI_STS, - .smienoffset = R_PCH_PCR_GPIO_GPP_C_SMI_EN, - }, - /* GPP_D */ - { - .community = PID_GPIOCOM1, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_D_PAD_MAX, - .smistsoffset = R_PCH_PCR_GPIO_GPP_D_SMI_STS, - .smienoffset = R_PCH_PCR_GPIO_GPP_D_SMI_EN, - }, - /* GPP_E */ - { - .community = PID_GPIOCOM1, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_E_PAD_MAX, - .smistsoffset = R_PCH_PCR_GPIO_GPP_E_SMI_STS, - .smienoffset = R_PCH_PCR_GPIO_GPP_E_SMI_EN, - }, - /* GPP_F */ - { - .community = PID_GPIOCOM3, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_F_PAD_MAX, - .smistsoffset = NO_REGISTER_PROPERTY, - .smienoffset = NO_REGISTER_PROPERTY, - }, - /* GPP_G */ - { - .community = PID_GPIOCOM3, - .padcfgoffset = R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPP_G_PAD_MAX, - .smistsoffset = NO_REGISTER_PROPERTY, - .smienoffset = NO_REGISTER_PROPERTY, - }, - /* GPD */ - { - .community = PID_GPIOCOM2, - .padcfgoffset = R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET, - .padpergroup = V_PCH_GPIO_GPD_PAD_MAX, - .smistsoffset = NO_REGISTER_PROPERTY, - .smienoffset = NO_REGISTER_PROPERTY, - }, -}; - -void gpio_clear_all_smi(void) -{ - u32 gpiogroupinfolength; - u32 gpioindex = 0; - - gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO); - - for (gpioindex = 0; gpioindex < gpiogroupinfolength; gpioindex++) { - /*Check if group has GPI SMI register */ - if (gpio_group_info[gpioindex].smistsoffset == - NO_REGISTER_PROPERTY) - continue; - /* Clear all GPI SMI Status bits by writing '1' */ - pcr_write32(gpio_group_info[gpioindex].community, - gpio_group_info[gpioindex].smistsoffset, - 0xFFFFFFFF); - } -} - -void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]) -{ - u32 num_of_communities; - u32 gpioindex; - u32 outputvalue = 0; - - num_of_communities = ARRAY_SIZE(gpio_group_info); - - for (gpioindex = 0; gpioindex < num_of_communities; gpioindex++) { - /*Check if group has GPI SMI register */ - if (gpio_group_info[gpioindex].smistsoffset == - NO_REGISTER_PROPERTY) - continue; - /* Read SMI status register */ - pcr_read32(gpio_group_info[gpioindex].community, - gpio_group_info[gpioindex].smistsoffset, - &outputvalue); - status[gpioindex] = outputvalue; - } -} - -void gpio_enable_all_smi(void) -{ - u32 gpiogroupinfolength; - u32 gpioindex = 0; - - gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO); - - for (gpioindex = 0; gpioindex < gpiogroupinfolength; gpioindex++) { - /*Check if group has GPI SMI register */ - if (gpio_group_info[gpioindex].smienoffset == - NO_REGISTER_PROPERTY) - continue; - /* Set all GPI SMI Enable bits by writing '1' */ - pcr_write32(gpio_group_info[gpioindex].community, - gpio_group_info[gpioindex].smienoffset, - 0xFFFFFFFF); - } -} diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 2116c7e..488a2b5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -28,19 +28,22 @@ #include <stddef.h> #include <soc/gpio_fsp.h> -/* SOC has 8 GPIO communities GPP A~G, GPD */ -#define GPIO_COMMUNITY_MAX 8 - typedef uint32_t gpio_t; -/* Clear GPIO SMI Status */ -void gpio_clear_all_smi(void); +/* Structure to represent GPI status for GPE and SMI. Use helper + * functions for interrogating particular GPIs. */ +struct gpi_status { + uint32_t grp[GPIO_NUM_GROUPS]; +}; -/* Get GPIO SMI Status */ -void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); +/* + * Clear GPI SMI status and fill in the structure representing enabled + * and set status. + */ +void gpi_clear_get_smi_status(struct gpi_status *sts); -/* Enable GPIO SMI */ -void gpio_enable_all_smi(void); +/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */ +int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); /* * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index c0a165e..3daa320 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -174,10 +174,6 @@ uint32_t clear_smi_status(void); void enable_smi(uint32_t mask); void disable_smi(uint32_t mask); -/* ALT_GP_SMI */ -uint32_t clear_alt_smi_status(void); -void reset_alt_smi_status(void); - /* TCO */ uint32_t clear_tco_status(void); void enable_tco_sci(void); diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index fbae6ef..212a444 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -25,6 +25,7 @@ #include <cpu/x86/msr.h> #include <soc/intel/common/romstage.h> #include <soc/intel/common/memmap.h> +#include <soc/gpio.h> struct ied_header { char signature[10]; @@ -51,6 +52,10 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; +/* Mainboard handler for GPI SMIs*/ +void mainboard_smi_gpi_handler(const struct gpi_status *sts); + + #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) int smm_initialize(void); void smm_relocate(void); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 8e54db4..b048c99 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -210,54 +210,6 @@ void disable_smi(u32 mask) outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } - -/* - * ALT_GP_SMI - */ - -/* Clear GPIO SMI status and return events that are enabled and active */ -void reset_alt_smi_status(void) -{ - /*Clear GPIO SMI Status*/ - gpio_clear_all_smi(); -} - -/* Print GPIO SMI status bits */ -static u32 print_alt_smi_status(void) -{ - u32 alt_sts[GPIO_COMMUNITY_MAX]; - int gpio_index; - /* GPIO Communities GPP_A ~ E support SMI */ - const char gpiowell[] = { - [0] = 'A', - [1] = 'B', - [2] = 'C', - [3] = 'D', - [4] = 'E' - }; - - printk(BIOS_DEBUG, "ALT_STS: "); - gpio_get_smi_status(alt_sts); - /* GPP_A to GPP_E GPIO has Status and Enable functionality*/ - for (gpio_index = 0; gpio_index < ARRAY_SIZE(gpiowell); - gpio_index++) { - printk(BIOS_DEBUG, "GPIO Group_%c\n", - gpiowell[gpio_index]); - print_gpio_status(alt_sts[gpio_index], 0); - } - - printk(BIOS_DEBUG, "\n"); - - return 0; -} - -/* Print, clear, and return GPIO SMI status */ -u32 clear_alt_smi_status(void) -{ - reset_alt_smi_status(); - return print_alt_smi_status(); -} - /* * TCO */ diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 6c95955..fa5ef04 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -351,12 +351,18 @@ static void southbridge_smi_gpe0(void) clear_gpe_status(); } +void __attribute__((weak)) +mainboard_smi_gpi_handler(const struct gpi_status *sts) { } + static void southbridge_smi_gpi(void) { - mainboard_smi_gpi(clear_alt_smi_status()); + struct gpi_status smi_sts; + + gpi_clear_get_smi_status(&smi_sts); + mainboard_smi_gpi_handler(&smi_sts); /* Clear again after mainboard handler */ - clear_alt_smi_status(); + gpi_clear_get_smi_status(&smi_sts); } static void southbridge_smi_mc(void)

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New patch to review for coreboot: skylake: enable SMI routed GPIs
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11207 -gerrit commit b7a95ab0e22cb7eb619a088b31388d872fd202d9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 9 14:20:41 2015 -0500 skylake: enable SMI routed GPIs The first pass of the GPIO configuration patch didn't enable the SMI# generation for GPIs marked as SMI routed. Now when a pad is configured as SMI routed the bit for the SMI enablement is set accordingly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Confirmed SMI_EN being set for SMI routed GPIOs. Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292010 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/gpio.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index afd838f..6a904bd 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -156,11 +156,37 @@ static void gpio_handle_pad_mode(const struct pad_config *cfg) write32(hostsw_own_reg, reg); } +static void gpi_enable_smi(gpio_t pad) +{ + const struct gpio_community *comm; + uint8_t *regs; + uint32_t *gpi_status_reg; + uint32_t *gpi_en_reg; + size_t group_offset; + uint32_t pad_mask; + + comm = gpio_get_community(pad); + + regs = pcr_port_regs(comm->port_id); + gpi_status_reg = (void *)&regs[GPI_SMI_STS_OFFSET]; + gpi_en_reg = (void *)&regs[GPI_SMI_EN_OFFSET]; + + /* Offset of SMI STS/EN for this pad's group within the community. */ + group_offset = (pad - comm->min) / GPIO_MAX_NUM_PER_GROUP; + + /* Clear status then set enable. */ + pad_mask = 1 << ((pad - comm->min) % GPIO_MAX_NUM_PER_GROUP); + write32(&gpi_status_reg[group_offset], pad_mask); + write32(&gpi_en_reg[group_offset], + read32(&gpi_en_reg[group_offset]) | pad_mask); +} + static void gpio_configure_pad(const struct pad_config *cfg) { uint32_t *dw_regs; uint32_t reg; uint32_t termination; + uint32_t dw0; const uint32_t termination_mask = PAD_TERM_MASK << PAD_TERM_SHIFT; dw_regs = gpio_dw_regs(cfg->pad); @@ -168,7 +194,9 @@ static void gpio_configure_pad(const struct pad_config *cfg) if (dw_regs == NULL) return; - write32(&dw_regs[0], cfg->dw0); + dw0 = cfg->dw0; + + write32(&dw_regs[0], dw0); reg = read32(&dw_regs[1]); reg &= ~termination_mask; termination = cfg->attrs; @@ -177,6 +205,9 @@ static void gpio_configure_pad(const struct pad_config *cfg) write32(&dw_regs[1], reg); gpio_handle_pad_mode(cfg); + + if ((dw0 & PAD_FIELD(GPIROUTSMI, MASK)) == PAD_FIELD(GPIROUTSMI, YES)) + gpi_enable_smi(cfg->pad); } void gpio_configure_pads(const struct pad_config *cfgs, size_t num)

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New patch to review for coreboot: skylake: clarify and fix gpio macros
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11206 -gerrit commit 20b7af8152276eb710d45d2c33a191714a3ce52e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:31:05 2015 -0500 skylake: clarify and fix gpio macros The gpio pad configuration currently defaults to ACPI owned GPIs. A '0' was used which wasn't so clear. Add a comment and explicitly set it to ACPI. Also, PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS macro which causes compliation errors if attempted to be instantiated. No piece of code tried to use it so the error was overlooked. Lastly, allow for soc/gpio.h to be included during ASL compilation. That allows for gpio_defs.h to be included and those macros utilized without needing to know the file name and where it lives; just use the generic gpio.h. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291935 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/gpio.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 1c462a7..2116c7e 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -21,9 +21,11 @@ #ifndef _SOC_GPIO_H_ #define _SOC_GPIO_H_ +#include <soc/gpio_defs.h> + +#ifndef __ACPI__ #include <stdint.h> #include <stddef.h> -#include <soc/gpio_defs.h> #include <soc/gpio_fsp.h> /* SOC has 8 GPIO communities GPP A~G, GPD */ @@ -99,7 +101,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); .dw0 = dw0_, \ } -#define _PAD_CFG(pad_, term_, dw0_) _PAD_CFG_ATTRS(pad_, term_, dw0_, 0) +/* Default to ACPI owned. Ownership only matters for GPI pads. */ +#define _PAD_CFG(pad_, term_, dw0_) \ + _PAD_CFG_ATTRS(pad_, term_, dw0_, PAD_FIELD(HOSTSW, ACPI)) /* Native Function - No Rx buffer manipulation */ #define PAD_CFG_NF(pad_, term_, rst_, func_) \ @@ -131,7 +135,7 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); /* General purpose input routed to SMI. This assumes edge triggered events. */ #define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \ - _PAD_CFG(pad_, term_, \ + _PAD_CFG_ATTRS(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) @@ -151,4 +155,5 @@ struct pad_config { uint32_t dw0; }; +#endif /* __ACPI__ */ #endif

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New patch to review for coreboot: skylake: provide clarification for FADT gpe0_blk_len
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11205 -gerrit commit 63734fd6ddceb1e881764eb1ab3044ea55aab6a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 23:00:22 2015 -0500 skylake: provide clarification for FADT gpe0_blk_len Instead of using a hard-coded value leverage the existing definitions to perform GPE0 block length calculations. There are 4 pairs of 32-bit status/enable registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291932 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 1b193c7..87d4eb0 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -222,7 +222,8 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = 0;

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coreboot-gerrit August 2015