coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: skylake: remove ec_smi_gpio and alt_gp_smi_en
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11204 -gerrit commit 742cede3a3f9bd91ae1ad20923bb6af674bde409 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 22:57:42 2015 -0500 skylake: remove ec_smi_gpio and alt_gp_smi_en The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/devicetree.cb | 5 +---- src/mainboard/intel/sklrvp/devicetree.cb | 4 +--- src/soc/intel/skylake/chip.h | 4 ---- src/soc/intel/skylake/gpio.c | 18 ------------------ src/soc/intel/skylake/include/soc/gpio.h | 3 --- src/soc/intel/skylake/include/soc/pm.h | 1 - src/soc/intel/skylake/pmc.c | 3 --- src/soc/intel/skylake/pmutil.c | 8 -------- 8 files changed, 2 insertions(+), 44 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 7f1b35f..6f03bbf 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -28,11 +28,8 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" - # EC_SMI - register "ec_smi_gpio" = "34" - register "alt_gp_smi_en" = "0x0400" + # GPE configuration register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" register "gpe0_en_3" = "0x00000000" diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb index 128c222..cfa51a8 100644 --- a/src/mainboard/intel/sklrvp/devicetree.cb +++ b/src/mainboard/intel/sklrvp/devicetree.cb @@ -49,9 +49,7 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" - # EC_SMI - register "ec_smi_gpio" = "34" - register "alt_gp_smi_en" = "0x0400" + # GPE configuration register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 873342a..9fe1ed2 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -54,10 +54,6 @@ struct soc_intel_skylake_config { uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ - /* GPIO SMI configuration */ - uint32_t ec_smi_gpio; - uint32_t alt_gp_smi_en; - /* Generic IO decode ranges */ uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 1863887..afd838f 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -371,21 +371,3 @@ void gpio_enable_all_smi(void) 0xFFFFFFFF); } } - -void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask) -{ - u32 gpioindex = 0; - u32 smien = 0; - - if (gpio_num > MAX_GPIO_NUMBER) - return; - - gpioindex = (gpio_num / MAX_GPIO_PIN_PER_GROUP); - - pcr_read32(gpio_group_info[gpioindex].community, - gpio_group_info[gpioindex].smienoffset, &smien); - smien |= mask; - /* Set all GPI SMI Enable bits by writing '1' */ - pcr_write32(gpio_group_info[gpioindex].community, - gpio_group_info[gpioindex].smienoffset, smien); -} diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 321f04c..1c462a7 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -40,9 +40,6 @@ void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); /* Enable GPIO SMI */ void gpio_enable_all_smi(void); -/* Enable GPIO individual Group SMI */ -void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); - /* * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted * as the packed configuration for GPE0_DW[2:0]: diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 9409ba2..c0a165e 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -176,7 +176,6 @@ void disable_smi(uint32_t mask); /* ALT_GP_SMI */ uint32_t clear_alt_smi_status(void); -void enable_alt_smi(int gpionum, u32 mask); void reset_alt_smi_status(void); /* TCO */ diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index b6c35eb..2704956 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -227,9 +227,6 @@ static void pch_power_options(void) /* Set up GPE configuration. */ pmc_gpe_init(config); - - /* SMI setup based on device tree configuration */ - enable_alt_smi(config->ec_smi_gpio, config->alt_gp_smi_en); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index e5d4a2e..8e54db4 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -258,14 +258,6 @@ u32 clear_alt_smi_status(void) return print_alt_smi_status(); } -/* Enable GPIO SMI events */ -void enable_alt_smi(int gpionum, u32 mask) -{ - /*Set GPIO EN Status*/ - gpio_enable_groupsmi(gpionum, mask); -} - - /* * TCO */

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New patch to review for coreboot: skylake: provide GPE0 routing devicetree configuration
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11203 -gerrit commit 937b46fc66eea9daa51703deb2d25c2aab3e81e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 22:29:42 2015 -0500 skylake: provide GPE0 routing devicetree configuration On skylake the GPE0 routing can be dynamically changed to a particular GPIO group. Provide the ability for the mainboard to set the route accordingly. If any of the values in the devicetree are the same the current setting in the PMC register is used. The GPIO communities need to have matching configuration for the plumbing to work properly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados w/ and w/o devicetree changes. Fields are set accordingly. Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291930 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.h | 21 ++++++++----- src/soc/intel/skylake/gpio.c | 23 ++++++++++++++ src/soc/intel/skylake/include/soc/gpio.h | 9 ++++++ src/soc/intel/skylake/include/soc/gpio_defs.h | 31 ++++++++++++++++--- src/soc/intel/skylake/include/soc/pmc.h | 5 ++++ src/soc/intel/skylake/pmc.c | 43 +++++++++++++++++++++++++-- 6 files changed, 118 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 96389a9..873342a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -19,14 +19,16 @@ * Foundation, Inc. */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + #include <stdint.h> +#include <soc/gpio_defs.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/serialio.h> -#ifndef _SOC_CHIP_H_ -#define _SOC_CHIP_H_ - struct soc_intel_skylake_config { /* * Interrupt Routing configuration @@ -42,10 +44,15 @@ struct soc_intel_skylake_config { uint8_t pirqh_routing; /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; + uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ + uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ + uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ + uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ /* GPIO SMI configuration */ uint32_t ec_smi_gpio; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 28ed07e..1863887 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -71,6 +71,29 @@ static const struct gpio_community *gpio_get_community(gpio_t pad) return NULL; } +void gpio_route_gpe(uint16_t gpe0_route) +{ + int i; + uint32_t misc_cfg; + const uint32_t misc_cfg_reg_mask = GPE_DW_MASK; + + misc_cfg = (uint32_t)gpe0_route << GPE_DW_SHIFT; + misc_cfg &= misc_cfg_reg_mask; + + for (i = 0; i < ARRAY_SIZE(communities); i++) { + uint8_t *regs; + uint32_t reg; + const struct gpio_community *comm = &communities[i]; + + regs = pcr_port_regs(comm->port_id); + + reg = read32(regs + MISCCFG_OFFSET); + reg &= ~misc_cfg_reg_mask; + reg |= misc_cfg; + write32(regs + MISCCFG_OFFSET, reg); + } +} + static void *gpio_dw_regs(gpio_t pad) { const struct gpio_community *comm; diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index a7d9158..321f04c 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -43,6 +43,15 @@ void gpio_enable_all_smi(void); /* Enable GPIO individual Group SMI */ void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); +/* + * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted + * as the packed configuration for GPE0_DW[2:0]: + * dw0 = gpe0_route[3:0] + * dw1 = gpe0_route[7:4] + * dw2 = gpe0_route[11:8]. + */ +void gpio_route_gpe(uint16_t gpe0_route); + /* Configure the pads according to the pad_config array. */ struct pad_config; void gpio_configure_pads(const struct pad_config *cfgs, size_t num); diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 625acdb..09f5019 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -21,6 +21,23 @@ #define _SOC_GPIO_DEFS_H_ /* + * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case + * where that group is not so generic. So most of the fixed numbers and macros + * are based on the GPP groups. The GPIO groups are accessed through register + * blocks called communities. + */ +#define GPP_A 0 +#define GPP_B 1 +#define GPP_C 2 +#define GPP_D 3 +#define GPP_E 4 +#define GPP_F 5 +#define GPP_G 6 +#define GPD 7 +#define GPIO_NUM_GROUPS 8 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ @@ -375,6 +392,12 @@ #define GPD11_IRQ 0x5b /* Register defines. */ +#define MISCCFG_OFFSET 0x10 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 #define PAD_OWN_REG_OFFSET 0x20 #define PAD_OWN_PADS_PER 8 #define PAD_OWN_WIDTH_PER 4 @@ -476,9 +499,9 @@ #define PAD_TERM_667_PU 13 #define PAD_TERM_NATIVE 15 -#define MISCCFG_OFFSET 0x10 -#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPI_GPE_STS_OFFSET 0x140 +#define GPI_GPE_EN_OFFSET 0x160 +#define GPI_SMI_STS_OFFSET 0x180 +#define GPI_SMI_EN_OFFSET 0x1a0 #endif /* _SOC_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 5774d46..9c9b175 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -91,6 +91,11 @@ #define DSX_EN_LAN_WAKE_PIN (1 << 0) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) +#define GPIO_CFG 0x120 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW0_SHIFT 0 +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 2c794ca..b6c35eb 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -27,6 +27,7 @@ #include <pc80/mc146818rtc.h> #include <reg_script.h> #include <string.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pmc.h> @@ -147,6 +148,42 @@ static void pch_rtc_init(void) #endif } +static void pmc_gpe_init(config_t *config) +{ + uint8_t *pmc_regs; + uint32_t gpio_cfg; + uint32_t gpio_cfg_reg; + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW0_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT); + + pmc_regs = pmc_mmio_regs(); + gpio_cfg = 0; + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. */ + if (config->gpe0_dw0 == config->gpe0_dw1 || + config->gpe0_dw1 == config->gpe0_dw2) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32(pmc_regs + GPIO_CFG); + } else { + gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT; + } + gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + write32(pmc_regs + GPIO_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT); + + /* Set GPE enables based on devictree. */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); +} + static void pch_power_options(void) { u16 reg16; @@ -187,9 +224,9 @@ static void pch_power_options(void) } pci_write_config16(dev, GEN_PMCON_B, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* GPE setup based on device tree configuration */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); + + /* Set up GPE configuration. */ + pmc_gpe_init(config); /* SMI setup based on device tree configuration */ enable_alt_smi(config->ec_smi_gpio, config->alt_gp_smi_en);

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New patch to review for coreboot: util/cbmem: accumulate total time for all entries
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11202 -gerrit commit 5863d77dbc0d96b5b523d93084d71fce4c1c6824 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 6 13:52:08 2015 -0500 util/cbmem: accumulate total time for all entries Display the total accumulated time using each timestamp entry. It purposefully doesn't take into account the first timestamp because that can be a platform dependent value that may not contribute to the concept of "total". BUG=None BRANCH=None TEST=Ran cbmem on glados where TSC doesn't reset to 0 on reboots. Clear total value given at end. Original-Change-Id: Idddb8b88d3aaad11d72c58b18e8fd9fd1447a30e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291480 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I79a0954d3b738323aaebb3e05171bcf639e5d977 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index a11935e..6526384 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -476,10 +476,11 @@ static const struct timestamp_id_to_name { { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" } }; -void timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) { int i; const char *name; + uint64_t step_time; name = "<unknown>"; for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { @@ -492,12 +493,15 @@ void timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) printf("%4d:", id); printf("%-50s", name); print_norm(arch_convert_raw_ts_entry(stamp)); + step_time = arch_convert_raw_ts_entry(stamp - prev_stamp); if (prev_stamp) { printf(" ("); - print_norm(arch_convert_raw_ts_entry(stamp - prev_stamp)); + print_norm(step_time); printf(")"); } printf("\n"); + + return step_time; } /* dump the timestamp table */ @@ -507,6 +511,7 @@ static void dump_timestamps(void) struct timestamp_table *tst_p; size_t size; uint64_t prev_stamp; + uint64_t total_time; if (timestamps.tag != LB_TAG_TIMESTAMPS) { fprintf(stderr, "No timestamps found in coreboot table.\n"); @@ -527,16 +532,22 @@ static void dump_timestamps(void) timestamp_print_entry(0, tst_p->base_time, prev_stamp); prev_stamp = tst_p->base_time; + total_time = 0; for (i = 0; i < tst_p->num_entries; i++) { uint64_t stamp; const struct timestamp_entry *tse = &tst_p->entries[i]; /* Make all timestamps absolute. */ stamp = tse->entry_stamp + tst_p->base_time; - timestamp_print_entry(tse->entry_id, stamp, prev_stamp); + total_time += timestamp_print_entry(tse->entry_id, + stamp, prev_stamp); prev_stamp = stamp; } + printf("\nTotal Time: "); + print_norm(total_time); + printf("\n"); + unmap_memory(); }

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New patch to review for coreboot: skylake: remove IedSize from chip.h
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11201 -gerrit commit c91f86edc86ea78f0531c4599a9833143e022f5c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:38:14 2015 -0500 skylake: remove IedSize from chip.h IedSize is not used in replace of IED_REGION_SIZE. Drop it from chip.h. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290933 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index c04e9f8..96389a9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -132,7 +132,6 @@ struct soc_intel_skylake_config { u64 PlatformMemorySize; u8 SmramMask; u8 MrcFastBoot; - u32 IedSize; u32 TsegSize; u16 MmioSize;

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New patch to review for coreboot: kunimitsu sklrvp: remove unused IedSize
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11200 -gerrit commit 2bec24976e6a5139438fffaaeda265585a2c218f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:36:36 2015 -0500 kunimitsu sklrvp: remove unused IedSize The skylake code is using IED_REGION_SIZE instead of devicetree.cb. Drop the the option from the device trees. BUG=chrome-os-partner:43636 BRANCH=None TEST=None Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290932 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/devicetree.cb | 1 - src/mainboard/intel/sklrvp/devicetree.cb | 3 --- 2 files changed, 4 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 9b0ca0f..7f1b35f 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "gpe0_en_4" = "0x00000000" # Memory related - register "IedSize" = "0x0" register "ProbelessTrace" = "0" # Lan diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb index 66c1f18..128c222 100644 --- a/src/mainboard/intel/sklrvp/devicetree.cb +++ b/src/mainboard/intel/sklrvp/devicetree.cb @@ -68,9 +68,6 @@ chip soc/intel/skylake # Enable S0ix register "s0ix_enable" = "0" - # Memory related - register "IedSize" = "0x0" - # Probeless Trace function register "ProbelessTrace" = "0"

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New patch to review for coreboot: skylake: pass IED_REGION_SIZE Kconfig to FSP
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11199 -gerrit commit c9a4d3e000946a87be4021135440d77a97888c49 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:33:49 2015 -0500 skylake: pass IED_REGION_SIZE Kconfig to FSP Ignore the devicetree.cb setting and use the already existing IED_REGION_SIZE Kconfig option. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290931 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/romstage/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index af9c78b..253eaba 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -99,7 +99,7 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) params->MmioSize = 0x800; /* 2GB in MB */ params->TsegSize = CONFIG_SMM_TSEG_SIZE; - params->IedSize = config->IedSize; + params->IedSize = CONFIG_IED_REGION_SIZE; params->ProbelessTrace = config->ProbelessTrace; params->EnableLan = config->EnableLan; params->EnableSata = config->EnableSata;

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New patch to review for coreboot: skylake: use smm_subregion() during SMM relocation
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11198 -gerrit commit fe42c86c30c1daba5481a2a42ec144b4456c4f07 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:28:50 2015 -0500 skylake: use smm_subregion() during SMM relocation The smm_subregion() support allows the SMM relocation to not use duplicated math by calling out the specific regions it wants. IED base is now correct and not pointing outside from SMRAM. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290930 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/smmrelocate.c | 40 ++++++++++++------------------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 874d95f..2f75c2e 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -196,28 +196,20 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) write_smrr(relo_params); } -static u32 northbridge_get_base_reg(device_t dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - static void fill_in_relocation_params(device_t dev, struct smm_relocation_params *params) { - u32 tseg_size; - u32 tsegmb; - u32 bgsm; + void *handler_base; + size_t handler_size; + void *ied_base; + size_t ied_size; + void *tseg_base; + size_t tseg_size; u32 emrr_base; u32 emrr_size; int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); - config_t *conf = dev->chip_info; /* * Some of the range registers are dependent on the number of physical @@ -225,21 +217,15 @@ static void fill_in_relocation_params(device_t dev, */ phys_bits = cpuid_eax(0x80000008) & 0xff; - /* - * The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. - */ - tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - tseg_size = bgsm - tsegmb; + smm_region(&tseg_base, &tseg_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); - params->ied_size = conf->IedSize; - params->smram_size = tseg_size - params->ied_size; - params->smram_base = tsegmb; - params->ied_base = tsegmb + params->smram_size; + params->smram_size = handler_size; + params->smram_base = (uintptr_t)handler_base; - /* Adjust available SMM handler memory size. */ - params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + params->ied_base = (uintptr_t)ied_base; + params->ied_size = ied_size; /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;

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New patch to review for coreboot: intel/common: fix stage_cache_external_region()
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11197 -gerrit commit d217e5254c18476a53af5950336771c00f5aad61 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 14:51:48 2015 -0500 intel/common: fix stage_cache_external_region() The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/braswell/memmap.c | 39 ++++++++++++++++++++++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/fsp_ramstage.c | 66 ++++++++----------------------------- src/soc/intel/common/memmap.h | 18 ++++++++++ src/soc/intel/common/stage_cache.c | 19 ++++------- src/soc/intel/skylake/memmap.c | 47 ++++++++++++++++++++++++++ 6 files changed, 124 insertions(+), 66 deletions(-) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d1d784d..52bba3e 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -47,6 +47,45 @@ size_t mmap_region_granluarity(void) : 8 << 20; } +/* + * Subregions within SMM + * +-------------------------+ BUNIT_SMRRH + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ BUNIT_SMRRL + */ +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + void *sub_ptr; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_ptr, &sub_size); + sub_base = (uintptr_t)sub_ptr; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + void *cbmem_top(void) { char *smm_base; diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 76854ad..7c5bbbe 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index a5728b5..c5916e3 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -36,63 +36,23 @@ __attribute__((weak)) void soc_after_silicon_init(void) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -/* - * SMM Memory Map: - * - * +--------------------------+ smm_region_size() ----. - * | FSP Cache | | - * +--------------------------+ | - * | SMM Stage Cache | + CONFIG_SMM_RESERVED_SIZE - * +--------------------------+ ---------------------' - * | SMM Code | - * +--------------------------+ smm_base - * - */ - -void stage_cache_external_region(void **base, size_t *size) -{ - size_t cache_size; - u8 *cache_base; - - /* Determine the location of the ramstage cache */ - smm_region((void **)&cache_base, &cache_size); - *size = CONFIG_SMM_RESERVED_SIZE; - *base = &cache_base[cache_size - CONFIG_SMM_RESERVED_SIZE]; -} - /* Display SMM memory map */ static void smm_memory_map(void) { - u8 *smm_base; - size_t smm_bytes; - size_t smm_code_bytes; - u8 *ext_cache; - size_t ext_cache_bytes; - u8 *smm_reserved; - size_t smm_reserved_bytes; - - /* Locate the SMM regions */ - smm_region((void **)&smm_base, &smm_bytes); - stage_cache_external_region((void **)&ext_cache, &ext_cache_bytes); - smm_code_bytes = ext_cache - smm_base; - smm_reserved_bytes = smm_bytes - ext_cache_bytes - smm_code_bytes; - smm_reserved = smm_base + smm_bytes - smm_reserved_bytes; - - /* Display the SMM regions */ - printk(BIOS_SPEW, "\nLocation SMM Memory Map Offset\n"); - if (smm_reserved_bytes) { - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - &smm_reserved[smm_reserved_bytes], (u32)smm_bytes); - printk(BIOS_SPEW, " | Other reserved region |\n"); + void *base; + size_t size; + int i; + + printk(BIOS_SPEW, "SMM Memory Map\n"); + + smm_region(&base, &size); + printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + + for (i = 0; i < SMM_SUBREGION_NUM; i++) { + if (smm_subregion(i, &base, &size)) + continue; + printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); } - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - smm_reserved, (u32)(smm_reserved - smm_base)); - printk(BIOS_SPEW, " | external cache |\n"); - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - ext_cache, (u32)(ext_cache - smm_base)); - printk(BIOS_SPEW, " | SMM code |\n"); - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - smm_base, 0); } static void fsp_run_silicon_init(int is_s3_wakeup) diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h index d94f0ad..3d51539 100644 --- a/src/soc/intel/common/memmap.h +++ b/src/soc/intel/common/memmap.h @@ -28,6 +28,24 @@ * this value should be set to 8 MiB. */ size_t mmap_region_granluarity(void); + +/* Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. */ void smm_region(void **start, size_t *size); +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on susccess, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c index 8e96d73..5bb83c9 100644 --- a/src/soc/intel/common/stage_cache.c +++ b/src/soc/intel/common/stage_cache.c @@ -18,22 +18,15 @@ * Foundation, Inc. */ -#include <cbmem.h> +#include <console/console.h> #include <soc/intel/common/memmap.h> -#include <soc/smm.h> #include <stage_cache.h> void stage_cache_external_region(void **base, size_t *size) { - char *smm_base; - size_t smm_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* - * The ramstage cache lives in the TSEG region. - * The top of ram is defined to be the TSEG base address. - */ - smm_region((void **)&smm_base, &smm_size); - *size = cache_size; - *base = (void *)(&smm_base[smm_size - cache_size]); + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 81ec89d..494b259 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -61,6 +61,53 @@ void smm_region(void **start, size_t *size) *size = smm_region_size(); } +/* + * Subregions within SMM + * +-------------------------+ BGSM + * | IED | IED_REGION_SIZE + * +-------------------------+ + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ TSEG + */ +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_CHIPSET: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + void *cbmem_top(void) { /*

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New patch to review for coreboot: intel/common: use external stage cache for fsp_ramstage
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11196 -gerrit commit f0ee3932574ee5fc4746497a8ddd32a37e066c27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 12:26:56 2015 -0500 intel/common: use external stage cache for fsp_ramstage The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/Kconfig | 9 --- src/soc/intel/common/fsp_ramstage.c | 146 +++++++----------------------------- 2 files changed, 27 insertions(+), 128 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index dfbc6bb..ab8c475 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -44,15 +44,6 @@ config DISPLAY_SMM_MEMORY_MAP bool "SMM: Display the SMM memory map" default n -config FSP_CACHE_SIZE - hex "FSP Cache Size in bytes" - default 0 - help - Size of the region in SMM used to cache the FSP binary. This region - size value is used to split the SMM_RESERVED_SIZE config value - into a region specifically for FSP. The remaining region is for - ramstage. - config SOC_INTEL_COMMON_FSP_RAM_INIT bool "FSP: Use the common raminit.c module" default n diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index 1c3c38a..a5728b5 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -40,9 +40,9 @@ __attribute__((weak)) void soc_after_silicon_init(void) * SMM Memory Map: * * +--------------------------+ smm_region_size() ----. - * | FSP Cache | CONFIG_FSP_CACHE_SIZE | + * | FSP Cache | | * +--------------------------+ | - * | SMM Ramstage Cache | + CONFIG_SMM_RESERVED_SIZE + * | SMM Stage Cache | + CONFIG_SMM_RESERVED_SIZE * +--------------------------+ ---------------------' * | SMM Code | * +--------------------------+ smm_base @@ -56,42 +56,27 @@ void stage_cache_external_region(void **base, size_t *size) /* Determine the location of the ramstage cache */ smm_region((void **)&cache_base, &cache_size); - *size = CONFIG_SMM_RESERVED_SIZE - CONFIG_FSP_CACHE_SIZE; + *size = CONFIG_SMM_RESERVED_SIZE; *base = &cache_base[cache_size - CONFIG_SMM_RESERVED_SIZE]; } -static void *smm_fsp_cache_base(size_t *size) -{ - size_t cache_size; - u8 *cache_base; - - /* Determine the location of the FSP cache */ - stage_cache_external_region((void **)&cache_base, &cache_size); - *size = CONFIG_FSP_CACHE_SIZE; - return &cache_base[cache_size]; -} - /* Display SMM memory map */ static void smm_memory_map(void) { u8 *smm_base; size_t smm_bytes; size_t smm_code_bytes; - u8 *fsp_cache; - size_t fsp_cache_bytes; - u8 *ramstage_cache; - size_t ramstage_cache_bytes; + u8 *ext_cache; + size_t ext_cache_bytes; u8 *smm_reserved; size_t smm_reserved_bytes; /* Locate the SMM regions */ smm_region((void **)&smm_base, &smm_bytes); - fsp_cache = smm_fsp_cache_base(&fsp_cache_bytes); - stage_cache_external_region((void **)&ramstage_cache, &ramstage_cache_bytes); - smm_code_bytes = ramstage_cache - smm_base; - smm_reserved = fsp_cache + fsp_cache_bytes; - smm_reserved_bytes = smm_bytes - fsp_cache_bytes - ramstage_cache_bytes - - smm_code_bytes; + stage_cache_external_region((void **)&ext_cache, &ext_cache_bytes); + smm_code_bytes = ext_cache - smm_base; + smm_reserved_bytes = smm_bytes - ext_cache_bytes - smm_code_bytes; + smm_reserved = smm_base + smm_bytes - smm_reserved_bytes; /* Display the SMM regions */ printk(BIOS_SPEW, "\nLocation SMM Memory Map Offset\n"); @@ -102,79 +87,12 @@ static void smm_memory_map(void) } printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", smm_reserved, (u32)(smm_reserved - smm_base)); - printk(BIOS_SPEW, " | FSP binary cache |\n"); - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - fsp_cache, (u32)(fsp_cache - smm_base)); - printk(BIOS_SPEW, " | ramstage cache |\n"); + printk(BIOS_SPEW, " | external cache |\n"); printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - ramstage_cache, (u32)(ramstage_cache - smm_base)); + ext_cache, (u32)(ext_cache - smm_base)); printk(BIOS_SPEW, " | SMM code |\n"); printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", smm_base, 0); - printk(BIOS_ERR, "\nCONFIG_FSP_CACHE_SIZE: 0x%08x bytes\n\n", - CONFIG_FSP_CACHE_SIZE); -} - -struct smm_fsp_cache_header { - void *start; - size_t size; - FSP_INFO_HEADER *fih; -}; - -/* SoC implementation for caching support code. */ -static void soc_save_support_code(void *start, size_t size, - FSP_INFO_HEADER *fih) -{ - u8 *fsp_cache; - size_t fsp_cache_length; - struct smm_fsp_cache_header *header; - size_t smm_fsp_cache_length; - - if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) - smm_memory_map(); - - /* Locate the FSP cache in SMM */ - fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); - - /* Initialize the FSP cache header */ - header = (struct smm_fsp_cache_header *)fsp_cache; - fsp_cache += sizeof(*header); - header->start = start; - header->size = size; - header->fih = fih; - - /* Validate the CONFIG_FSP_CACHE_SIZE value */ - fsp_cache_length = sizeof(*header) + size; - if (smm_fsp_cache_length < fsp_cache_length) { - printk(BIOS_ERR, "CONFIG_FSP_CACHE_SIZE < 0x%08x bytes\n", - (u32)fsp_cache_length); - die("ERROR: Insufficent space to cache FSP binary!\n"); - } - - /* Copy the FSP binary into the SMM region for safe keeping */ - memcpy(fsp_cache, start, size); -} - -/* SoC implementation for restoring support code after S3 resume. Returns - * previously passed fih pointer from soc_save_support_code(). */ -static FSP_INFO_HEADER *soc_restore_support_code(void) -{ - u8 *fsp_cache; - struct smm_fsp_cache_header *header; - size_t smm_fsp_cache_length; - - /* Locate the FSP cache in SMM */ - fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); - - /* Get the FSP cache header */ - header = (struct smm_fsp_cache_header *)fsp_cache; - fsp_cache += sizeof(*header); - - /* Copy the FSP binary from the SMM region back into RAM */ - memcpy(header->start, fsp_cache, header->size); - - /* Return the FSP_INFO_HEADER address */ - return header->fih; } static void fsp_run_silicon_init(int is_s3_wakeup) @@ -261,64 +179,54 @@ static void fsp_run_silicon_init(int is_s3_wakeup) soc_after_silicon_init(); } -static void fsp_cache_save(void) +static void fsp_cache_save(struct prog *fsp) { - const struct cbmem_entry *fsp_entry; - FSP_INFO_HEADER *fih; - - fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE); - - if (fsp_entry == NULL) { - printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n"); - return; - } - - fih = fsp_get_fih(); + if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) + smm_memory_map(); - if (fih == NULL) { - printk(BIOS_ERR, "ERROR: No FIH found.\n"); + if (prog_entry(fsp) == NULL) { + printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n"); return; } - soc_save_support_code(cbmem_entry_start(fsp_entry), - cbmem_entry_size(fsp_entry), fih); + stage_cache_add(STAGE_REFCODE, fsp); } -static int fsp_find_and_relocate(void) +static int fsp_find_and_relocate(struct prog *fsp) { - struct prog fsp_prog = PROG_INIT(ASSET_REFCODE, "fsp.bin"); struct region_device fsp_rdev; uint32_t type = CBFS_TYPE_FSP; - if (cbfs_boot_locate(&fsp_rdev, prog_name(&fsp_prog), &type)) { + if (cbfs_boot_locate(&fsp_rdev, prog_name(fsp), &type)) { printk(BIOS_ERR, "ERROR: Couldn't find fsp.bin in CBFS.\n"); return -1; } - if (fsp_relocate(&fsp_prog, &fsp_rdev)) { + if (fsp_relocate(fsp, &fsp_rdev)) { printk(BIOS_ERR, "ERROR: FSP relocation failed.\n"); return -1; } - /* FSP_INFO_HEADER is set as the program entry. */ - fsp_update_fih(prog_entry(&fsp_prog)); - return 0; } void intel_silicon_init(void) { + struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); if (is_s3_wakeup) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); - fsp_update_fih(soc_restore_support_code()); + stage_cache_load_stage(STAGE_REFCODE, &fsp); } else { - fsp_find_and_relocate(); + fsp_find_and_relocate(&fsp); printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); - fsp_cache_save(); + fsp_cache_save(&fsp); } + /* FSP_INFO_HEADER is set as the program entry. */ + fsp_update_fih(prog_entry(&fsp)); + fsp_run_silicon_init(is_s3_wakeup); }

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New patch to review for coreboot: skylake: clean up SMM region calculations
by Aaron Durbin 12 Aug '15

12 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11195 -gerrit commit 4c6c459dc39a7f5f2ac00447ba32f292d75447f8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 14:33:37 2015 -0500 skylake: clean up SMM region calculations The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/smm.h | 1 - src/soc/intel/skylake/memmap.c | 31 +++++++++++++++++++------------ 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index d895302..fbae6ef 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -51,7 +51,6 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -#define smm_region_size mmap_region_granluarity #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) int smm_initialize(void); void smm_relocate(void); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index bba93cb..81ec89d 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -25,6 +25,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> +#include <stdlib.h> size_t mmap_region_granluarity(void) { @@ -34,24 +35,30 @@ size_t mmap_region_granluarity(void) return CONFIG_SMM_TSEG_SIZE; /* Make it 8MiB by default. */ - return 8 << 20; + return 8*MiB; } -static void *smm_region_start(void) +/* Returns base of requested region encoded in the system agent. */ +static inline uintptr_t system_agent_region_base(size_t reg) { - /* - * SMM base address matches the top of DPR. The DPR register has - * 1 MiB alignment and reports the TOP of the DPR range. - */ - uint32_t smm_base = pci_read_config32(SA_DEV_ROOT, DPR); - smm_base = ALIGN_DOWN(smm_base, 1 << 20); - return (void *)smm_base; + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, reg), 1*MiB); +} + +static inline uintptr_t smm_region_start(void) +{ + return system_agent_region_base(TSEG); +} + +static inline size_t smm_region_size(void) +{ + return system_agent_region_base(BGSM) - smm_region_start(); } void smm_region(void **start, size_t *size) { - *start = smm_region_start(); - *size = mmap_region_granluarity(); + *start = (void *)smm_region_start(); + *size = smm_region_size(); } void *cbmem_top(void) @@ -84,7 +91,7 @@ void *cbmem_top(void) * +-------------------------+ */ - unsigned long top_of_ram = (unsigned long)smm_region_start(); + uintptr_t top_of_ram = smm_region_start(); /* * Subtract DMA Protected Range size if enabled and align to a multiple

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coreboot-gerrit August 2015