coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: buildgcc: Fix the options check
by Zheng Bao 13 Aug '15

13 Aug '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11158 -gerrit commit 958b701a079f825d7f0a2909a4bc6263e52c1aa9 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Aug 11 02:43:46 2015 -0400 buildgcc: Fix the options check 1. Add -P|--package to build iasl 2. Remove -G|--skip-gdb, which was to skip gdb. 3. Add -S|--scripting to build gdb 4. Remove -C|--clang, which was to build clang. All these changes are aligned with the options parsing below. The help text is correct. Change-Id: I897ea5e8ab002086e45bf05ff33230815b246057 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index eaeafcf..bd0d8ef 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -499,11 +499,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache,clang Vhcd:p:j:D:tGyC -- "$@") + args=$(getopt -l version,help,clean,directory:,platform:,package:,jobs:,destdir:,savetemps,scripting,ccache Vhcd:p:P:j:D:tSy -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:j:D:tGyC $*) + args=$(getopt Vhcd:p:P:j:D:tSy $*) set -- $args fi

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Patch merged into coreboot/master: board-status: move board status back to $TMPDIR
by gerrit＠coreboot.org 13 Aug '15

13 Aug '15

the following patch was just integrated into master: commit aa7dcef49427bde74ae4ddb48f6ed9823661a4a5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Aug 13 07:57:26 2015 +0200 board-status: move board status back to $TMPDIR Change-Id: I05a8c246384abfc954cfcf163a68cca71aa6b2f0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11224 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/11224 for details. -gerrit

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New patch to review for coreboot: board-status: move board status back to $TMPDIR
by Patrick Georgi 13 Aug '15

13 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11224 -gerrit commit 5202149a543f90ce2c4a793e40e3e67a96753bd8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Aug 13 07:57:26 2015 +0200 board-status: move board status back to $TMPDIR Change-Id: I05a8c246384abfc954cfcf163a68cca71aa6b2f0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/board_status/board_status.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 14d6514..ee27bc0 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -211,7 +211,8 @@ fi # Results will be placed in a temporary location until we're ready to upload. # If the user does not wish to upload, results will remain in /tmp. -tmpdir=$(mktemp -d coreboot_board_status.XXXXXXXX) +tmpdir=$(mktemp -d --tmpdir coreboot_board_status.XXXXXXXX) +tmpcfg=$(mktemp coreboot_config.XXXXXX) cbfstool_cmd="build/cbfstool" if test ! -x build/cbfstool; then @@ -219,8 +220,11 @@ if test ! -x build/cbfstool; then fi test_cmd $LOCAL "$cbfstool_cmd" $cbfstool_cmd build/coreboot.rom extract -n config -f ${tmpdir}/config.txt -cp ${tmpdir}/config.txt ${tmpdir}/config.short.txt -yes "" | make DOTCONFIG=${tmpdir}/config.txt oldconfig +mv ${tmpdir}/config.txt ${tmpdir}/config.short.txt +cp ${tmpdir}/config.short.txt ${tmpcfg} +yes "" | make DOTCONFIG=${tmpcfg} oldconfig 2>/dev/null >/dev/null +mv ${tmpcfg} ${tmpdir}/config.txt +rm -f ${tmpcfg}.old $cbfstool_cmd build/coreboot.rom print > ${tmpdir}/cbfs.txt # Obtain board and revision info to form the directory structure:

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New patch to review for coreboot: Revert "SeaBIOS: fix reproducible build by defining our own version string"
by Kevin O'Connor 12 Aug '15

12 Aug '15

Kevin O'Connor (kevin(a)koconnor.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11223 -gerrit commit cb2d3a48eafd12b6443d1c44436ffb2432c8077e Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Wed Aug 12 18:38:59 2015 -0400 Revert "SeaBIOS: fix reproducible build by defining our own version string" This reverts commit 633886719e2853744d932bd15324dd21634b0bbb. The SeaBIOS maintainer (Kevin O'Connor) has requested that default builds of SeaBIOS continue to use the default SeaBIOS version string. The commit above changed the default for coreboot builds of SeaBIOS. This non-standard version string contains less information and it makes it harder for SeaBIOS developers to respond to trouble reports. Change-Id: I65f039b06dc4ee857b200bc2b67eea503fa7f537 Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- payloads/external/SeaBIOS/Makefile.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 7fb63d4..7390dd3 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -47,9 +47,6 @@ endif build: config echo " MAKE SeaBIOS $(TAG-y)" - export VERSION=$$(cd seabios && \ - git describe --tags --long --dirty 2>/dev/null || \ - echo "unknown") ; \ $(MAKE) -C seabios OUT=out/ clean:

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Patch merged into coreboot/master: getac/p470: enable early cbmem init
by gerrit＠coreboot.org 12 Aug '15

12 Aug '15

the following patch was just integrated into master: commit 608f9b5b165c141efd4cb51fbecaa846e28b7992 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Aug 11 10:35:25 2015 +0200 getac/p470: enable early cbmem init Change-Id: I4afec92c57c6af4c99858afae53fa7746f47bc7a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11159 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11159 for details. -gerrit

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Patch merged into coreboot/master: getac/p470: Enable native VGA init
by gerrit＠coreboot.org 12 Aug '15

12 Aug '15

the following patch was just integrated into master: commit 33cfe9b0f8349b2a0470294387bc4d19086562f5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 6 17:23:30 2014 +0200 getac/p470: Enable native VGA init Change-Id: I6c5a2324d1a9e21f4e052678be8f0e0dbfed6494 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11136 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11136 for details. -gerrit

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Patch merged into coreboot/master: getac/p470: Add C-State values
by gerrit＠coreboot.org 12 Aug '15

12 Aug '15

the following patch was just integrated into master: commit 21a78a88c6113eeeee565b610833e2dc9c5cfbaa Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Aug 9 09:22:30 2015 +0200 getac/p470: Add C-State values Derived from what the vendor BIOS is doing. Change-Id: Ie2cba7b86b6bb3f1dcc4a5e1c189aa45d0aab109 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: fwts 15.08 Reviewed-on: http://review.coreboot.org/11142 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11142 for details. -gerrit

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Patch set updated for coreboot: cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11211 -gerrit commit b545e9587f5fe5033eec8485a85bfba8dabd34e0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Aug 12 11:19:10 2015 -0500 cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled In the wake of the recent Intel APIC SMM exploit a code review of the AMD SMM code was undertaken. Native Family 10h initialization does not require SMM to function, and the SMM memory range initialization should only be executed if SMM will be used on the target platform. Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/model_10xxx_init.c | 34 ++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c17f335..590b89d 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -99,15 +99,31 @@ static void model_10xxx_init(device_t dev) msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(SMM_MASK_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n"); + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(SMM_MASK_MSR); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(SMM_MASK_MSR, msr); + } else { + printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n"); + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Disable the SMM memory window */ + msr.hi = 0x0; + msr.lo = 0x0; + wrmsr(SMM_MASK_MSR, msr); + } /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR);

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Patch set updated for coreboot: cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11211 -gerrit commit 2f6d3e1fc3730380309a68dd025313e2fcc3c86e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Aug 12 11:19:10 2015 -0500 cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled In the wake of the recent Intel APIC SMM exploit a code review of the AMD SMM code was undertaken. Native Family 10h initialization does not require SMM to function, and the SMM memory range initialization should only be executed if SMM will be used on the target platform. Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/model_10xxx_init.c | 35 ++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c17f335..40a8489 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -99,15 +99,32 @@ static void model_10xxx_init(device_t dev) msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); - /* Set SMM base address for this CPU */ - msr = rdmsr(SMM_BASE_MSR); - msr.lo = SMM_BASE - (lapicid() * 0x400); - wrmsr(SMM_BASE_MSR, msr); - - /* Enable the SMM memory window */ - msr = rdmsr(SMM_MASK_MSR); - msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ - wrmsr(SMM_MASK_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n"); + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(SMM_MASK_MSR); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(SMM_MASK_MSR, msr); + } + else { + printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n"); + + /* Set SMM base address for this CPU */ + msr = rdmsr(SMM_BASE_MSR); + msr.lo = SMM_BASE - (lapicid() * 0x400); + wrmsr(SMM_BASE_MSR, msr); + + /* Disable the SMM memory window */ + msr.hi = 0x0; + msr.lo = 0x0; + wrmsr(SMM_MASK_MSR, msr); + } /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR);

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Patch set updated for coreboot: libpayload: usb: dwc2: fix short packet transfer
by Patrick Georgi 12 Aug '15

12 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11187 -gerrit commit ef1e44f34e44298959945afac5a25595728e3577 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Fri Jul 24 16:12:42 2015 +0800 libpayload: usb: dwc2: fix short packet transfer If short packet detected, stop this transfer and return the actual transferred size BUG=chrome-os-partner:42817 TEST=Netboot could run well BRANCH=None Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288215 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba) Original-Reviewed-on: https://chromium-review.googlesource.com/291064 Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> --- payloads/libpayload/drivers/usb/dwc2.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index a3979e5..267dea7 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -174,8 +174,6 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) return -HCSTAT_BABBLE; else if (hcint.stall) return -HCSTAT_STALL; - else if (hcint.ack) - return -HCSTAT_ACK; else if (hcint.nyet) return -HCSTAT_NYET; else @@ -209,7 +207,7 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) static int dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, - uint32_t ch_num, u8 *data_buf) + uint32_t ch_num, u8 *data_buf, int *short_pkt) { uint32_t do_copy; int ret; @@ -277,6 +275,10 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, if (do_copy && (dir == EPDIR_IN)) memcpy(data_buf, aligned_buf, transferred); + + if ((short_pkt != NULL) && (dir == EPDIR_IN)) + *short_pkt = (ret > 0) ? 1 : 0; + } /* Save data toggle */ @@ -292,7 +294,8 @@ dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, static int dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, - uint32_t ch_num, u8 *data_buf, split_info_t *split) + uint32_t ch_num, u8 *data_buf, split_info_t *split, + int *short_pkt) { dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); hfnum_t hfnum; @@ -311,7 +314,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, /* Handle Start-Split */ ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num, - data_buf); + data_buf, NULL); if (ret < 0) goto out; @@ -326,7 +329,7 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, /* Handle Complete-Split */ do { ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle, - dir, ch_num, data_buf); + dir, ch_num, data_buf, short_pkt); } while (ret == -HCSTAT_NYET); if (dir == EPDIR_IN) @@ -360,15 +363,17 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, u8 *src, uint8_t skip_nak) { split_info_t split; - int ret, transferred = 0, timeout = 3000; + int ret, short_pkt, transferred = 0, timeout = 3000; ep->toggle = pid; do { + short_pkt = 0; if (dwc2_need_split(ep->dev, &split)) { nak_retry: - ret = dwc2_split_transfer(ep, size, ep->toggle, dir, 0, - src, &split); + ret = dwc2_split_transfer(ep, MIN(ep->maxpacketsize, + size), ep->toggle, dir, 0, src, &split, + &short_pkt); /* * dwc2_split_transfer() waits for the next FullSpeed @@ -380,7 +385,8 @@ nak_retry: goto nak_retry; } } else { - ret = dwc2_do_xfer(ep, size, pid, dir, 0, src); + ret = dwc2_do_xfer(ep, MIN(DMA_SIZE, size), pid, dir, 0, + src, &short_pkt); } if (ret < 0) @@ -389,7 +395,8 @@ nak_retry: size -= ret; src += ret; transferred += ret; - } while (size > 0); + + } while (size > 0 && !short_pkt); return transferred; }

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coreboot-gerrit August 2015