coreboot-gerrit August 2015

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Patch set updated for coreboot: AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0
by WANG Siyuan 12 Aug '15

12 Aug '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11148 -gerrit commit 83d28f706c265b1bc641fa7c7fbb50c2618ce3e4 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Aug 10 06:43:31 2015 +0800 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0 This is required the BLOB change Icb7a4f07 "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)" This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/vendorcode/amd/pi/00660F01/AGESA.h | 82 ++++++++++++++-------- .../pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h | 23 ++++-- .../amd/pi/00660F01/Proc/CPU/cpuRegisters.h | 4 +- .../amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h | 1 + .../pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 11 ++- 5 files changed, 86 insertions(+), 35 deletions(-) diff --git a/src/vendorcode/amd/pi/00660F01/AGESA.h b/src/vendorcode/amd/pi/00660F01/AGESA.h index 17205b1..5f0e3f9 100644 --- a/src/vendorcode/amd/pi/00660F01/AGESA.h +++ b/src/vendorcode/amd/pi/00660F01/AGESA.h @@ -1189,16 +1189,21 @@ typedef enum { DDR2_TECHNOLOGY, ///< DDR2 technology DDR3_TECHNOLOGY, ///< DDR3 technology GDDR5_TECHNOLOGY, ///< GDDR5 technology + DDR4_TECHNOLOGY, ///< DDR4 technology UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology } TECHNOLOGY_TYPE; /// Low voltage support typedef enum { - VOLT_INITIAL, ///< Initial value for VDDIO - VOLT1_5, ///< 1.5 Volt - VOLT1_35, ///< 1.35 Volt - VOLT1_25, ///< 1.25 Volt - VOLT_UNSUPPORTED = 0xFF ///< No common voltage found + VOLT_INITIAL, ///< Initial value for VDDIO + VOLT1_5, ///< 1.5 Volt + VOLT1_35, ///< 1.35 Volt + VOLT1_25, ///< 1.25 Volt + VOLT_DDR4_RANGE_START, ///< Start of DDR4 Voltage Range + VOLT1_2 = VOLT_DDR4_RANGE_START, ///< 1.2 Volt + VOLT_TBD1, ///< TBD1 Voltage + VOLT_TBD2, ///< TBD2 Voltage + VOLT_UNSUPPORTED = 0xFF ///< No common voltage found } DIMM_VOLTAGE; /// AMP voltage support @@ -1369,19 +1374,11 @@ typedef enum { /// /// SPD Data for each DIMM. /// -typedef struct _SPD_DEF_STRUCT_DX { - IN BOOLEAN SpdValid; ///< Indicates that the SPD is valid - IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT32 Adderess; ///< SMBus Address - IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM -} SPD_DEF_STRUCT_DX; - -//----------------------------------------------------------------------------- -/// -/// SPD Data for each DIMM. -/// typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid + IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to + ///< 0 = Lower Page + ///< 1 = Upper Page (DDR4 Only) IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; @@ -1566,11 +1563,8 @@ typedef struct _CH_DEF_STRUCT { OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved - - OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. - + OUT UINT8 DimmThermSensorPresent; ///< For each bit n 0..3, 1 = DIMM n has an On Dimm Thermal Sensor where 4..7 are reserved OUT UINT8 MaxVref; ///< Maximum Vref Value for channel - OUT UINT8 Reserved[100]; ///< Reserved } CH_DEF_STRUCT; @@ -1604,6 +1598,9 @@ typedef struct _CH_TIMING_STRUCT { OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs + OUT UINT16 DIMMTrrdL; ///< Minimax TrrdL*40 (ns) of DIMMs + OUT UINT16 DIMMTwtrL; ///< Minimax TtwrL*40 (ns) of DIMMs + OUT UINT16 DIMMTccdL; ///< Minimax TccdL*40 (ns) of DIMMs OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz OUT UINT16 Speed; ///< DRAM bus speed in MHz ///< 400 (MHz) @@ -1622,10 +1619,14 @@ typedef struct _CH_TIMING_STRUCT { OUT UINT8 Trrd; ///< DCT Trrd (busclocks) OUT UINT8 Twtr; ///< DCT Twtr (busclocks) OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) + OUT UINT8 TrrdL; ///< DCT TrrdL (busclocks) + OUT UINT8 TwtrL; ///< DCT TwtrL (busclocks) + OUT UINT8 TccdL; ///< DCT TccdL (busclocks) OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns) OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns) OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns) OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns) + OUT UINT16 Trfc4; ///< DCT Trfc4min All DIMMS (in ns) - DDR4 Only OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. ///< OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) @@ -1788,7 +1789,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< OUT UINT32 SysLimit; ///< Limit[47:16] (system address). ///< - OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. + OUT DIMM_VOLTAGE DDRVoltage; ///< Find support voltage and send back to platform BIOS for DDR3 or DDR4. ///< OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and @@ -1892,7 +1893,15 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< - TRUE =enable ///< ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} - // Extended temperature range + + // Temperature Controlled Refresh + + IN BOOLEAN DramTempControlledRefreshEn; ///< Enable Temperature Controlled Refresh + ///< - FALSE = Disable + ///< - TRUE = Enable (Default) + ///< @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} + ///< If EnableExtendedTemperatureRange is enabled with this feature + ///< then CfgDramDoubleRefreshrate must also be enabled. // Online Spare @@ -2072,13 +2081,12 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< TRUE = Enable, platfrom BIOS requests support for DDR4 ///< FALSE = Disable, platform BIOS requests no DDR4 support ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} - IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable + IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable ///< TRUE = Enable, platfrom BIOS requests support for DDR3 ///< FALSE = Disable, platform BIOS requests no DDR3 support ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} IN UINT16 CustomVddioSupport; ///< CustomVddioSupport ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} - } MEM_PARAMETER_STRUCT; @@ -2198,6 +2206,8 @@ typedef union { ///< cannot be applied to current configurations. #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match #define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue +#define MEM_ALERT_DRAM_DOUBLE_REFRESH_RATE_ENABLED 0x04010300ul ///< CfgDramDoubleRefreshRate has been enabled due + /// to Extended Temperature Range feature // AGESA_ERROR Memory Errors #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS @@ -2249,6 +2259,8 @@ typedef union { #define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found #define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found #define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found +#define MEM_ERROR_CAD_BUS_TMG_NOT_FOUND 0x040E3500ul ///< No CAD Bus Timing Entries found +#define MEM_ERROR_DATA_BUS_CFG_NOT_FOUND 0x040F3500ul ///< No Data Bus Config Entries found #define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window #define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height #define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error @@ -2306,7 +2318,7 @@ typedef union { // AGESA_CRITICAL Memory Errors #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3 -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2 +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR4 0x040A1F00ul ///< Heap allocation error for DMI table for DDR4 #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported #define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info @@ -2886,6 +2898,7 @@ typedef struct { IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range + IN BOOLEAN CfgDramTempControlledRefreshEn; ///< Temperature Controlled Refresh Rate - @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} IN UINT32 CfgPowerDownMode; ///< Power Down Mode. IN BOOLEAN CfgOnlineSpare; ///< Online Spare. IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. @@ -2938,7 +2951,7 @@ typedef struct { IN UINT8 CfgAbmSupport; ///< Abm Support IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control - IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. + IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID @@ -2985,6 +2998,10 @@ typedef struct { ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING} IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable ///< when it is mixed with other technology types. + IN BOOLEAN CfgDimmTypeDdr4Capable; ///< Select DDR4 as technology type that AGESA will enable + ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} + IN BOOLEAN CfgDimmTypeDdr3Capable; ///< Select DDR3 as technology type that AGESA will enable + ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE} IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured) @@ -3141,6 +3158,10 @@ typedef struct { OUT UINT16 T4ProcFamily2; ///< Family 2 OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer + OUT UINT16 T4CoreCount2; ///< Core count 2 + OUT UINT16 T4CoreEnabled2; ///< Core Enable 2 + OUT UINT16 T4ThreadCount2; ///< Thread count 2 + } TYPE4_DMI_INFO; /// DMI Type 7 - Cache information @@ -3250,7 +3271,12 @@ typedef enum { Ddr2MemType, ///< Assign 19 to DDR2 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM Ddr3MemType = 0x18, ///< Assign 24 to DDR3 - Fbd2MemType ///< Assign 25 to FBD2 + Fbd2MemType, ///< Assign 25 to FBD2 + Ddr4MemType, ///< Assign 26 to DDR4 + LpDdrMemType, ///< Assign 27 to LPDDR + LpDdr2MemType, ///< Assign 28 to LPDDR2 + LpDdr3MemType, ///< Assign 29 to LPDDR3 + LpDdr4MemType, ///< Assign 30 to LPDDR4 } DMI_T17_MEMORY_TYPE; /// DMI Type 17 offset 13h - Type Detail @@ -3270,7 +3296,7 @@ typedef struct { OUT UINT16 NonVolatile:1; ///< Non-volatile OUT UINT16 Registered:1; ///< Registered (Buffered) OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) - OUT UINT16 Reserved2:1; ///< Reserved + OUT UINT16 LRDIMM:1; ///< LRDIMM } DMI_T17_TYPE_DETAIL; /// DMI Type 17 - Memory Device diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h index c4be628..62ef892 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h @@ -69,7 +69,11 @@ // Family 15h equates #define AMD_FAMILY_15_CZ 0x0004u #define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ) -#define AMD_FAMILY_15 AMD_FAMILY_15_CZ + +#define AMD_FAMILY_15_ST 0x0008u +#define AMD_FAMILY_ST (AMD_FAMILY_15_ST) + +#define AMD_FAMILY_15 (AMD_FAMILY_15_CZ | AMD_FAMILY_ST) // Family Unknown #define AMD_FAMILY_UNKNOWN 0x8000u @@ -81,12 +85,23 @@ // Family 15h CZ steppings #define AMD_F15_CZ_A0 0x0001u #define AMD_F15_CZ_A1 0x0002u +#define AMD_F15_BR_A1 0x0004u + // Family 15h ST steppings +#define AMD_F15_ST_A0 0x0010u // Family 15h Unknown stepping #define AMD_F15_UNKNOWN 0x8000u -#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1) -#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax) + // CZ and BR +#define AMD_F15_BR_Ax (AMD_F15_BR_A1) +#define AMD_F15_BR_ALL (AMD_F15_BR_Ax) + +#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1 | AMD_F15_BR_Ax) +#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax | AMD_F15_BR_ALL) + + // ST +#define AMD_F15_ST_Ax (AMD_F15_ST_A0) +#define AMD_F15_ST_ALL (AMD_F15_ST_Ax) -#define AMD_F15_ALL AMD_F15_CZ_ALL +#define AMD_F15_ALL (AMD_F15_CZ_ALL | AMD_F15_ST_ALL) #endif // _CPU_FAM_REGISTERS_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index e51a01f..889be76 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -429,14 +429,14 @@ typedef struct { #define CPUID_EXT_FAMILY_MASK 0x0FF00000ul #define CZ_SOCKET_FP4 0 +#define ST_SOCKET_FP4 0 +#define ST_SOCKET_FT4 3 #define SOCKET_IGNORE 0xF #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull #define APIC_EXT_BRDCST_MASK 0x000E0000ul #define APIC_ENABLE_BIT 0x00000800ul -#ifndef LOCAL_APIC_ADDR #define LOCAL_APIC_ADDR 0xFEE00000ul -#endif #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h index fb2bae2..35a76d2 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -986,6 +986,7 @@ typedef struct { VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings + BOOLEAN NoClearThermalTripSts; /// Skip clearing ThermalTrip status } FCH_ACPI; diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index c18e191..6108274 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -68,6 +68,11 @@ #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR #define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset +#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port +#define PMIO_DATA_PORT 0xCD7 ///Pmio data port + +#define PMIO_REG62 0x62 ///PMIOx62 + //====================================================================================== // // Define Mailbox Status field @@ -162,7 +167,7 @@ GetPspMboxStatus ( BOOLEAN -PspBarInitEarly (void); +PspBarInitEarly (VOID); VOID PspLibPciIndirectRead ( @@ -184,4 +189,8 @@ UINT8 PspLibAccessWidth ( IN ACCESS_WIDTH AccessWidth ); + +BOOLEAN +IsS3Resume (VOID); + #endif // _AMD_LIB_H_

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Patch set updated for coreboot: cpu/amd/microcode: Update microcode parser to handle expanded blob files
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11164 -gerrit commit c53345a3d6abcccaa71183d6613edb74ea5b674e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 19:14:34 2015 -0500 cpu/amd/microcode: Update microcode parser to handle expanded blob files The Family 15h microcode files provided by AMD are approximately 1.5x larger than the Family 10h and K8 files currently in the coreboot tree. As a result, they exceed the 2k/update size limit of coreboot's update mechanism. To handle the increased microcode size, coreboot's AMD microcode file format was changed to 4k/update in a separate commit to the blobs repository. This patch allows parsing of that updated format. Change-Id: Id6aeff0c65d151a9741c83c2872676427932e6e0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/microcode/microcode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 45e4bf0..b12e2cf 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -83,13 +83,13 @@ static void amd_update_microcode(const void *ucode, size_t ucode_len, const uint8_t *c = ucode; const uint8_t *ucode_end = (uint8_t*)ucode + ucode_len; - while (c <= (ucode_end - 2048)) { + while (c <= (ucode_end - 4096)) { m = (struct microcode *)c; if (m->processor_rev_id == equivalent_processor_rev_id) { apply_microcode_patch(m); break; } - c += 2048; + c += 4096; } }

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Patch set updated for coreboot: cpu/amd/microcode: Update microcode parser to handle expanded blob files
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11164 -gerrit commit 4592fbc5dcf4ae28afe96e8cd964f30e6aa726e9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 19:14:34 2015 -0500 cpu/amd/microcode: Update microcode parser to handle expanded blob files The Family 15h microcode files provided by AMD are approximately 1,5x larger than the Family 10h and K8 files currently in the coreboot tree. As a result, they exceed the 2k/update size limit of coreboot's update mechanism. To handle the increased microcode size, coreboot's AMD microcode file format was changed to 4k/update in a separate commit to the blobs repository. This patch allows parsing of that updated format. Change-Id: Id6aeff0c65d151a9741c83c2872676427932e6e0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/microcode/microcode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 45e4bf0..b12e2cf 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -83,13 +83,13 @@ static void amd_update_microcode(const void *ucode, size_t ucode_len, const uint8_t *c = ucode; const uint8_t *ucode_end = (uint8_t*)ucode + ucode_len; - while (c <= (ucode_end - 2048)) { + while (c <= (ucode_end - 4096)) { m = (struct microcode *)c; if (m->processor_rev_id == equivalent_processor_rev_id) { apply_microcode_patch(m); break; } - c += 2048; + c += 4096; } }

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New patch to review for coreboot: cpu/amd/microcode: Update microcode parser to handle expanded blob files
by Timothy Pearson 12 Aug '15

12 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11164 -gerrit commit 6ee94978c21f68e9127259144171761347f054fa Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 19:14:34 2015 -0500 cpu/amd/microcode: Update microcode parser to handle expanded blob files Change-Id: Id6aeff0c65d151a9741c83c2872676427932e6e0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/microcode/microcode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 45e4bf0..b12e2cf 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -83,13 +83,13 @@ static void amd_update_microcode(const void *ucode, size_t ucode_len, const uint8_t *c = ucode; const uint8_t *ucode_end = (uint8_t*)ucode + ucode_len; - while (c <= (ucode_end - 2048)) { + while (c <= (ucode_end - 4096)) { m = (struct microcode *)c; if (m->processor_rev_id == equivalent_processor_rev_id) { apply_microcode_patch(m); break; } - c += 2048; + c += 4096; } }

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Patch set updated for coreboot: emulation/qemu: Serialize IQCR method
by Paul Menzel 11 Aug '15

11 Aug '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11162 -gerrit commit 0f4505b1db32a0fd04d442618d3d262fb1ed2b63 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Aug 11 22:01:00 2015 +0200 emulation/qemu: Serialize IQCR method Fix the remark below for the mainboards qemu-i440x and qemu-q35. Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150717-32 Copyright (c) 2000 - 2015 Intel Corporation dsdt.aml 336: Method(IQCR, 1, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ASL Input: dsdt.aml - 399 lines, 16756 bytes, 245 keywords AML Output: dsdt.aml - 4000 bytes, 146 named objects, 99 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 233 Optimizations Change-Id: Ibe48f872768ab8295d6fed3359d9eef04b736a05 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 2 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 569d0d5..8594f38 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -233,7 +233,7 @@ DefinitionBlock ( } Return (0x0B) } - Method(IQCR, 1, NotSerialized) { + Method(IQCR, 1, Serialized) { // _CRS method - get current settings Name(PRR0, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0 } diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a160cbc..9cee022 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -331,7 +331,7 @@ DefinitionBlock ( } Return (0x0B) } - Method(IQCR, 1, NotSerialized) { + Method(IQCR, 1, Serialized) { // _CRS method - get current settings Name(PRR0, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0 }

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New patch to review for coreboot: emulation/qemu: Serialize IQCR method
by Paul Menzel 11 Aug '15

11 Aug '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11162 -gerrit commit 69e216e2f5c1227d47ba0c22232eb73a42402ddb Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Aug 11 22:01:00 2015 +0200 emulation/qemu: Serialize IQCR method Fix the warning below for the mainboards qemu-i440x and qemu-q35. Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150717-32 Copyright (c) 2000 - 2015 Intel Corporation dsdt.aml 336: Method(IQCR, 1, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ASL Input: dsdt.aml - 399 lines, 16756 bytes, 245 keywords AML Output: dsdt.aml - 4000 bytes, 146 named objects, 99 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 233 Optimizations Change-Id: Ibe48f872768ab8295d6fed3359d9eef04b736a05 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 2 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 569d0d5..8594f38 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -233,7 +233,7 @@ DefinitionBlock ( } Return (0x0B) } - Method(IQCR, 1, NotSerialized) { + Method(IQCR, 1, Serialized) { // _CRS method - get current settings Name(PRR0, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0 } diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a160cbc..9cee022 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -331,7 +331,7 @@ DefinitionBlock ( } Return (0x0B) } - Method(IQCR, 1, NotSerialized) { + Method(IQCR, 1, Serialized) { // _CRS method - get current settings Name(PRR0, ResourceTemplate() { Interrupt(, Level, ActiveHigh, Shared) { 0 }

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Patch set updated for coreboot: Store the payload config and revision in CBFS
by Martin Roth 11 Aug '15

11 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10607 -gerrit commit aba53f2acf516cfc8a36fbe97910f274bb73ae99 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 20:50:59 2015 -0600 Store the payload config and revision in CBFS Store the payload config and version files in CBFS if using a SeaBIOS or filo payload if INCLUDE_CONFIG_FILE is enabled. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 10 ++++++++++ payloads/external/Makefile.inc | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 1f74bbe..ad421b7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -645,6 +645,16 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) endif endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG $(PAYLOAD_CONFIG)\n" + if [ -f "$(PAYLOAD_CONFIG)" ]; then \ + $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_CONFIG)" -n payload_config -t raw; \ + fi + @printf " REVISION $(PAYLOAD_VERSION)\n" + if [ -f "$(PAYLOAD_VERSION)" ]; then \ + $(CBFSTOOL) $@.tmp add -f "$(PAYLOAD_VERSION)" -n payload_revision -t raw; \ + fi +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ad1a3ef..f80e420 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -32,6 +32,17 @@ ifeq ($(CONFIG_PAYLOAD_GRUB2),y) COREBOOT_ROM_DEPENDENCIES+=grub2 endif +###################################################################### +# set up payload config and version files for later inclusion +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config +PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/version.c +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +PAYLOAD_CONFIG=payloads/external/FILO/filo/.config +PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +endif + SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \

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Patch merged into coreboot/master: getac/p470: Clean up SIO access in ACPI
by gerrit＠coreboot.org 11 Aug '15

11 Aug '15

the following patch was just integrated into master: commit 82fe90829b73241c0d100daec7067c263b8a9093 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Aug 11 10:54:15 2015 +0200 getac/p470: Clean up SIO access in ACPI This adapts Ia5101d5a1 for the p470. Change-Id: Ib09a0bc58fddd6240834cc890f00df91a74f4161 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11160 for details. -gerrit

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Patch set updated for coreboot: AMD Merlin Falcon vendorcode: update to CarrizoPI 1.1.0.0
by WANG Siyuan 11 Aug '15

11 Aug '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11148 -gerrit commit f73df151f4108bc99e509a2de3c445c11b00392b Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Aug 10 06:43:31 2015 +0800 AMD Merlin Falcon vendorcode: update to CarrizoPI 1.1.0.0 This is required the BLOB change Icb7a4f07 "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)" This is tested by Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC works. Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/vendorcode/amd/pi/00660F01/AGESA.h | 82 ++++++++++++++-------- .../pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h | 23 ++++-- .../amd/pi/00660F01/Proc/CPU/cpuRegisters.h | 4 +- .../amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h | 1 + .../pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 11 ++- 5 files changed, 86 insertions(+), 35 deletions(-) diff --git a/src/vendorcode/amd/pi/00660F01/AGESA.h b/src/vendorcode/amd/pi/00660F01/AGESA.h index 17205b1..5f0e3f9 100644 --- a/src/vendorcode/amd/pi/00660F01/AGESA.h +++ b/src/vendorcode/amd/pi/00660F01/AGESA.h @@ -1189,16 +1189,21 @@ typedef enum { DDR2_TECHNOLOGY, ///< DDR2 technology DDR3_TECHNOLOGY, ///< DDR3 technology GDDR5_TECHNOLOGY, ///< GDDR5 technology + DDR4_TECHNOLOGY, ///< DDR4 technology UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology } TECHNOLOGY_TYPE; /// Low voltage support typedef enum { - VOLT_INITIAL, ///< Initial value for VDDIO - VOLT1_5, ///< 1.5 Volt - VOLT1_35, ///< 1.35 Volt - VOLT1_25, ///< 1.25 Volt - VOLT_UNSUPPORTED = 0xFF ///< No common voltage found + VOLT_INITIAL, ///< Initial value for VDDIO + VOLT1_5, ///< 1.5 Volt + VOLT1_35, ///< 1.35 Volt + VOLT1_25, ///< 1.25 Volt + VOLT_DDR4_RANGE_START, ///< Start of DDR4 Voltage Range + VOLT1_2 = VOLT_DDR4_RANGE_START, ///< 1.2 Volt + VOLT_TBD1, ///< TBD1 Voltage + VOLT_TBD2, ///< TBD2 Voltage + VOLT_UNSUPPORTED = 0xFF ///< No common voltage found } DIMM_VOLTAGE; /// AMP voltage support @@ -1369,19 +1374,11 @@ typedef enum { /// /// SPD Data for each DIMM. /// -typedef struct _SPD_DEF_STRUCT_DX { - IN BOOLEAN SpdValid; ///< Indicates that the SPD is valid - IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT32 Adderess; ///< SMBus Address - IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM -} SPD_DEF_STRUCT_DX; - -//----------------------------------------------------------------------------- -/// -/// SPD Data for each DIMM. -/// typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid + IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to + ///< 0 = Lower Page + ///< 1 = Upper Page (DDR4 Only) IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; @@ -1566,11 +1563,8 @@ typedef struct _CH_DEF_STRUCT { OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved - - OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. - + OUT UINT8 DimmThermSensorPresent; ///< For each bit n 0..3, 1 = DIMM n has an On Dimm Thermal Sensor where 4..7 are reserved OUT UINT8 MaxVref; ///< Maximum Vref Value for channel - OUT UINT8 Reserved[100]; ///< Reserved } CH_DEF_STRUCT; @@ -1604,6 +1598,9 @@ typedef struct _CH_TIMING_STRUCT { OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs + OUT UINT16 DIMMTrrdL; ///< Minimax TrrdL*40 (ns) of DIMMs + OUT UINT16 DIMMTwtrL; ///< Minimax TtwrL*40 (ns) of DIMMs + OUT UINT16 DIMMTccdL; ///< Minimax TccdL*40 (ns) of DIMMs OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz OUT UINT16 Speed; ///< DRAM bus speed in MHz ///< 400 (MHz) @@ -1622,10 +1619,14 @@ typedef struct _CH_TIMING_STRUCT { OUT UINT8 Trrd; ///< DCT Trrd (busclocks) OUT UINT8 Twtr; ///< DCT Twtr (busclocks) OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) + OUT UINT8 TrrdL; ///< DCT TrrdL (busclocks) + OUT UINT8 TwtrL; ///< DCT TwtrL (busclocks) + OUT UINT8 TccdL; ///< DCT TccdL (busclocks) OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns) OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns) OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns) OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns) + OUT UINT16 Trfc4; ///< DCT Trfc4min All DIMMS (in ns) - DDR4 Only OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. ///< OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) @@ -1788,7 +1789,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< OUT UINT32 SysLimit; ///< Limit[47:16] (system address). ///< - OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. + OUT DIMM_VOLTAGE DDRVoltage; ///< Find support voltage and send back to platform BIOS for DDR3 or DDR4. ///< OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and @@ -1892,7 +1893,15 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< - TRUE =enable ///< ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} - // Extended temperature range + + // Temperature Controlled Refresh + + IN BOOLEAN DramTempControlledRefreshEn; ///< Enable Temperature Controlled Refresh + ///< - FALSE = Disable + ///< - TRUE = Enable (Default) + ///< @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} + ///< If EnableExtendedTemperatureRange is enabled with this feature + ///< then CfgDramDoubleRefreshrate must also be enabled. // Online Spare @@ -2072,13 +2081,12 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< TRUE = Enable, platfrom BIOS requests support for DDR4 ///< FALSE = Disable, platform BIOS requests no DDR4 support ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} - IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable + IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable ///< TRUE = Enable, platfrom BIOS requests support for DDR3 ///< FALSE = Disable, platform BIOS requests no DDR3 support ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} IN UINT16 CustomVddioSupport; ///< CustomVddioSupport ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} - } MEM_PARAMETER_STRUCT; @@ -2198,6 +2206,8 @@ typedef union { ///< cannot be applied to current configurations. #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match #define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue +#define MEM_ALERT_DRAM_DOUBLE_REFRESH_RATE_ENABLED 0x04010300ul ///< CfgDramDoubleRefreshRate has been enabled due + /// to Extended Temperature Range feature // AGESA_ERROR Memory Errors #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS @@ -2249,6 +2259,8 @@ typedef union { #define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found #define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found #define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found +#define MEM_ERROR_CAD_BUS_TMG_NOT_FOUND 0x040E3500ul ///< No CAD Bus Timing Entries found +#define MEM_ERROR_DATA_BUS_CFG_NOT_FOUND 0x040F3500ul ///< No Data Bus Config Entries found #define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window #define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height #define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error @@ -2306,7 +2318,7 @@ typedef union { // AGESA_CRITICAL Memory Errors #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3 -#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2 +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR4 0x040A1F00ul ///< Heap allocation error for DMI table for DDR4 #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported #define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info @@ -2886,6 +2898,7 @@ typedef struct { IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range + IN BOOLEAN CfgDramTempControlledRefreshEn; ///< Temperature Controlled Refresh Rate - @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} IN UINT32 CfgPowerDownMode; ///< Power Down Mode. IN BOOLEAN CfgOnlineSpare; ///< Online Spare. IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. @@ -2938,7 +2951,7 @@ typedef struct { IN UINT8 CfgAbmSupport; ///< Abm Support IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control - IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. + IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID @@ -2985,6 +2998,10 @@ typedef struct { ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING} IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable ///< when it is mixed with other technology types. + IN BOOLEAN CfgDimmTypeDdr4Capable; ///< Select DDR4 as technology type that AGESA will enable + ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} + IN BOOLEAN CfgDimmTypeDdr3Capable; ///< Select DDR3 as technology type that AGESA will enable + ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE} IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured) @@ -3141,6 +3158,10 @@ typedef struct { OUT UINT16 T4ProcFamily2; ///< Family 2 OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer + OUT UINT16 T4CoreCount2; ///< Core count 2 + OUT UINT16 T4CoreEnabled2; ///< Core Enable 2 + OUT UINT16 T4ThreadCount2; ///< Thread count 2 + } TYPE4_DMI_INFO; /// DMI Type 7 - Cache information @@ -3250,7 +3271,12 @@ typedef enum { Ddr2MemType, ///< Assign 19 to DDR2 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM Ddr3MemType = 0x18, ///< Assign 24 to DDR3 - Fbd2MemType ///< Assign 25 to FBD2 + Fbd2MemType, ///< Assign 25 to FBD2 + Ddr4MemType, ///< Assign 26 to DDR4 + LpDdrMemType, ///< Assign 27 to LPDDR + LpDdr2MemType, ///< Assign 28 to LPDDR2 + LpDdr3MemType, ///< Assign 29 to LPDDR3 + LpDdr4MemType, ///< Assign 30 to LPDDR4 } DMI_T17_MEMORY_TYPE; /// DMI Type 17 offset 13h - Type Detail @@ -3270,7 +3296,7 @@ typedef struct { OUT UINT16 NonVolatile:1; ///< Non-volatile OUT UINT16 Registered:1; ///< Registered (Buffered) OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) - OUT UINT16 Reserved2:1; ///< Reserved + OUT UINT16 LRDIMM:1; ///< LRDIMM } DMI_T17_TYPE_DETAIL; /// DMI Type 17 - Memory Device diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h index c4be628..62ef892 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h @@ -69,7 +69,11 @@ // Family 15h equates #define AMD_FAMILY_15_CZ 0x0004u #define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ) -#define AMD_FAMILY_15 AMD_FAMILY_15_CZ + +#define AMD_FAMILY_15_ST 0x0008u +#define AMD_FAMILY_ST (AMD_FAMILY_15_ST) + +#define AMD_FAMILY_15 (AMD_FAMILY_15_CZ | AMD_FAMILY_ST) // Family Unknown #define AMD_FAMILY_UNKNOWN 0x8000u @@ -81,12 +85,23 @@ // Family 15h CZ steppings #define AMD_F15_CZ_A0 0x0001u #define AMD_F15_CZ_A1 0x0002u +#define AMD_F15_BR_A1 0x0004u + // Family 15h ST steppings +#define AMD_F15_ST_A0 0x0010u // Family 15h Unknown stepping #define AMD_F15_UNKNOWN 0x8000u -#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1) -#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax) + // CZ and BR +#define AMD_F15_BR_Ax (AMD_F15_BR_A1) +#define AMD_F15_BR_ALL (AMD_F15_BR_Ax) + +#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1 | AMD_F15_BR_Ax) +#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax | AMD_F15_BR_ALL) + + // ST +#define AMD_F15_ST_Ax (AMD_F15_ST_A0) +#define AMD_F15_ST_ALL (AMD_F15_ST_Ax) -#define AMD_F15_ALL AMD_F15_CZ_ALL +#define AMD_F15_ALL (AMD_F15_CZ_ALL | AMD_F15_ST_ALL) #endif // _CPU_FAM_REGISTERS_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index e51a01f..889be76 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -429,14 +429,14 @@ typedef struct { #define CPUID_EXT_FAMILY_MASK 0x0FF00000ul #define CZ_SOCKET_FP4 0 +#define ST_SOCKET_FP4 0 +#define ST_SOCKET_FT4 3 #define SOCKET_IGNORE 0xF #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull #define APIC_EXT_BRDCST_MASK 0x000E0000ul #define APIC_ENABLE_BIT 0x00000800ul -#ifndef LOCAL_APIC_ADDR #define LOCAL_APIC_ADDR 0xFEE00000ul -#endif #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h index fb2bae2..35a76d2 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -986,6 +986,7 @@ typedef struct { VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings + BOOLEAN NoClearThermalTripSts; /// Skip clearing ThermalTrip status } FCH_ACPI; diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index c18e191..6108274 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -68,6 +68,11 @@ #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR #define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset +#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port +#define PMIO_DATA_PORT 0xCD7 ///Pmio data port + +#define PMIO_REG62 0x62 ///PMIOx62 + //====================================================================================== // // Define Mailbox Status field @@ -162,7 +167,7 @@ GetPspMboxStatus ( BOOLEAN -PspBarInitEarly (void); +PspBarInitEarly (VOID); VOID PspLibPciIndirectRead ( @@ -184,4 +189,8 @@ UINT8 PspLibAccessWidth ( IN ACCESS_WIDTH AccessWidth ); + +BOOLEAN +IsS3Resume (VOID); + #endif // _AMD_LIB_H_

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New patch to review for coreboot: AMD ROMSIG: Only check location if ROMSIG is used
by Martin Roth 11 Aug '15

11 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11161 -gerrit commit c9db804ca8f3137dec891b5793a277a77a132dfc Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 11 09:05:42 2015 -0600 AMD ROMSIG: Only check location if ROMSIG is used The location of the AMD ROMSIG binary was being checked and warnings were being printed even when the ROMSIG file wasn't being used. These false warnings are avoided by moving the warnings into the block where the CBFS file for the ROMSIG is generated. Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 13 ++++++------- src/southbridge/amd/pi/hudson/Makefile.inc | 12 ++++++------ 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index d6283c3..9e42cf2 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -39,13 +39,6 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif - #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) @@ -88,6 +81,12 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM done > $@ ifeq ($(CONFIG_HUDSON_FWM), y) +ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) +endif +ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) +endif cbfs-files-y += hudson/fwm hudson/fwm-file := $(obj)/coreboot_hudson_romsig.bin hudson/fwm-position := $(HUDSON_FWM_POSITION) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 73b15f9..5369823 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -66,12 +66,6 @@ HUDSON_FWM_POS_CALC=$(call int-add, $(call int-subtract, 0xffffffff $(call int-m HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) HUDSON_FWM_INSIDE_CBFS=$(call int-lt, $(CBFS_BASE_ADDRESS) $(HUDSON_FWM_POSITION)) -ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) -endif -ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) -$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) -endif CBFS_HEADER_SIZE=0x60 #assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes. @@ -146,6 +140,12 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM rm $@.tmp ifeq ($(CONFIG_HUDSON_FWM), y) +ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) +endif +ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) +endif cbfs-files-y += fch/fwm fch/fwm-file := $(obj)/coreboot_hudson_romsig.bin fch/fwm-position := $(HUDSON_FWM_POSITION)

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coreboot-gerrit August 2015