coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: fsp1.1: stub out missing header just enough so it compiles
by Patrick Georgi 10 Aug '15

10 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11156 -gerrit commit 521d664c4185bdad54e1469dfab2a91bc9f30526 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Aug 10 22:05:09 2015 +0200 fsp1.1: stub out missing header just enough so it compiles Change-Id: Ie3d43e19803b26a26f118806f7e2a946c524926d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- src/drivers/intel/fsp1_1/Kconfig | 15 ++- src/soc/intel/braswell/Kconfig | 4 +- src/soc/intel/braswell/microcode/Makefile.inc | 2 +- src/soc/intel/braswell/microcode/microcode_blob.c | 2 + src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h | 153 ++++++++++++++++++++++ 5 files changed, 170 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 33283db..a938f83 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -43,8 +43,6 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot -if HAVE_FSP_BIN - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0 @@ -58,6 +56,8 @@ config CPU_MICROCODE_CBFS_LOC The location (base address) in CBFS that contains the microcode update binary. +if HAVE_FSP_BIN + config ENABLE_MRC_CACHE bool default y if HAVE_ACPI_RESUME @@ -140,6 +140,15 @@ config VIRTUAL_ROM_SIZE endif #HAVE_FSP_BIN +if !HAVE_FSP_BIN +config FSP_INCLUDE_PATH + string "Path for FSP specific include files" + default "src/vendorcode/intel/fsp/fsp1_1/stub" + help + The path and filename of the Intel FSP binary for this platform. + +endif #!HAVE_FSP_BIN + config CACHE_ROM_SIZE_OVERRIDE hex "Cache ROM Size" default CBFS_SIZE @@ -181,7 +190,7 @@ config FSP_USES_UPD config GOP_SUPPORT bool "Enable GOP support" - default y + default n config USE_GENERIC_FSP_CAR_INC bool diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4f7ed6a..4d743db 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -152,7 +152,7 @@ config ENABLE_BUILTIN_COM1 config HAVE_IFD_BIN bool - default y + default n config BUILD_WITH_FAKE_IFD bool "Build with a fake IFD" @@ -173,7 +173,7 @@ config BUILD_WITH_FAKE_IFD config HAVE_ME_BIN bool "Add Intel Management Engine firmware" - default y + default n help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..a5e8981 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,5 +1,5 @@ # Add CPU uCode source to list of files to build. -cpu_microcode-y += microcode_blob.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c # This section overrides the default build process for the microcode to place # it at a known location in the CBFS. This only needs to be enabled if FSP is diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c index e0aeaff..20268d4 100644 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -18,5 +18,7 @@ */ unsigned microcode[] = { +#if IS_ENABLED(CONFIG_HAVE_FSP_BIN) #include <microcode/microcode_blob.h> +#endif }; diff --git a/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h new file mode 100644 index 0000000..ce5a9a8 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/stub/FspUpdVpd.h @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* NOTE: These definitions probably don't match the FSP-side definitions, so + * the build result won't be usable even with the FSP binary added. + * They merely act as stub to make things compile. + */ + +typedef struct { + int PcdMemoryTypeEnable; + int PcdDvfsEnable; + int PcdMemorySpdPtr; + int PcdMemChannel0Config; + int PcdMemChannel1Config; + int PcdMrcInitTsegSize; + int PcdMrcInitSpdAddr1; + int PcdMrcInitSpdAddr2; + int PcdMrcInitMmioSize; + int PcdIgdDvmt50PreAlloc; + int PcdApertureSize; + int PcdGttSize; + int PcdLegacySegDecode; +} MEMORY_INIT_UPD; + +typedef struct { + int MemoryInitUpdOffset; + int SiliconInitUpdOffset; +} UPD_DATA_REGION; + +typedef struct { + int PcdUpdRegionOffset; +} VPD_DATA_REGION; + +typedef struct { + int DimmId; + int SizeInMb; +} DIMM_INFO; + +typedef struct { + int ChannelId; + int DimmCount; + DIMM_INFO DimmInfo[16]; +} CHANNEL_INFO; + +typedef struct { + int DataWidth; + int Revision; + int MemoryType; + int MemoryFrequencyInMHz; + int ErrorCorrectionType; + int ChannelCount; + CHANNEL_INFO ChannelInfo[16]; +} FSP_SMBIOS_MEMORY_INFO; + +typedef struct { + int ISPPciDevConfig; + int ISPEnable; + int PMIC_I2CBus; + int PcdRtcLock; + int PcdLogoSize; + int PcdLogoPtr; + int PcdPchSsicEnable; + int PcdPcieRootPortSpeed; + int PcdPchUsbHsicPort; + int PcdPchUsbSsicPort; + int PcdSataInterfaceSpeed; + int Usb0Lane0Ow2tapgen2deemph3p5; + int Usb0Lane1Ow2tapgen2deemph3p5; + int Usb0Lane2Ow2tapgen2deemph3p5; + int Usb0Lane3Ow2tapgen2deemph3p5; + int Usb1Lane0Ow2tapgen2deemph3p5; + int Usb1Lane1Ow2tapgen2deemph3p5; + int Usb1Lane2Ow2tapgen2deemph3p5; + int Usb1Lane3Ow2tapgen2deemph3p5; + int Usb2Lane0Ow2tapgen2deemph3p5; + int Usb2Lane1Ow2tapgen2deemph3p5; + int Usb2Lane2Ow2tapgen2deemph3p5; + int Usb2Lane3Ow2tapgen2deemph3p5; + int Usb3Lane0Ow2tapgen2deemph3p5; + int Usb3Lane1Ow2tapgen2deemph3p5; + int Usb3Lane2Ow2tapgen2deemph3p5; + int Usb3Lane3Ow2tapgen2deemph3p5; + int Usb2Port0PerPortPeTxiSet; + int Usb2Port0PerPortTxiSet; + int Usb2Port0IUsbTxEmphasisEn; + int Usb2Port0PerPortTxPeHalf; + int Usb2Port1PerPortPeTxiSet; + int Usb2Port1PerPortTxiSet; + int Usb2Port1IUsbTxEmphasisEn; + int Usb2Port1PerPortTxPeHalf; + int Usb2Port2PerPortPeTxiSet; + int Usb2Port2PerPortTxiSet; + int Usb2Port2IUsbTxEmphasisEn; + int Usb2Port2PerPortTxPeHalf; + int Usb2Port3PerPortPeTxiSet; + int Usb2Port3PerPortTxiSet; + int Usb2Port3IUsbTxEmphasisEn; + int Usb2Port3PerPortTxPeHalf; + int Usb2Port4PerPortPeTxiSet; + int Usb2Port4PerPortTxiSet; + int Usb2Port4IUsbTxEmphasisEn; + int Usb2Port4PerPortTxPeHalf; + int PcdSataClkSsc; + int PcdDispClkSsc; + int PcdUsb3ClkSsc; + int PcdEmmcMode; + int DptfDisable; + int ChvSvidConfig; + int PunitPwrConfigDisable; + int GpioPadInitTablePtr; + int GpioFamilyInitTablePtr; + int PcdGraphicsConfigPtr; + int PcdEnableI2C0; + int PcdEnableI2C1; + int PcdEnableI2C2; + int PcdEnableI2C3; + int PcdEnableI2C4; + int PcdEnableI2C5; + int PcdEnableI2C6; + int PcdEnableDma0; + int PcdEnableDma1; + int PcdEnableLpe; + int PcdEnableXhci; + int PcdEnableSata; + int AzaliaConfigPtr; + int AzaliaVerbTablePtr; + int PcdEnableAzalia; + int PcdEnableHsuart0; + int PcdEnableHsuart1; + int PcdSdcardMode; + +} SILICON_INIT_UPD; + +enum { + MEM_LPDDR3, + MEM_DDR3, +};

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Patch merged into coreboot/master: what-jenkins-does: Add building chromeos configurations
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit 1c487048a796ae8b5c45b0ee2a3e4aa8d63dabe8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:40:05 2015 +0200 what-jenkins-does: Add building chromeos configurations This prevents us from inadvertedly breaking Chrome OS' configurations. They're built in addition to the normal configurations for each boards, to accomodate all use cases on these devices. Change-Id: I772a47dca8815f47c12f6fd4405ae28c7c997aa8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11104 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11104 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Kconfig include in lpgcc
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit f1b7afb4a4b5a7afedfef1f03e28a1298874f553 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 10 11:00:39 2015 +0200 libpayload: Kconfig include in lpgcc Payloads will include headers from libpayload, which depend on kconfig.h, so it has to be included in the command line produced by lpgcc. Change-Id: I3b55928babba2896a112f8c5fae46365cf71d308 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11114 for details. -gerrit

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Patch merged into coreboot/master: xcompile: crossgcc lookup in parent paths, for painless libpayload support
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit 15dd6c2fa3b0953248a6a22b1b4b68c27b4c9c63 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 16:46:29 2015 +0200 xcompile: crossgcc lookup in parent paths, for painless libpayload support libpayload is calling the xcompile script from payloads/libpayload, so the script never finds the path on its own and has to be fed the right XGCCPATH by hand. This makes xcompile look for the parent path too, so that it can find the crossgcc toolchains when called from libpayload. Change-Id: Icc41bb68e3a43810f40f03ab1eb08af07a50a3de Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11119 for details. -gerrit

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Patch set updated for coreboot: what-jenkins-does: Add building chromeos configurations
by Patrick Georgi 10 Aug '15

10 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11104 -gerrit commit 349ace80258adb69ac7a7f1367d07910890f6105 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:40:05 2015 +0200 what-jenkins-does: Add building chromeos configurations This prevents us from inadvertedly breaking Chrome OS' configurations. They're built in addition to the normal configurations for each boards, to accomodate all use cases on these devices. Change-Id: I772a47dca8815f47c12f6fd4405ae28c7c997aa8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 144bee6..1f74bbe 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -672,6 +672,8 @@ $(obj)/board_id: JENKINS_PAYLOAD?=none CPUS?=4 what-jenkins-does: + util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x + -mv abuild.xml abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(MAKE) V=$(V) Q=$(Q) -C util/cbmem junit.xml

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Patch merged into coreboot/master: chromeos: vboot: Adaptations for using a separate object out directory
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit 6a106943d020015fdeccb7a40a1e1f3e04ef9369 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 23:03:27 2015 +0200 chromeos: vboot: Adaptations for using a separate object out directory $(obj) might be defined either as a relative or an absolute path. Thus, it has to be filtered out before adding $(top) to it (in case of an absolute path) when building vboot. It is then provided separately in CFLAGS (as an absolute path). In addition, VB2_LIB inherits $(obj), so it might also already be an absolute path, and prefixing $(top) to it doesn't apply. Thus, the absolute path to it should be passed to the vboot make command. Change-Id: I13e893ebdf22c4513ee40d9331a30ac7de8f9788 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11120 for details. -gerrit

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Patch merged into coreboot/master: Makefile.inc: use correct make
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit d09b32b668f0f131144710f561d36eef72cb5625 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 10 12:15:40 2015 -0500 Makefile.inc: use correct make Change-Id: I4ff1da3fcb787d72ba58b976f73a57ccc0e1c260 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/11155 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11155 for details. -gerrit

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New patch to review for coreboot: Makefile.inc: use correct make
by Jonathan A. Kollasch 10 Aug '15

10 Aug '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11155 -gerrit commit 975873df2d680328a8b24a713cecf70fd9ba45f6 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 10 12:15:40 2015 -0500 Makefile.inc: use correct make Change-Id: I4ff1da3fcb787d72ba58b976f73a57ccc0e1c260 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 65d308d..144bee6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -628,7 +628,7 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp && \ - make DOTCONFIG=$(DOTCONFIG) DEFCONFIG=$(obj)/config.tmp savedefconfig && \ + $(MAKE) DOTCONFIG=$(DOTCONFIG) DEFCONFIG=$(obj)/config.tmp savedefconfig && \ $(CBFSTOOL) $@.tmp add -f $(obj)/config.tmp -n config -t raw; rm -f $(obj)/config.tmp ; fi @printf " REVISION build.h\n" if [ -f $(obj)/build.h ]; then $(CBFSTOOL) $@.tmp add -f $(obj)/build.h -n revision -t raw; fi

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Patch set updated for coreboot: what-jenkins-does: Add building chromeos configurations
by Patrick Georgi 10 Aug '15

10 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11104 -gerrit commit 8ae7851b2616683ed7e7fca6fcf07122f494a0bb Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:40:05 2015 +0200 what-jenkins-does: Add building chromeos configurations This prevents us from inadvertedly breaking Chrome OS' configurations. They're built in addition to the normal configurations for each boards, to accomodate all use cases on these devices. Change-Id: I772a47dca8815f47c12f6fd4405ae28c7c997aa8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 65d308d..c6c56d2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -672,6 +672,8 @@ $(obj)/board_id: JENKINS_PAYLOAD?=none CPUS?=4 what-jenkins-does: + util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x + -mv abuild.xml abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(MAKE) V=$(V) Q=$(Q) -C util/cbmem junit.xml

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Patch merged into coreboot/master: google/stout: Fix ELOG related ifdefs
by gerrit＠coreboot.org 10 Aug '15

10 Aug '15

the following patch was just integrated into master: commit 7605a5ac575d80ef68f06f7a7f59522c865a4b36 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 17:18:16 2015 +0200 google/stout: Fix ELOG related ifdefs The used functions require the ELOG_GSMI feature, not just ELOG. Change-Id: If38cf0b710d9236012bfb1f0b119c10f9e533a25 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11098 for details. -gerrit

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coreboot-gerrit August 2015