Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11151
-gerrit
commit 4ca029cf601fb155f64a833a567218e4682a4312
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Mon Aug 10 10:21:14 2015 +0200
board_status: use command -v over which(1)
The script is pretty linux specific as-is, but more portability won't hurt.
Change-Id: I33e18606bea4e23043d748e3fe66a345e720d389
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/board_status/board_status.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh
index ec98277..14d6514 100755
--- a/util/board_status/board_status.sh
+++ b/util/board_status/board_status.sh
@@ -38,10 +38,10 @@ test_cmd()
fi
if [ "$1" -eq "$REMOTE" ] && [ -n "$REMOTE_HOST" ]; then
- ssh root@${REMOTE_HOST} which "$2" > /dev/null
+ ssh root@${REMOTE_HOST} command -v "$2" > /dev/null
rc=$?
else
- which "$2" >/dev/null
+ command -v "$2" >/dev/null
rc=$?
fi
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11150
-gerrit
commit 6f635c880cf8eb3b6afce3a7404d1b3317439e67
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Mon Aug 10 10:21:51 2015 +0200
board_status: create temporary directory in coreboot tree
Otherwise there may be a filesystem boundary that breaks make oldconfig.
Change-Id: I1eb55bcabc3e1b834d54f3da9fadfc352f0c4a65
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/board_status/board_status.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh
index 5bcbd04..0f5627d 100755
--- a/util/board_status/board_status.sh
+++ b/util/board_status/board_status.sh
@@ -211,7 +211,7 @@ fi
# Results will be placed in a temporary location until we're ready to upload.
# If the user does not wish to upload, results will remain in /tmp.
-tmpdir=$(mktemp -d --tmpdir coreboot_board_status.XXXXXXXX)
+tmpdir=$(mktemp -d coreboot_board_status.XXXXXXXX)
cbfstool_cmd="build/cbfstool"
if test ! -x build/cbfstool; then
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11138
-gerrit
commit f4e45f65ebd8fa15d54fbe48634ce0ac267c8dba
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 21:35:38 2015 +0200
seabios integration: fix interaction with ccache
SeaBIOS' build system doesn't like CC to be a compound command like
"ccache gcc", so we strip things. Unfortunately with CCACHE enabled,
we passed /usr/bin/ccache (or wherever it was found on the PATH).
Instead use the second term in CCACHE mode.
Change-Id: I905fcdc73d067e553e923e307fafceaacdefdc6c
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
payloads/external/Makefile.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 165670d..ad1a3ef 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -32,10 +32,11 @@ ifeq ($(CONFIG_PAYLOAD_GRUB2),y)
COREBOOT_ROM_DEPENDENCIES+=grub2
endif
+SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1)
seabios:
$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
- CC=$(word 1,$(CC_x86_32)) CFLAGS="$(patsubst $(word 1,$(CC_x86_32))%,,$(CC_x86_32))" \
+ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) CFLAGS="$(patsubst $(word $(SEABIOS_CC_OFFSET),$(CC_x86_32))%,,$(CC_x86_32))" \
LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \
OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11139
-gerrit
commit f963766609c6c7c2f77d0058dd42728cc22723b1
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 22:02:12 2015 +0200
intel/i945: don't read structs out of uninitialized pointers
Change-Id: I7f17cd1418f05ff3e8cd559eca6ec3ce7f9bfb79
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/northbridge/intel/i945/gma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a2e5163..437b6ce 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -496,6 +496,9 @@ intel_gma_get_controller_info(void)
return NULL;
}
struct northbridge_intel_i945_config *chip = dev->chip_info;
+ if (!chip) {
+ return NULL;
+ }
return &chip->gfx;
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11137
-gerrit
commit cbc11a0e5662374047a4825ebc75e905b6f480be
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 11:52:06 2015 +0200
libpayload: Fix compile error in time.c if nvram support is disabled
rdtsc() is only used for nvram access.
Change-Id: I896116d6a5782e5e50aa3acfbe1831b080f55d34
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
payloads/libpayload/libc/time.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
index 4109eab..4ed788f 100644
--- a/payloads/libpayload/libc/time.c
+++ b/payloads/libpayload/libc/time.c
@@ -34,7 +34,7 @@
#include <libpayload-config.h>
#include <libpayload.h>
-#if IS_ENABLED(CONFIG_LP_ARCH_X86)
+#if IS_ENABLED(CONFIG_LP_ARCH_X86) && IS_ENABLED(CONFIG_LP_NVRAM)
#include <arch/rdtsc.h>
#endif
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10525
-gerrit
commit b9215ed95a2783f5b4287507a38f8af46e2b858e
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Jun 12 11:35:10 2015 +0200
board-status: expand minimized config to full size
Otherwise the later processing may fail. Keep minimized version as
config.short.txt for the user's benefit.
Change-Id: I1082ff68de85027d526266cdbf2073d22ce7f2e0
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/board_status/board_status.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh
index 0f5627d..ec98277 100755
--- a/util/board_status/board_status.sh
+++ b/util/board_status/board_status.sh
@@ -219,6 +219,8 @@ if test ! -x build/cbfstool; then
fi
test_cmd $LOCAL "$cbfstool_cmd"
$cbfstool_cmd build/coreboot.rom extract -n config -f ${tmpdir}/config.txt
+cp ${tmpdir}/config.txt ${tmpdir}/config.short.txt
+yes "" | make DOTCONFIG=${tmpdir}/config.txt oldconfig
$cbfstool_cmd build/coreboot.rom print > ${tmpdir}/cbfs.txt
# Obtain board and revision info to form the directory structure:
@@ -238,6 +240,7 @@ echo "Temporarily placing output in ${tmpdir}/${results}"
mkdir -p "${tmpdir}/${results}"
mv "${tmpdir}/config.txt" "${tmpdir}/${results}"
+mv "${tmpdir}/config.short.txt" "${tmpdir}/${results}"
mv "${tmpdir}/cbfs.txt" "${tmpdir}/${results}"
touch ${tmpdir}/${results}/revision.txt
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11140
-gerrit
commit 91e133be2779ac6b3bbbd860601d9c6495af789c
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 22:07:10 2015 +0200
getac/p470: enable GPU devices in devicetree
This enables adding the GPU specific entries to the SSDT.
Change-Id: I04d0eb7bf6f3e28d89c9318b777875e8a78b1ab5
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/mainboard/getac/p470/devicetree.cb | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index cbf7651..edf165e 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -31,10 +31,9 @@ chip northbridge/intel/i945
device domain 0 on
device pci 00.0 on end # host bridge
- # autodetect:
- #device pci 01.0 off end # i945 PCIe root port
- #device pci 02.0 on end # vga controller
- #device pci 02.1 on end # display controller
+ device pci 01.0 off end # i945 PCIe root port
+ device pci 02.0 on end # vga controller
+ device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0a"