coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 99e0b27 smmrelocate: Remove dead TSEG code.
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 99e0b27189adcb9c32d3b3ce115546e311c6ea77 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 29 07:44:03 2015 +0200 smmrelocate: Remove dead TSEG code. Change-Id: I786dd8295d310bfd21db49cfbe5ea39675b25b68 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10361 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10361 for details. -gerrit

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Patch merged into coreboot/master: f119f08 i82801gx: Reserve LPC decodes.
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit f119f0895cb11be9f546321a7028d048a353c8bf Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Nov 24 21:05:56 2014 +0100 i82801gx: Reserve LPC decodes. This change makes sure that LPC controller declares resources that it actually decodes. bd82x6x already does it but i82801gx doesn't leading to allocator potentially allocating something else to the same range. Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7662 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/7662 for details. -gerrit

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Patch set updated for coreboot: 93654e8 i82801gx: Reserve LPC decodes.
by Vladimir Serbinenko 29 May '15

29 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7662 -gerrit commit 93654e80c9c2e2a73a77d6b5cc0ce60d50a82d65 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Nov 24 21:05:56 2014 +0100 i82801gx: Reserve LPC decodes. This change makes sure that LPC controller declares resources that it actually decodes. bd82x6x already does it but i82801gx doesn't leading to allocator potentially allocating something else to the same range. Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801gx/lpc.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9dbb3ec..6466038 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -579,18 +579,20 @@ void acpi_fill_fadt(acpi_fadt_t * fadt) static void i82801gx_lpc_read_resources(device_t dev) { struct resource *res; + u8 io_index = 0; + int i; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | @@ -600,6 +602,20 @@ static void i82801gx_lpc_read_resources(device_t dev) res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Set IO decode ranges if required.*/ + for (i = 0; i < 4; i++) { + u32 gen_dec; + gen_dec = pci_read_config32(dev, 0x84 + 4 * i); + + if ((gen_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = gen_dec & 0xFFFC; + res->size = (gen_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + } } static void set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch merged into coreboot/master: 7ef3d90 x230: Clean up smihandler.c
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 7ef3d903ab1496d01a3396804ae26d36f3ad21ab Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 11:25:50 2015 +0200 x230: Clean up smihandler.c Remove dead code and dead includes. Change-Id: I5564ebfbbef6f65c275c2f94f75724f4e36472db Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10349 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10349 for details. -gerrit

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Patch set updated for coreboot: 7b5305a x230: Clean up smihandler.c
by Vladimir Serbinenko 29 May '15

29 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10349 -gerrit commit 7b5305ad1fc58a4b164bb986f0fe8a0a39685e13 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 11:25:50 2015 +0200 x230: Clean up smihandler.c Remove dead code and dead includes. Change-Id: I5564ebfbbef6f65c275c2f94f75724f4e36472db Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/smihandler.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 7e518ab..f0ef637 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -23,14 +23,8 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> -#include <delay.h> -#include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/me.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 @@ -51,14 +45,7 @@ int mainboard_io_trap_handler(int smif) smm_initialized = 1; } - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; + return 0; } static void mainboard_smi_handle_ec_sci(void)

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Patch merged into coreboot/master: 852014c lenovo: Move pc_keyboard_init to h8 init.
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 852014cf003efa142e1992b45b2a4a627426a5df Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 08:30:47 2015 +0200 lenovo: Move pc_keyboard_init to h8 init. PS/2 emulation is part of H8, so should be inited in relevant files. Change-Id: Ie873ea7f6f88f68f622351799462d0b000d17585 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See http://review.coreboot.org/10348 for details. -gerrit

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Patch merged into coreboot/master: faa46e0 nvs: Add missing stdint.h include.
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit faa46e0cb697371535fef1b806101f1fd57c354e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 09:57:43 2015 +0200 nvs: Add missing stdint.h include. nvs.h uses u8 without including stdint.h. Change-Id: I4ffcbb850cb7b8f47126ee1906b9e0960dd449e8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10331 for details. -gerrit

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Patch merged into coreboot/master: 38a6062 h8: Add missing include of stdint.h
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 38a6062c3550f0efefb98d2a83c9027270f55c94 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 09:57:35 2015 +0200 h8: Add missing include of stdint.h h8.h uses u8 without including stdint.h. Change-Id: I7e46f6b8ca92ed23af93597fe2f08add464eb176 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10330 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10330 for details. -gerrit

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New patch to review for coreboot: fd06848 smmrelocate: Remove dead TSEG code.
by Vladimir Serbinenko 29 May '15

29 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10361 -gerrit commit fd06848b827ae25c1a903fb642b99d66ac8f58b9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 29 07:44:03 2015 +0200 smmrelocate: Remove dead TSEG code. Change-Id: I786dd8295d310bfd21db49cfbe5ea39675b25b68 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/smm/smmrelocate.S | 43 ------------------------------------------- 1 file changed, 43 deletions(-) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index ec489ce..2283e7b 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -139,54 +139,11 @@ smm_relocate: movl %ecx, %edx shl $10, %edx -#if CONFIG_SMM_TSEG - movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ - andl $~1, %eax /* Remove lock bit */ -#else movl $0xa0000, %eax -#endif subl %edx, %eax /* subtract offset, see above */ addr32 movl %eax, (%ebx) -#if CONFIG_SMM_TSEG - /* Check for SMRR capability in MTRRCAP[11] */ - movl $MTRRcap_MSR, %ecx - rdmsr - bt $11, %eax - jnc skip_smrr - - /* TSEG base */ - movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ - addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ - andl $~1, %eax /* Remove lock bit */ - movl %eax, %ebx - - /* Set SMRR base address. */ - movl $SMRRphysBase_MSR, %ecx - orl $MTRR_TYPE_WRBACK, %eax - xorl %edx, %edx - wrmsr - - /* Set SMRR mask. */ - movl $SMRRphysMask_MSR, %ecx - movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax - xorl %edx, %edx - wrmsr - -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE - /* - * IED base is top 4M of TSEG - */ - addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx - movl $(0x30000 + 0x8000 + 0x7eec), %eax - addr32 movl %ebx, (%eax) -#endif - -skip_smrr: -#endif - /* The next section of code is potentially southbridge specific */ /* Clear SMI status */

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Patch merged into coreboot/master: 41652a9 Remove leftover smi_get_tseg_base
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 41652a9bad054041de2bb9b805d21493e6a3a70f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:15:14 2015 +0200 Remove leftover smi_get_tseg_base Change-Id: I8e694f37c8709efd702208aa005096ebf1f3abb5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10356 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10356 for details. -gerrit

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coreboot-gerrit May 2015