coreboot-gerrit May 2015

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New patch to review for coreboot: 45983d1 ACPI: Hide acpi_slp_type
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10360 -gerrit commit 45983d13bd55e4ec92ff1ad90ec26879ee1a1be8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:17:23 2015 +0300 ACPI: Hide acpi_slp_type Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index a7a638f..94845e9 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -919,7 +919,7 @@ void acpi_resume(void *wake_vec) } /* This is filled with acpi_is_wakeup() call early in ramstage. */ -int acpi_slp_type = -1; +static int acpi_slp_type = -1; #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) int acpi_get_sleep_type(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 10db820..3e81131 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -578,7 +578,6 @@ static inline int acpi_s3_resume_allowed(void) } #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -extern int acpi_slp_type; #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) @@ -591,7 +590,6 @@ int acpi_is_wakeup_s3(void); #endif #else -#define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } #endif

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Patch set updated for coreboot: 71e1965 intel: Fix S3 handoff state to ramstage
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 71e196515d627dd32be29581b0ffe270238a05c1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Fix S3 handoff state to ramstage TODO: missing romstage find_or_add_romstage_handoff() Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before use. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t60/mainboard.c | 7 +++---- src/mainboard/lenovo/x200/romstage.c | 18 +++++++++--------- src/mainboard/lenovo/x201/mainboard.c | 5 ++--- src/mainboard/lenovo/x201/romstage.c | 12 +++++++----- src/mainboard/lenovo/x60/mainboard.c | 7 +++---- src/mainboard/packardbell/ms2290/romstage.c | 11 ++++++----- src/mainboard/roda/rk9/romstage.c | 20 ++++++++++---------- src/northbridge/intel/gm45/northbridge.c | 17 ----------------- src/northbridge/intel/i945/early_init.c | 20 ++++++++++++++------ src/northbridge/intel/i945/northbridge.c | 23 ----------------------- src/northbridge/intel/nehalem/nehalem.h | 4 ---- src/northbridge/intel/nehalem/northbridge.c | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 4 ---- src/northbridge/intel/sandybridge/northbridge.c | 21 --------------------- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- src/southbridge/intel/i82801gx/smi.c | 13 ++----------- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801ix/smi.c | 13 ++----------- 18 files changed, 58 insertions(+), 164 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 428e18a..170656b 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -21,12 +21,12 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> @@ -53,13 +53,12 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + device_t idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index a739d18..1f5a211 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -177,11 +177,17 @@ void main(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME + + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -191,14 +197,8 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } -#endif + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 85c27b2..ae5d56d 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> @@ -98,7 +99,6 @@ static void fill_ssdt(void) static void mainboard_enable(device_t dev) { - device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; @@ -118,8 +118,7 @@ static void mainboard_enable(device_t dev) 0x10); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1e335d3..d335c31 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -184,6 +184,7 @@ void main(unsigned long bist) u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; + struct romstage_handoff *handoff; timestamp_init(timestamp_get()); @@ -281,7 +282,12 @@ void main(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } -#if CONFIG_HAVE_ACPI_RESUME + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ @@ -299,13 +305,9 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } -#endif #if CONFIG_LPC_TPM init_tpm(s3resume); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index fbab0f1..5a93e53 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -21,13 +21,13 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -56,7 +56,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { - device_t dev0, idedev, sdhci_dev; + device_t idedev, sdhci_dev; ec_clr_bit(0x03, 2); @@ -68,8 +68,7 @@ static void mainboard_init(device_t dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 82bacfe..724b36b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,12 @@ void main(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } -#if CONFIG_HAVE_ACPI_RESUME + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ @@ -290,13 +295,9 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } -#endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 889b940..e27d2f2 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -190,12 +190,18 @@ void main(unsigned long bist) init_iommu(); - cbmem_initted = !cbmem_recovery(0); -#if CONFIG_HAVE_ACPI_RESUME + cbmem_initted = !cbmem_recovery(s3_resume); + + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -205,13 +211,7 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } -#endif + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 9372e26..c8fa324 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,11 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; - static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 3b86a9c..452c41c 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -195,7 +195,6 @@ static void i945_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ @@ -896,13 +895,25 @@ void i945_early_initialization(void) static void i945_prepare_resume(int s3resume) { int cbmem_was_initted; + struct romstage_handoff *handoff; cbmem_was_initted = !cbmem_recovery(s3resume); + if (s3_resume && !acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + s3_resume = 0; + } + + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3_resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_was_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption @@ -913,11 +924,8 @@ static void i945_prepare_resume(int s3resume) if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); } + } void i945_late_initialization(int s3resume) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 067285b..a4668b4 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,26 +232,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) -{ - switch (pci_read_config32(dev, SKPAD)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -} -#endif - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -261,9 +241,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 87f622d..cacc4e9 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -226,10 +226,6 @@ enum { #define D0F0_TOLUD 0xb0 #define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #define D0F0_CAPID0 0xe0 #define TSEG 0xac /* TSEG base */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 43bd846..dfa44d7 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,26 +283,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -312,7 +292,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 21ef223..433e2d4 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -195,10 +195,6 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7d257f6..f53615c 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,26 +412,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -441,7 +421,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index bbadde7..084fbc9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -386,7 +386,5 @@ int southbridge_detect_s3_resume(void); #define SS_CNT 0x50 #define C3_RES 0x54 -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index bd598fd..1ebabc1 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -319,16 +320,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -342,7 +333,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index adf81cc..892e884 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -222,10 +222,6 @@ #define FD_SAD1 (1 << 2) /* SATA #1 */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5c1e939..95bfa51 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -318,16 +319,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -341,7 +332,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);

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New patch to review for coreboot: 609941b intel/broadwell: Hide use of acpi_slp_type
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10359 -gerrit commit 609941b141b785f6a85ebd620cd8af1a53318218 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:18:18 2015 +0300 intel/broadwell: Hide use of acpi_slp_type Change-Id: I106779571df5168ec358ad1cc4dc4195639a7a7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/broadwell/igd.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/refcode.c | 3 ++- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 93c9e3c..987d56c 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -489,7 +489,7 @@ static void igd_init(struct device *dev) return; /* Wait for any configured pre-graphics delay */ - if (acpi_slp_type != SLEEP_STATE_S3) { + if (!acpi_is_wakeup_s3()) { #if IS_ENABLED(CONFIG_CHROMEOS) if (developer_mode_enabled() || recovery_mode_enabled() || vboot_wants_oprom()) @@ -542,7 +542,7 @@ static void igd_init(struct device *dev) memset((void *)((u32)fb->base), 0, 64); } - if (!gfx_get_init_done() && acpi_slp_type != 3) { + if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) { /* * Enable DDI-A if the Option ROM did not execute: * diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index ecfa1dd..8cd605f 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -1053,13 +1053,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 2fb365d..722669b 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -32,6 +32,7 @@ #endif #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include <soc/pm.h> #include <soc/ramstage.h> static pei_wrapper_entry_t load_refcode_from_cache(void) @@ -128,7 +129,7 @@ void broadwell_run_reference_code(void) mainboard_fill_pei_data(&pei_data); broadwell_fill_pei_data(&pei_data); - pei_data.boot_mode = acpi_slp_type; + pei_data.boot_mode = acpi_is_wakeup_s3() ? SLEEP_STATE_S3 : 0; pei_data.saved_data = (void *) &dummy; entry = load_reference_code();

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New patch to review for coreboot: 08723a0 binaryPI: Hide use of acpi_slp_type
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10358 -gerrit commit 08723a0f2d626aaa586a478d721cb46aa66a4ebc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:18:08 2015 +0300 binaryPI: Hide use of acpi_slp_type Change-Id: I867932db4388eb078b69b6f42c82967777d45d79 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/model_15_init.c | 6 +----- src/mainboard/amd/lamar/mainboard.c | 5 +---- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index da64d76..e2ba65e 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -34,9 +34,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/pi/s3_resume.h> -#endif static void model_15_init(device_t dev) { @@ -71,10 +69,8 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 3b0be4e..6d4bb06 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -158,11 +158,8 @@ static void mainboard_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); -#endif /* Initialize the PIRQ data structures for consumption */ pirq_setup();

1 0

Patch merged into coreboot/master: 4bddb75 chromeos: always enable timestamps
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit 4bddb75c4edb8880bae0aa45c3c31a45c27a1fc2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu May 28 13:48:47 2015 -0700 chromeos: always enable timestamps Timestamps should not be forced on by a subset of chipsets. However, they are a requirement on Chrome OS platforms, so have CONFIG_CHROMEOS select it. Change-Id: I408c6b17aa8721a3abec69020084174e414a8940 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/10357 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10357 for details. -gerrit

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New patch to review for coreboot: a25d7fb chromeos: always enable timestamps
by Stefan Reinauer 28 May '15

28 May '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10357 -gerrit commit a25d7fb1ca9ee971f7cafc42c74173cf74ff99c9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu May 28 13:48:47 2015 -0700 chromeos: always enable timestamps Timestamps should not be forced on by a subset of chipsets. However, they are a requirement on Chrome OS platforms, so have CONFIG_CHROMEOS select it. Change-Id: I408c6b17aa8721a3abec69020084174e414a8940 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/vendorcode/google/chromeos/Kconfig | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 85631fc..3f69fec 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CAR_MIGRATION - select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 4a71aa7..5e12e13 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION - select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 90e3505..9115c9c 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -28,6 +28,7 @@ config CHROMEOS select TPM select BOOTMODE_STRAPS select ELOG + select COLLECT_TIMESTAMPS help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

1 0

Patch merged into coreboot/master: 44cbe10 smm: Merge configs SMM_MODULES and SMM_TSEG
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit 44cbe10f592965d7611d8624f94f2952d42eba35 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:09:31 2015 +0200 smm: Merge configs SMM_MODULES and SMM_TSEG SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG Remove some newly dead code while on it. Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10355 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10355 for details. -gerrit

1 0

Patch merged into coreboot/master: beb4502 Remove leftover tseg_relocate
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit beb45020ace2b2d3f6cf4b88f9e7218c33a6225b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:06:24 2015 +0200 Remove leftover tseg_relocate Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10354 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10354 for details. -gerrit

1 0

Patch merged into coreboot/master: 7f46420 Migrate fsp_206ax to SMM_MODULES
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit 7f46420f4c85e7b296bfb4e8b3796a152e24b5fb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:03:51 2015 +0200 Migrate fsp_206ax to SMM_MODULES This gets rid of ugly tseg_relocate for fsp_bd82x6x. This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10353 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10353 for details. -gerrit

1 0

Patch merged into coreboot/master: 456f495 Migrate 2065x to SMM_MODULES
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit 456f495d4e3199146590bcb5cd76e12053c33c9e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 20:42:32 2015 +0200 Migrate 2065x to SMM_MODULES This gets rid of ugly tseg_relocate for ibexpeak. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to ibexpeak. Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10352 for details. -gerrit

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