coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 6f71380 Remove leftover tseg_relocate
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10354 -gerrit commit 6f713804dd41fe671125e6133aacc3c200be1b58 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:06:24 2015 +0200 Remove leftover tseg_relocate Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/spi/spi_flash.c | 17 ----------------- src/include/cpu/x86/smm.h | 4 ---- 2 files changed, 21 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d2a3c66..b0558bb 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -349,10 +349,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) /* search the table for matches in shift and id */ for (i = 0; i < ARRAY_SIZE(flashes); ++i) if (flashes[i].shift == shift && flashes[i].idcode == *idp) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Need to relocate this function */ - tseg_relocate((void **)&flashes[i].probe); -#endif /* we have a match, call probe */ flash = flashes[i].probe(spi, idp); if (flash) @@ -360,10 +356,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) } if (!flash && spi->programmer_specific_probe) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Need to relocate this function */ - tseg_relocate((void **)&spi->programmer_specific_probe); -#endif flash = spi->programmer_specific_probe (spi); } if (!flash) { @@ -372,15 +364,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) } flash_detected: -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Ensure flash handlers are valid for TSEG */ - tseg_relocate((void **)&flash->read); - tseg_relocate((void **)&flash->write); - tseg_relocate((void **)&flash->erase); - tseg_relocate((void **)&flash->status); - tseg_relocate((void **)&flash->name); -#endif - printk(BIOS_INFO, "SF: Detected %s with sector size 0x%x, total 0x%x\n", flash->name, flash->sector_size, flash->size); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6992774..56e9a65 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -487,15 +487,11 @@ void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#define tseg_relocate(ptr) #elif CONFIG_SMM_MODULES -#define tseg_relocate(ptr) #define smi_get_tseg_base() 0 #else /* Return address of TSEG base */ u32 smi_get_tseg_base(void); -/* Adjust pointer with TSEG base */ -void tseg_relocate(void **ptr); #endif /* Get PMBASE address */

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Patch set updated for coreboot: 5bd1e35 smm: Merge configs SMM_MODULES and SMM_TSEG
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10355 -gerrit commit 5bd1e35f241e4c20cdbc382ef222f7560e852fd6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:09:31 2015 +0200 smm: Merge configs SMM_MODULES and SMM_TSEG SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG Remove some newly dead code while on it. Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/model_2065x/Kconfig | 1 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/x86/Kconfig | 11 +- src/cpu/x86/smm/Makefile.inc | 14 +- src/cpu/x86/smm/smihandler.c | 11 -- src/cpu/x86/smm/smmhandler_tseg.S | 318 ---------------------------------- src/include/cpu/x86/smm.h | 13 +- src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - 13 files changed, 9 insertions(+), 366 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index b1a5e09..3280f77 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index f284807..779f1d6 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 946825b..4a85f09 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1ecc911..490849b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21a0fac..9e5f615 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -79,21 +79,12 @@ config LOGICAL_CPUS config SMM_TSEG bool default n - -config SMM_MODULES - bool - default n - depends on HAVE_SMI_HANDLER select RELOCATABLE_MODULES - help - If SMM_MODULES is selected then SMM handlers are built as modules. - A SMM stub along with a SMM loader/relocator. All the handlers are - written in C with stub being the only assembly. config SMM_MODULE_HEAP_SIZE hex default 0x4000 - depends on SMM_MODULES + depends on SMM_TSEG help This option determines the size of the heap within the SMM handler modules. diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 9f8f1d2..60b0388 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -34,7 +34,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group -ifeq ($(CONFIG_SMM_MODULES),y) +ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -79,7 +79,7 @@ else cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) endif -else # CONFIG_SMM_MODULES +else # CONFIG_SMM_TSEG $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o @@ -101,19 +101,11 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap.manual endif -# Use TSEG specific entry point and linker script -ifeq ($(CONFIG_SMM_TSEG),y) -smm-y += smmhandler_tseg.S -smm-c-ccopts += -fpic -SMM_LDFLAGS := -pie -SMM_LDSCRIPT := smm_tseg.ld -else smm-y += smmhandler.S SMM_LDFLAGS := SMM_LDSCRIPT := smm.ld -endif smm-y += smihandler.c -endif # CONFIG_SMM_MODULES +endif # CONFIG_SMM_TSEG diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 2387f6e..9c282c3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -29,7 +29,6 @@ static int do_driver_init = 1; -#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ @@ -61,7 +60,6 @@ void smi_release_lock(void) : "eax" ); } -#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -129,12 +127,6 @@ void smi_handler(u32 smm_revision) smm_state_save_area_t state_save; u32 smm_base = 0xa0000; /* ASEG */ -#if CONFIG_SMM_TSEG - /* Update global variable TSEG base */ - if (!smi_get_tseg_base()) - return; - smm_base = smi_get_tseg_base(); -#else /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs @@ -147,7 +139,6 @@ void smi_handler(u32 smm_revision) } return; } -#endif smi_backup_pci_address(); @@ -204,9 +195,7 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); -#if !CONFIG_SMM_TSEG smi_release_lock(); -#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S deleted file mode 100644 index 90dd932..0000000 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ /dev/null @@ -1,318 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* - * +--------------------------------+ - * | SMM Handler C Code | - * +--------------------------------+ 0x14000 - * | SMM Handler Heap | - * +--------------------------------+ 0x10000 - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | - * +--------------------------------+ 0xf000 - * | | - * | | - * | EARLY DATA (lock, vectors) | - * +--------------------------------+ 0x8400 - * | SMM Entry Node 0 (+ stack) | - * +--------------------------------+ 0x8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | - * +--------------------------------+ 0x7400 - * | | - * | SMM Handler Assembly Stub | - * | | - * +--------------------------------+ TSEG - * - */ - -#define LAPIC_ID 0xfee00020 -#define SMM_STACK_SIZE (0x400 - 0x10) - -/* Values for the xchg lock */ -#define SMI_LOCKED 0 -#define SMI_UNLOCKED 1 - -#define __PRE_RAM__ -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE -#include <northbridge/intel/sandybridge/sandybridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM -#include <northbridge/intel/nehalem/nehalem.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL -#include <northbridge/intel/haswell/haswell.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#error "Northbridge must define TSEG_BAR." -#endif -#endif - - - -/* initially SMM is some sort of real mode. Let gcc know - * how to treat the SMM handler stub - */ - -.section ".handler", "a", @progbits - -.code16 - -/** - * SMM code to enable protected mode and jump to the - * C-written function void smi_handler(u32 smm_revision) - * - * All the bad magic is not all that bad after all. - */ -.global smm_handler_start -smm_handler_start: - movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ - andl $~1, %edx /* Remove lock bit */ - - /* Obtain lock */ - movl %edx, %ebx - addl $(smm_lock), %ebx - movw $SMI_LOCKED, %ax - addr32 xchg %ax, (%ebx) - cmpw $SMI_UNLOCKED, %ax - - /* Proceed if we got the lock */ - je smm_check_prot_vector - - /* If we did not get the lock, wait for release */ -wait_for_unlock: - pause - addr32 movw (%ebx), %ax - cmpw $SMI_LOCKED, %ax - je wait_for_unlock - rsm - -smm_check_prot_vector: - /* See if we need to adjust protected vector */ - movl %edx, %eax - addl $(smm_prot_vector), %eax - addr32 movl (%eax), %ebx - cmpl $(smm_prot_start), %ebx - jne smm_check_gdt_vector - - /* Adjust vector with TSEG offset */ - addl %edx, %ebx - addr32 movl %ebx, (%eax) - -smm_check_gdt_vector: - /* See if we need to adjust GDT vector */ - movl %edx, %eax - addl $(smm_gdt_vector + 2), %eax - addr32 movl (%eax), %ebx - cmpl $(smm_gdt - smm_handler_start), %ebx - jne smm_load_gdt - - /* Adjust vector with TSEG offset */ - addl %edx, %ebx - addr32 movl %ebx, (%eax) - -smm_load_gdt: - movl $(smm_gdt_vector), %ebx - addl %edx, %ebx /* TSEG base in %edx */ - data32 lgdt (%ebx) - - movl %cr0, %eax - andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ - movl %eax, %cr0 - - /* Enable protected mode */ - movl $(smm_prot_vector), %eax - addl %edx, %eax - data32 ljmp *(%eax) - -.code32 -smm_prot_start: - /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Get this CPU's LAPIC ID */ - movl $LAPIC_ID, %esi - movl (%esi), %ecx - shr $24, %ecx - - /* calculate stack offset by multiplying the APIC ID - * by 1024 (0x400), and save that offset in ebp. - */ - shl $10, %ecx - movl %ecx, %ebp - - /* We put the stack for each core right above - * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, - * we spare 0x10 bytes for the jump to be sure. - */ - movl $0x8010, %eax /* core 0 address */ - addl %edx, %eax /* addjust for TSEG */ - subl %ecx, %eax /* subtract offset, see above */ - movl %eax, %ebx /* Save bottom of stack in ebx */ - - /* clear stack */ - cld - movl %eax, %edi - movl $(SMM_STACK_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* set new stack */ - addl $SMM_STACK_SIZE, %ebx - movl %ebx, %esp - - /* Get SMM revision */ - movl $0xfefc, %ebx /* core 0 address */ - addl %edx, %ebx /* addjust for TSEG */ - subl %ebp, %ebx /* subtract core X offset */ - movl (%ebx), %eax - pushl %eax - - /* Call 32bit C handler */ - call smi_handler - - /* Release lock */ - movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ - andl $~1, %ebx /* Remove lock bit */ - addl $(smm_lock), %ebx - movw $SMI_UNLOCKED, %ax - xchg %ax, (%ebx) - - /* To return, just do rsm. It will "clean up" protected mode */ - rsm - -smm_gdt: - /* The first GDT entry can not be used. Keep it zero */ - .long 0x00000000, 0x00000000 - - /* gdt selector 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ - - /* gdt selector 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - -smm_gdt_end: - -.section ".earlydata", "a", @progbits - -.code16 - -.align 4, 0xff - -smm_lock: - .word SMI_UNLOCKED - -.align 4, 0xff - -smm_prot_vector: - .long smm_prot_start - .short 8 - -.align 4, 0xff - -smm_gdt_vector: - .word smm_gdt_end - smm_gdt - 1 - .long smm_gdt - smm_handler_start - -.section ".jumptable", "a", @progbits - -/* This is the SMM jump table. All cores use the same SMM handler - * for simplicity. But SMM Entry needs to be different due to the - * save state area. The jump table makes sure all CPUs jump into the - * real handler on SMM entry. - */ - -/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores - * shall be used, below table has to be updated, as well as smm_tseg.ld - */ - -/* When using TSEG do a relative jump and fix up the CS later since we - * do not know what our TSEG base is yet. - */ - -.code16 -jumptable: - /* core 15 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 14 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 13 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 12 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 11 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 10 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 9 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 8 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 7 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 6 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 5 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 4 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 3 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 2 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 1 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 0 */ - jmp smm_handler_start -.align 1024, 0x00 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 56e9a65..b717811 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -472,7 +472,7 @@ int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); -#if CONFIG_SMM_MODULES +#if CONFIG_SMM_TSEG void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); @@ -480,24 +480,21 @@ void southbridge_smi_handler(void); void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -#endif /* CONFIG_SMM_MODULES */ +#endif /* CONFIG_SMM_TSEG */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#elif CONFIG_SMM_MODULES -#define smi_get_tseg_base() 0 #else -/* Return address of TSEG base */ -u32 smi_get_tseg_base(void); +#define smi_get_tseg_base() 0 #endif /* Get PMBASE address */ u16 smm_get_pmbase(void); -#if CONFIG_SMM_MODULES +#if CONFIG_SMM_TSEG struct smm_runtime { u32 smbase; @@ -569,7 +566,7 @@ struct smm_loader_params { int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, int size, struct smm_loader_params *params); #endif /* __SMM__ */ -#endif /* CONFIG_SMM_MODULES */ +#endif /* CONFIG_SMM_TSEG */ /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 85631fc..0290632 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3f938c3..aa191b3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6c54a55..33fa4de 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 1cdbddc..371ad52 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select BAYTRAIL_SMM select SMP

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Patch set updated for coreboot: 5f18d19 Migrate fsp_206ax to SMM_MODULES
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10353 -gerrit commit 5f18d1934e908113866c4828b573ca61905b8682 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:03:51 2015 +0200 Migrate fsp_206ax to SMM_MODULES This gets rid of ugly tseg_relocate for fsp_bd82x6x. This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/fsp_model_206ax/Makefile.inc | 2 + src/cpu/intel/fsp_model_206ax/model_206ax.h | 1 + src/cpu/intel/fsp_model_206ax/smmrelocate.c | 333 +++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 12 +- .../intel/fsp_sandybridge/northbridge.h | 1 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 51 +--- src/southbridge/intel/fsp_bd82x6x/pch.h | 5 + src/southbridge/intel/fsp_bd82x6x/smi.c | 103 ++----- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 68 ++--- 10 files changed, 385 insertions(+), 192 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 3280f77..b1a5e09 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index 577d44e..4e0f956 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -13,3 +13,5 @@ ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)") CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) endif endif + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 49d995b..bf5de53 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -106,6 +106,7 @@ void intel_model_206ax_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +void smm_relocate(void); #endif #endif diff --git a/src/cpu/intel/fsp_model_206ax/smmrelocate.c b/src/cpu/intel/fsp_model_206ax/smmrelocate.c new file mode 100644 index 0000000..c2f6712 --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/smmrelocate.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <northbridge/intel/fsp_sandybridge/northbridge.h> +#include <southbridge/intel/fsp_bd82x6x/pch.h> +#include "model_206ax.h" + +#define EMRRphysBase_MSR 0x1f4 +#define EMRRphysMask_MSR 0x1f5 +#define UNCORE_EMRRphysBase_MSR 0x2f4 +#define UNCORE_EMRRphysMask_MSR 0x2f5 + +#define CORE_THREAD_COUNT_MSR 0x35 + +#define SMRR_SUPPORTED (1<<11) +#define EMRR_SUPPORTED (1<<12) + +struct smm_relocation_params { + u32 smram_base; + u32 smram_size; + u32 ied_base; + u32 ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t emrr_base; + msr_t emrr_mask; + msr_t uncore_emrr_base; + msr_t uncore_emrr_mask; +}; + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); + wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); +} + +static inline void write_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->emrr_base.lo, relo_params->emrr_mask.lo); + wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); + wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); +} + +static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); + wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); + wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void asmlinkage cpu_smm_do_relocation(void *arg) +{ + em64t101_smm_state_save_area_t *save_state; + msr_t mtrr_cap; + struct smm_relocation_params *relo_params; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + relo_params = p->arg; + cpu = p->cpu; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* All threads need to set IEDBASE and SMBASE in the save state area. + * Since one thread runs at a time during the relocation the save state + * is the same for all cpus. */ + save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - + runtime->save_state_size); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + save_state->smbase = relo_params->smram_base - + cpu * runtime->save_state_size; + save_state->iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRRcap_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); + + if (mtrr_cap.lo & EMRR_SUPPORTED) { + write_emrr(relo_params); + /* UNCORE_EMRR msrs are package level. Therefore, only + * configure these MSRs on the BSP. */ + if (cpu == 0) + write_uncore_emrr(relo_params); + } + + southbridge_clear_smi_status(); +} + +static u32 northbridge_get_base_reg(device_t dev, int reg) +{ + u32 value; + + value = pci_read_config32(dev, reg); + /* Base registers are at 1MiB granularity. */ + value &= ~((1 << 20) - 1); + return value; +} + +static void fill_in_relocation_params(device_t dev, + struct smm_relocation_params *params) +{ + u32 tseg_size; + u32 tsegmb; + u32 bgsm; + u32 emrr_base; + u32 emrr_size; + int phys_bits; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + /* Some of the range registers are dependent on the number of physical + * address bits supported. */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + /* The range bounded by the TSEGMB and BGSM registers encompasses the + * SMRAM range as well as the IED range. However, the SMRAM available + * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. + */ + tsegmb = northbridge_get_base_reg(dev, TSEG); + bgsm = northbridge_get_base_reg(dev, BGSM); + tseg_size = bgsm - tsegmb; + + params->smram_base = tsegmb; + params->smram_size = 4 << 20; + params->ied_base = tsegmb + params->smram_size; + params->ied_size = tseg_size - params->smram_size; + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.hi = 0; + + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ + emrr_base = (params->ied_base + (2 << 20)) & rmask; + emrr_size = params->ied_size - (2 << 20); + + /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + * on the number of physical address bits supported. */ + params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; + params->emrr_base.hi = 0; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + + /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_emrr_base.lo = emrr_base; + params->uncore_emrr_base.hi = 0; + params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + MTRRphysMaskValid; + params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; +} + +static int install_relocation_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* The default SMM entry happens serially at the default location. + * Therefore, there is only 1 concurrent save state area. Set the + * stack size to the save state size, and call into the + * do_relocation handler. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = &cpu_smm_do_relocation, + .handler_arg = (void *)relo_params, + }; + + return smm_setup_relocation_handler(&smm_params); +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); +} + +static int install_permanent_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_params->smram_base); + return smm_load_module((void *)relo_params->smram_base, + relo_params->smram_size, &smm_params); +} + +static int cpu_smm_setup(void) +{ + device_t dev; + int num_cpus; + msr_t msr; + + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + fill_in_relocation_params(dev, &smm_reloc_params); + + setup_ied_area(&smm_reloc_params); + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_cpus = msr.lo & 0xffff; + if (num_cpus > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); + } + + if (install_relocation_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); + return -1; + } + + if (install_permanent_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + /* TODO(adurbin): Is this really needed? */ + wbinvd(); + + return 0; +} + +void smm_init(void) +{ + /* Return early if CPU SMM setup failed. */ + if (cpu_smm_setup()) + return; + + southbridge_smm_init(); + + /* Initiate first SMI to kick off SMM-context relocation. Note: this + * SMI being triggered here queues up an SMI in the APs which are in + * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI + * at the SMM_DEFAULT_BASE before jumping to startup vector. */ + southbridge_trigger_smi(); + + printk(BIOS_DEBUG, "Relocation complete.\n"); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 0ff7149..ec489ce 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -36,8 +36,6 @@ #include "../../../southbridge/intel/i82801dx/i82801dx.h" #elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X -#include "../../../southbridge/intel/fsp_bd82x6x/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX #include "../../../southbridge/intel/i82801ix/i82801ix.h" #else @@ -45,15 +43,7 @@ #endif #if CONFIG_SMM_TSEG - -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#error "Northbridge must define TSEG_BAR." -#endif - -#include <cpu/x86/mtrr.h> +#error "Don't use this file with TSEG." #endif /* CONFIG_SMM_TSEG */ diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index 95831a5..6d4f83c 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -102,6 +102,7 @@ #define TOM 0xa0 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 73e11e8..1d92532 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -42,7 +42,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_fsp_bd82x6x_config config_t; @@ -405,58 +404,20 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; } -#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(struct device *dev) +static void pch_set_acpi_mode(void) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - - if (!acpi_is_wakeup_s3()) { + if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); // Enable ACPI mode + outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode printk(BIOS_DEBUG, "done.\n"); #else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); // Disable ACPI mode + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); #endif } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } -#endif static void pch_disable_smm_only_flashing(struct device *dev) { @@ -541,9 +502,7 @@ static void lpc_init(struct device *dev) pch_disable_smm_only_flashing(dev); -#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif + pch_set_acpi_mode(); pch_fixups(dev); } diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 9e3b4da..10e536e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -64,6 +64,11 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) && !defined(__SMM__) #include "chip.h" +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); + int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index bb0be47..2374f5f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -29,13 +29,6 @@ #include <string.h> #include "pch.h" -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" -#endif - -extern unsigned char _binary_smm_start; -extern unsigned char _binary_smm_size; - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -231,15 +224,18 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); } -extern uint8_t smm_relocation_start, smm_relocation_end; - -static void smm_relocate(void) +void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; - printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_ELOG + /* Log events from chipset before clearing */ + pch_log_state(); +#endif + + printk(BIOS_DEBUG, "Initializing southbridge SMI..."); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; @@ -252,10 +248,6 @@ static void smm_relocate(void) return; } - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); @@ -304,7 +296,10 @@ static void smm_relocate(void) smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); +} +void southbridge_trigger_smi(void) +{ /** * There are several methods of raising a controlled SMI# via * software, among them: @@ -323,76 +318,16 @@ static void smm_relocate(void) outb(0x00, 0xb2); } -static int smm_handler_copied = 0; - -static void smm_install(void) +void southbridge_clear_smi_status(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - u32 smm_base = 0xa0000; - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = IED_SIZE, - .reserved = {0}, - }; - - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - /* enable the SMM memory window */ - pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); - -#if CONFIG_SMM_TSEG - smm_base = pci_read_config32(dev, TSEG) & ~1; -#endif - - /* copy the real SMM handler */ - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); - memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size); - - /* copy the IED header into place */ - if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { - /* Top of TSEG region */ - smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; - printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); - memcpy((void *)smm_base, &ied, sizeof(ied)); - } - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) -{ -#if CONFIG_ELOG - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - /* Put SMM code to 0xa0000 */ - smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + /* Clear SMI status */ + reset_smi_status(); + + /* Clear PM1 status */ + reset_pm1_status(); + + /* Set EOS bit so other SMIs can occur. */ + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 0648ce3..96de457 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -51,28 +51,12 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { return gnvs; } -#if CONFIG_SMM_TSEG -static u32 tseg_base = 0; -u32 smi_get_tseg_base(void) -{ - if (!tseg_base) - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; - return tseg_base; -} -void tseg_relocate(void **ptr) -{ - /* Adjust pointer with TSEG base */ - if (*ptr && *ptr < (void*)smi_get_tseg_base()) - *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); -} -#endif - /** * @brief read and clear PM1_STS * @return PM1_STS register @@ -323,7 +307,7 @@ static void southbridge_gate_memory_reset(void) outl(reg32, gpiobase + GP_LVL2); } -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_sleep(void) { u8 reg8; u32 reg32; @@ -338,8 +322,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outb(tmp70, 0x70); outb(tmp72, 0x72); - void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; - /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); reg8 &= ~SLP_SMI_EN; @@ -351,8 +333,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat slp_typ = (reg32 >> 10) & 7; /* Do any mainboard sleep handling */ - tseg_relocate((void **)&mainboard_sleep); - mainboard_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -428,13 +409,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; - u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00; int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = (em64t101_smm_state_save_area_t *) - (base - (node * 0x400)); + state = smm_get_save_state(node); /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) @@ -481,11 +460,10 @@ static void southbridge_smi_gsmi(void) } #endif -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_apmc(void) { u32 pmctrl; u8 reg8; - int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -538,11 +516,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state #endif } - tseg_relocate((void **)&mainboard_apmc); - mainboard_apmc(reg8); + mainboard_smi_apmc(reg8); } -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_pm1(void) { u16 pm1_sts; @@ -563,7 +540,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpe0(void) { u32 gpe0_sts; @@ -571,17 +548,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpi(void) { - void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - tseg_relocate((void **)&mainboard_gpi); - mainboard_gpi(reg16); + mainboard_smi_gpi(reg16); if (reg16) printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); @@ -589,7 +564,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_mc(void) { u32 reg32; @@ -604,7 +579,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_tco(void) { u32 tco_sts; @@ -641,7 +616,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_periodic(void) { u32 reg32; @@ -654,7 +629,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s printk(BIOS_DEBUG, "Periodic SMI.\n"); } -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -708,8 +683,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); +typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved @@ -753,7 +727,7 @@ static smi_handler_t southbridge_smi[32] = { * @param state_save */ -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { int i, dump = 0; u32 smi_sts; @@ -770,15 +744,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) { -#if CONFIG_SMM_TSEG - smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + - smi_get_tseg_base()); - if (handler) - handler(node, state_save); -#else - southbridge_smi[i](node, state_save); -#endif + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i);

1 0

Patch set updated for coreboot: 7788807 Remove leftover smi_get_tseg_base
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10356 -gerrit commit 7788807f195585a1cfd671dab5c5bf4fa52435f8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:15:14 2015 +0200 Remove leftover smi_get_tseg_base Change-Id: I8e694f37c8709efd702208aa005096ebf1f3abb5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/include/cpu/x86/smm.h | 2 -- src/lib/malloc.c | 6 ------ 2 files changed, 8 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b717811..f7aafa9 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -487,8 +487,6 @@ void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#else -#define smi_get_tseg_base() 0 #endif /* Get PMBASE address */ diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 0140185..9974b2c 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -44,11 +44,5 @@ void *memalign(size_t boundary, size_t size) void *malloc(size_t size) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - if (!free_mem_ptr) { - free_mem_ptr = &_heap + smi_get_tseg_base(); - free_mem_end_ptr = &_eheap + smi_get_tseg_base(); - } -#endif return memalign(sizeof(u64), size); }

1 0

New patch to review for coreboot: 87328ba Remove leftover smi_get_tseg_base
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10356 -gerrit commit 87328baef122a29bb717b260c8a2c362cee61d7a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:15:14 2015 +0200 Remove leftover smi_get_tseg_base Change-Id: I8e694f37c8709efd702208aa005096ebf1f3abb5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/include/cpu/x86/smm.h | 2 -- src/lib/malloc.c | 6 ------ 2 files changed, 8 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b717811..f7aafa9 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -487,8 +487,6 @@ void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#else -#define smi_get_tseg_base() 0 #endif /* Get PMBASE address */ diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 0140185..9974b2c 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -44,11 +44,5 @@ void *memalign(size_t boundary, size_t size) void *malloc(size_t size) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - if (!free_mem_ptr) { - free_mem_ptr = &_heap + smi_get_tseg_base(); - free_mem_end_ptr = &_eheap + smi_get_tseg_base(); - } -#endif return memalign(sizeof(u64), size); }

1 0

New patch to review for coreboot: 77717d0 smm: Merge configs SMM_MODULES and SMM_TSEG
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10355 -gerrit commit 77717d0c57e5158f747a79c763ebff012cac9573 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:09:31 2015 +0200 smm: Merge configs SMM_MODULES and SMM_TSEG SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG Remove some newly dead code while on it. Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/model_2065x/Kconfig | 1 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/x86/Kconfig | 11 +- src/cpu/x86/smm/Makefile.inc | 14 +- src/cpu/x86/smm/smihandler.c | 11 -- src/cpu/x86/smm/smmhandler_tseg.S | 318 ---------------------------------- src/include/cpu/x86/smm.h | 13 +- src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - 13 files changed, 9 insertions(+), 366 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index b1a5e09..3280f77 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index f284807..779f1d6 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 946825b..4a85f09 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1ecc911..490849b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21a0fac..9e5f615 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -79,21 +79,12 @@ config LOGICAL_CPUS config SMM_TSEG bool default n - -config SMM_MODULES - bool - default n - depends on HAVE_SMI_HANDLER select RELOCATABLE_MODULES - help - If SMM_MODULES is selected then SMM handlers are built as modules. - A SMM stub along with a SMM loader/relocator. All the handlers are - written in C with stub being the only assembly. config SMM_MODULE_HEAP_SIZE hex default 0x4000 - depends on SMM_MODULES + depends on SMM_TSEG help This option determines the size of the heap within the SMM handler modules. diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 9f8f1d2..60b0388 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -34,7 +34,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group -ifeq ($(CONFIG_SMM_MODULES),y) +ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -79,7 +79,7 @@ else cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) endif -else # CONFIG_SMM_MODULES +else # CONFIG_SMM_TSEG $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o @@ -101,19 +101,11 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap.manual endif -# Use TSEG specific entry point and linker script -ifeq ($(CONFIG_SMM_TSEG),y) -smm-y += smmhandler_tseg.S -smm-c-ccopts += -fpic -SMM_LDFLAGS := -pie -SMM_LDSCRIPT := smm_tseg.ld -else smm-y += smmhandler.S SMM_LDFLAGS := SMM_LDSCRIPT := smm.ld -endif smm-y += smihandler.c -endif # CONFIG_SMM_MODULES +endif # CONFIG_SMM_TSEG diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 2387f6e..9c282c3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -29,7 +29,6 @@ static int do_driver_init = 1; -#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ @@ -61,7 +60,6 @@ void smi_release_lock(void) : "eax" ); } -#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -129,12 +127,6 @@ void smi_handler(u32 smm_revision) smm_state_save_area_t state_save; u32 smm_base = 0xa0000; /* ASEG */ -#if CONFIG_SMM_TSEG - /* Update global variable TSEG base */ - if (!smi_get_tseg_base()) - return; - smm_base = smi_get_tseg_base(); -#else /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs @@ -147,7 +139,6 @@ void smi_handler(u32 smm_revision) } return; } -#endif smi_backup_pci_address(); @@ -204,9 +195,7 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); -#if !CONFIG_SMM_TSEG smi_release_lock(); -#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S deleted file mode 100644 index 90dd932..0000000 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ /dev/null @@ -1,318 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* - * +--------------------------------+ - * | SMM Handler C Code | - * +--------------------------------+ 0x14000 - * | SMM Handler Heap | - * +--------------------------------+ 0x10000 - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | - * +--------------------------------+ 0xf000 - * | | - * | | - * | EARLY DATA (lock, vectors) | - * +--------------------------------+ 0x8400 - * | SMM Entry Node 0 (+ stack) | - * +--------------------------------+ 0x8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | - * +--------------------------------+ 0x7400 - * | | - * | SMM Handler Assembly Stub | - * | | - * +--------------------------------+ TSEG - * - */ - -#define LAPIC_ID 0xfee00020 -#define SMM_STACK_SIZE (0x400 - 0x10) - -/* Values for the xchg lock */ -#define SMI_LOCKED 0 -#define SMI_UNLOCKED 1 - -#define __PRE_RAM__ -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE -#include <northbridge/intel/sandybridge/sandybridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM -#include <northbridge/intel/nehalem/nehalem.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL -#include <northbridge/intel/haswell/haswell.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#error "Northbridge must define TSEG_BAR." -#endif -#endif - - - -/* initially SMM is some sort of real mode. Let gcc know - * how to treat the SMM handler stub - */ - -.section ".handler", "a", @progbits - -.code16 - -/** - * SMM code to enable protected mode and jump to the - * C-written function void smi_handler(u32 smm_revision) - * - * All the bad magic is not all that bad after all. - */ -.global smm_handler_start -smm_handler_start: - movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ - andl $~1, %edx /* Remove lock bit */ - - /* Obtain lock */ - movl %edx, %ebx - addl $(smm_lock), %ebx - movw $SMI_LOCKED, %ax - addr32 xchg %ax, (%ebx) - cmpw $SMI_UNLOCKED, %ax - - /* Proceed if we got the lock */ - je smm_check_prot_vector - - /* If we did not get the lock, wait for release */ -wait_for_unlock: - pause - addr32 movw (%ebx), %ax - cmpw $SMI_LOCKED, %ax - je wait_for_unlock - rsm - -smm_check_prot_vector: - /* See if we need to adjust protected vector */ - movl %edx, %eax - addl $(smm_prot_vector), %eax - addr32 movl (%eax), %ebx - cmpl $(smm_prot_start), %ebx - jne smm_check_gdt_vector - - /* Adjust vector with TSEG offset */ - addl %edx, %ebx - addr32 movl %ebx, (%eax) - -smm_check_gdt_vector: - /* See if we need to adjust GDT vector */ - movl %edx, %eax - addl $(smm_gdt_vector + 2), %eax - addr32 movl (%eax), %ebx - cmpl $(smm_gdt - smm_handler_start), %ebx - jne smm_load_gdt - - /* Adjust vector with TSEG offset */ - addl %edx, %ebx - addr32 movl %ebx, (%eax) - -smm_load_gdt: - movl $(smm_gdt_vector), %ebx - addl %edx, %ebx /* TSEG base in %edx */ - data32 lgdt (%ebx) - - movl %cr0, %eax - andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ - movl %eax, %cr0 - - /* Enable protected mode */ - movl $(smm_prot_vector), %eax - addl %edx, %eax - data32 ljmp *(%eax) - -.code32 -smm_prot_start: - /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Get this CPU's LAPIC ID */ - movl $LAPIC_ID, %esi - movl (%esi), %ecx - shr $24, %ecx - - /* calculate stack offset by multiplying the APIC ID - * by 1024 (0x400), and save that offset in ebp. - */ - shl $10, %ecx - movl %ecx, %ebp - - /* We put the stack for each core right above - * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, - * we spare 0x10 bytes for the jump to be sure. - */ - movl $0x8010, %eax /* core 0 address */ - addl %edx, %eax /* addjust for TSEG */ - subl %ecx, %eax /* subtract offset, see above */ - movl %eax, %ebx /* Save bottom of stack in ebx */ - - /* clear stack */ - cld - movl %eax, %edi - movl $(SMM_STACK_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl - - /* set new stack */ - addl $SMM_STACK_SIZE, %ebx - movl %ebx, %esp - - /* Get SMM revision */ - movl $0xfefc, %ebx /* core 0 address */ - addl %edx, %ebx /* addjust for TSEG */ - subl %ebp, %ebx /* subtract core X offset */ - movl (%ebx), %eax - pushl %eax - - /* Call 32bit C handler */ - call smi_handler - - /* Release lock */ - movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ - movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ - andl $~1, %ebx /* Remove lock bit */ - addl $(smm_lock), %ebx - movw $SMI_UNLOCKED, %ax - xchg %ax, (%ebx) - - /* To return, just do rsm. It will "clean up" protected mode */ - rsm - -smm_gdt: - /* The first GDT entry can not be used. Keep it zero */ - .long 0x00000000, 0x00000000 - - /* gdt selector 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ - - /* gdt selector 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - -smm_gdt_end: - -.section ".earlydata", "a", @progbits - -.code16 - -.align 4, 0xff - -smm_lock: - .word SMI_UNLOCKED - -.align 4, 0xff - -smm_prot_vector: - .long smm_prot_start - .short 8 - -.align 4, 0xff - -smm_gdt_vector: - .word smm_gdt_end - smm_gdt - 1 - .long smm_gdt - smm_handler_start - -.section ".jumptable", "a", @progbits - -/* This is the SMM jump table. All cores use the same SMM handler - * for simplicity. But SMM Entry needs to be different due to the - * save state area. The jump table makes sure all CPUs jump into the - * real handler on SMM entry. - */ - -/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores - * shall be used, below table has to be updated, as well as smm_tseg.ld - */ - -/* When using TSEG do a relative jump and fix up the CS later since we - * do not know what our TSEG base is yet. - */ - -.code16 -jumptable: - /* core 15 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 14 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 13 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 12 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 11 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 10 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 9 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 8 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 7 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 6 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 5 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 4 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 3 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 2 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 1 */ - jmp smm_handler_start -.align 1024, 0x00 - /* core 0 */ - jmp smm_handler_start -.align 1024, 0x00 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 56e9a65..b717811 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -472,7 +472,7 @@ int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); -#if CONFIG_SMM_MODULES +#if CONFIG_SMM_TSEG void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); @@ -480,24 +480,21 @@ void southbridge_smi_handler(void); void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -#endif /* CONFIG_SMM_MODULES */ +#endif /* CONFIG_SMM_TSEG */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#elif CONFIG_SMM_MODULES -#define smi_get_tseg_base() 0 #else -/* Return address of TSEG base */ -u32 smi_get_tseg_base(void); +#define smi_get_tseg_base() 0 #endif /* Get PMBASE address */ u16 smm_get_pmbase(void); -#if CONFIG_SMM_MODULES +#if CONFIG_SMM_TSEG struct smm_runtime { u32 smbase; @@ -569,7 +566,7 @@ struct smm_loader_params { int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, int size, struct smm_loader_params *params); #endif /* __SMM__ */ -#endif /* CONFIG_SMM_MODULES */ +#endif /* CONFIG_SMM_TSEG */ /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 85631fc..0290632 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3f938c3..aa191b3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6c54a55..33fa4de 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 1cdbddc..371ad52 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT - select SMM_MODULES select SMM_TSEG select BAYTRAIL_SMM select SMP

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New patch to review for coreboot: be858a0 Remove leftover tseg_relocate
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10354 -gerrit commit be858a0edbff4280918d05c81573442d0fa666c3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:06:24 2015 +0200 Remove leftover tseg_relocate Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/spi/spi_flash.c | 17 ----------------- src/include/cpu/x86/smm.h | 4 ---- 2 files changed, 21 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d2a3c66..b0558bb 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -349,10 +349,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) /* search the table for matches in shift and id */ for (i = 0; i < ARRAY_SIZE(flashes); ++i) if (flashes[i].shift == shift && flashes[i].idcode == *idp) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Need to relocate this function */ - tseg_relocate((void **)&flashes[i].probe); -#endif /* we have a match, call probe */ flash = flashes[i].probe(spi, idp); if (flash) @@ -360,10 +356,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) } if (!flash && spi->programmer_specific_probe) { -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Need to relocate this function */ - tseg_relocate((void **)&spi->programmer_specific_probe); -#endif flash = spi->programmer_specific_probe (spi); } if (!flash) { @@ -372,15 +364,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) } flash_detected: -#if CONFIG_SMM_TSEG && defined(__SMM__) - /* Ensure flash handlers are valid for TSEG */ - tseg_relocate((void **)&flash->read); - tseg_relocate((void **)&flash->write); - tseg_relocate((void **)&flash->erase); - tseg_relocate((void **)&flash->status); - tseg_relocate((void **)&flash->name); -#endif - printk(BIOS_INFO, "SF: Detected %s with sector size 0x%x, total 0x%x\n", flash->name, flash->sector_size, flash->size); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6992774..56e9a65 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -487,15 +487,11 @@ void mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); -#define tseg_relocate(ptr) #elif CONFIG_SMM_MODULES -#define tseg_relocate(ptr) #define smi_get_tseg_base() 0 #else /* Return address of TSEG base */ u32 smi_get_tseg_base(void); -/* Adjust pointer with TSEG base */ -void tseg_relocate(void **ptr); #endif /* Get PMBASE address */

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New patch to review for coreboot: 9fe033f Migrate fsp_206ax to SMM_MODULES
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10353 -gerrit commit 9fe033f3e0a1202738913e222ba56677e1d8e795 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 21:03:51 2015 +0200 Migrate fsp_206ax to SMM_MODULES This gets rid of ugly tseg_relocate for fsp_bd82x6x. This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/fsp_model_206ax/Makefile.inc | 2 + src/cpu/intel/fsp_model_206ax/model_206ax.h | 1 + src/cpu/intel/fsp_model_206ax/smmrelocate.c | 333 +++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 9 +- .../intel/fsp_sandybridge/northbridge.h | 1 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 51 +--- src/southbridge/intel/fsp_bd82x6x/pch.h | 5 + src/southbridge/intel/fsp_bd82x6x/smi.c | 103 ++----- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 68 ++--- 10 files changed, 385 insertions(+), 189 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 3280f77..b1a5e09 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index 577d44e..4e0f956 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -13,3 +13,5 @@ ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)") CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) endif endif + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 49d995b..bf5de53 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -106,6 +106,7 @@ void intel_model_206ax_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +void smm_relocate(void); #endif #endif diff --git a/src/cpu/intel/fsp_model_206ax/smmrelocate.c b/src/cpu/intel/fsp_model_206ax/smmrelocate.c new file mode 100644 index 0000000..c2f6712 --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/smmrelocate.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <northbridge/intel/fsp_sandybridge/northbridge.h> +#include <southbridge/intel/fsp_bd82x6x/pch.h> +#include "model_206ax.h" + +#define EMRRphysBase_MSR 0x1f4 +#define EMRRphysMask_MSR 0x1f5 +#define UNCORE_EMRRphysBase_MSR 0x2f4 +#define UNCORE_EMRRphysMask_MSR 0x2f5 + +#define CORE_THREAD_COUNT_MSR 0x35 + +#define SMRR_SUPPORTED (1<<11) +#define EMRR_SUPPORTED (1<<12) + +struct smm_relocation_params { + u32 smram_base; + u32 smram_size; + u32 ied_base; + u32 ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t emrr_base; + msr_t emrr_mask; + msr_t uncore_emrr_base; + msr_t uncore_emrr_mask; +}; + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); + wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); +} + +static inline void write_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->emrr_base.lo, relo_params->emrr_mask.lo); + wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); + wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); +} + +static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); + wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); + wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void asmlinkage cpu_smm_do_relocation(void *arg) +{ + em64t101_smm_state_save_area_t *save_state; + msr_t mtrr_cap; + struct smm_relocation_params *relo_params; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + relo_params = p->arg; + cpu = p->cpu; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* All threads need to set IEDBASE and SMBASE in the save state area. + * Since one thread runs at a time during the relocation the save state + * is the same for all cpus. */ + save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - + runtime->save_state_size); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + save_state->smbase = relo_params->smram_base - + cpu * runtime->save_state_size; + save_state->iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRRcap_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); + + if (mtrr_cap.lo & EMRR_SUPPORTED) { + write_emrr(relo_params); + /* UNCORE_EMRR msrs are package level. Therefore, only + * configure these MSRs on the BSP. */ + if (cpu == 0) + write_uncore_emrr(relo_params); + } + + southbridge_clear_smi_status(); +} + +static u32 northbridge_get_base_reg(device_t dev, int reg) +{ + u32 value; + + value = pci_read_config32(dev, reg); + /* Base registers are at 1MiB granularity. */ + value &= ~((1 << 20) - 1); + return value; +} + +static void fill_in_relocation_params(device_t dev, + struct smm_relocation_params *params) +{ + u32 tseg_size; + u32 tsegmb; + u32 bgsm; + u32 emrr_base; + u32 emrr_size; + int phys_bits; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + /* Some of the range registers are dependent on the number of physical + * address bits supported. */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + /* The range bounded by the TSEGMB and BGSM registers encompasses the + * SMRAM range as well as the IED range. However, the SMRAM available + * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. + */ + tsegmb = northbridge_get_base_reg(dev, TSEG); + bgsm = northbridge_get_base_reg(dev, BGSM); + tseg_size = bgsm - tsegmb; + + params->smram_base = tsegmb; + params->smram_size = 4 << 20; + params->ied_base = tsegmb + params->smram_size; + params->ied_size = tseg_size - params->smram_size; + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.hi = 0; + + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ + emrr_base = (params->ied_base + (2 << 20)) & rmask; + emrr_size = params->ied_size - (2 << 20); + + /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + * on the number of physical address bits supported. */ + params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; + params->emrr_base.hi = 0; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + + /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_emrr_base.lo = emrr_base; + params->uncore_emrr_base.hi = 0; + params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + MTRRphysMaskValid; + params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; +} + +static int install_relocation_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* The default SMM entry happens serially at the default location. + * Therefore, there is only 1 concurrent save state area. Set the + * stack size to the save state size, and call into the + * do_relocation handler. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = &cpu_smm_do_relocation, + .handler_arg = (void *)relo_params, + }; + + return smm_setup_relocation_handler(&smm_params); +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); +} + +static int install_permanent_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_params->smram_base); + return smm_load_module((void *)relo_params->smram_base, + relo_params->smram_size, &smm_params); +} + +static int cpu_smm_setup(void) +{ + device_t dev; + int num_cpus; + msr_t msr; + + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + fill_in_relocation_params(dev, &smm_reloc_params); + + setup_ied_area(&smm_reloc_params); + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_cpus = msr.lo & 0xffff; + if (num_cpus > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); + } + + if (install_relocation_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); + return -1; + } + + if (install_permanent_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + /* TODO(adurbin): Is this really needed? */ + wbinvd(); + + return 0; +} + +void smm_init(void) +{ + /* Return early if CPU SMM setup failed. */ + if (cpu_smm_setup()) + return; + + southbridge_smm_init(); + + /* Initiate first SMI to kick off SMM-context relocation. Note: this + * SMI being triggered here queues up an SMI in the APs which are in + * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI + * at the SMM_DEFAULT_BASE before jumping to startup vector. */ + southbridge_trigger_smi(); + + printk(BIOS_DEBUG, "Relocation complete.\n"); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 0ff7149..8feaa4d 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -36,8 +36,6 @@ #include "../../../southbridge/intel/i82801dx/i82801dx.h" #elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X -#include "../../../southbridge/intel/fsp_bd82x6x/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX #include "../../../southbridge/intel/i82801ix/i82801ix.h" #else @@ -45,12 +43,7 @@ #endif #if CONFIG_SMM_TSEG - -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else -#error "Northbridge must define TSEG_BAR." +#error "Don't use this file with TSEG." #endif #include <cpu/x86/mtrr.h> diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index 95831a5..6d4f83c 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -102,6 +102,7 @@ #define TOM 0xa0 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 73e11e8..1d92532 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -42,7 +42,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_fsp_bd82x6x_config config_t; @@ -405,58 +404,20 @@ static void enable_hpet(void) RCBA32(HPTC) = reg32; } -#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(struct device *dev) +static void pch_set_acpi_mode(void) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - - if (!acpi_is_wakeup_s3()) { + if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); // Enable ACPI mode + outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode printk(BIOS_DEBUG, "done.\n"); #else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); // Disable ACPI mode + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); #endif } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } -#endif static void pch_disable_smm_only_flashing(struct device *dev) { @@ -541,9 +502,7 @@ static void lpc_init(struct device *dev) pch_disable_smm_only_flashing(dev); -#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif + pch_set_acpi_mode(); pch_fixups(dev); } diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 9e3b4da..10e536e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -64,6 +64,11 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) && !defined(__SMM__) #include "chip.h" +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); + int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index bb0be47..2374f5f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -29,13 +29,6 @@ #include <string.h> #include "pch.h" -#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" -#endif - -extern unsigned char _binary_smm_start; -extern unsigned char _binary_smm_size; - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -231,15 +224,18 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); } -extern uint8_t smm_relocation_start, smm_relocation_end; - -static void smm_relocate(void) +void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; - printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_ELOG + /* Log events from chipset before clearing */ + pch_log_state(); +#endif + + printk(BIOS_DEBUG, "Initializing southbridge SMI..."); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; @@ -252,10 +248,6 @@ static void smm_relocate(void) return; } - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); @@ -304,7 +296,10 @@ static void smm_relocate(void) smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); +} +void southbridge_trigger_smi(void) +{ /** * There are several methods of raising a controlled SMI# via * software, among them: @@ -323,76 +318,16 @@ static void smm_relocate(void) outb(0x00, 0xb2); } -static int smm_handler_copied = 0; - -static void smm_install(void) +void southbridge_clear_smi_status(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - u32 smm_base = 0xa0000; - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = IED_SIZE, - .reserved = {0}, - }; - - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - /* enable the SMM memory window */ - pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); - -#if CONFIG_SMM_TSEG - smm_base = pci_read_config32(dev, TSEG) & ~1; -#endif - - /* copy the real SMM handler */ - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); - memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size); - - /* copy the IED header into place */ - if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { - /* Top of TSEG region */ - smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; - printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); - memcpy((void *)smm_base, &ied, sizeof(ied)); - } - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) -{ -#if CONFIG_ELOG - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - /* Put SMM code to 0xa0000 */ - smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + /* Clear SMI status */ + reset_smi_status(); + + /* Clear PM1 status */ + reset_pm1_status(); + + /* Set EOS bit so other SMIs can occur. */ + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 0648ce3..96de457 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -51,28 +51,12 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { return gnvs; } -#if CONFIG_SMM_TSEG -static u32 tseg_base = 0; -u32 smi_get_tseg_base(void) -{ - if (!tseg_base) - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; - return tseg_base; -} -void tseg_relocate(void **ptr) -{ - /* Adjust pointer with TSEG base */ - if (*ptr && *ptr < (void*)smi_get_tseg_base()) - *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); -} -#endif - /** * @brief read and clear PM1_STS * @return PM1_STS register @@ -323,7 +307,7 @@ static void southbridge_gate_memory_reset(void) outl(reg32, gpiobase + GP_LVL2); } -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_sleep(void) { u8 reg8; u32 reg32; @@ -338,8 +322,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outb(tmp70, 0x70); outb(tmp72, 0x72); - void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; - /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); reg8 &= ~SLP_SMI_EN; @@ -351,8 +333,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat slp_typ = (reg32 >> 10) & 7; /* Do any mainboard sleep handling */ - tseg_relocate((void **)&mainboard_sleep); - mainboard_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -428,13 +409,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; - u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00; int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = (em64t101_smm_state_save_area_t *) - (base - (node * 0x400)); + state = smm_get_save_state(node); /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) @@ -481,11 +460,10 @@ static void southbridge_smi_gsmi(void) } #endif -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_apmc(void) { u32 pmctrl; u8 reg8; - int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -538,11 +516,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state #endif } - tseg_relocate((void **)&mainboard_apmc); - mainboard_apmc(reg8); + mainboard_smi_apmc(reg8); } -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_pm1(void) { u16 pm1_sts; @@ -563,7 +540,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpe0(void) { u32 gpe0_sts; @@ -571,17 +548,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpi(void) { - void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - tseg_relocate((void **)&mainboard_gpi); - mainboard_gpi(reg16); + mainboard_smi_gpi(reg16); if (reg16) printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); @@ -589,7 +564,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_mc(void) { u32 reg32; @@ -604,7 +579,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_tco(void) { u32 tco_sts; @@ -641,7 +616,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_periodic(void) { u32 reg32; @@ -654,7 +629,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s printk(BIOS_DEBUG, "Periodic SMI.\n"); } -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -708,8 +683,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); +typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved @@ -753,7 +727,7 @@ static smi_handler_t southbridge_smi[32] = { * @param state_save */ -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { int i, dump = 0; u32 smi_sts; @@ -770,15 +744,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) { -#if CONFIG_SMM_TSEG - smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + - smi_get_tseg_base()); - if (handler) - handler(node, state_save); -#else - southbridge_smi[i](node, state_save); -#endif + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i);

1 0

New patch to review for coreboot: af5bd9e Migrate 2065x to SMM_MODULES
by Vladimir Serbinenko 28 May '15

28 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10352 -gerrit commit af5bd9e7f07a9ec088f98c7664b47578ce8cb31a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 20:42:32 2015 +0200 Migrate 2065x to SMM_MODULES This gets rid of ugly tseg_relocate for ibexpeak. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to ibexpeak. Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_2065x/Makefile.inc | 2 + src/cpu/intel/model_2065x/model_2065x.h | 1 + src/cpu/intel/model_2065x/smmrelocate.c | 293 ++++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 7 - src/southbridge/intel/ibexpeak/lpc.c | 51 +---- src/southbridge/intel/ibexpeak/pch.h | 5 + src/southbridge/intel/ibexpeak/smi.c | 103 ++-------- src/southbridge/intel/ibexpeak/smihandler.c | 68 ++----- 9 files changed, 343 insertions(+), 188 deletions(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 4a85f09..946825b 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG + select SMM_MODULES select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index c21a4b5..77b2f02 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -20,3 +20,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 03fcf68..0ea7a54 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -95,6 +95,7 @@ void intel_model_2065x_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +void smm_relocate(void); #endif #endif diff --git a/src/cpu/intel/model_2065x/smmrelocate.c b/src/cpu/intel/model_2065x/smmrelocate.c new file mode 100644 index 0000000..94811c3 --- /dev/null +++ b/src/cpu/intel/model_2065x/smmrelocate.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include "model_2065x.h" + +#define CORE_THREAD_COUNT_MSR 0x35 + +#define SMRR_SUPPORTED (1<<11) + +struct smm_relocation_params { + u32 smram_base; + u32 smram_size; + u32 ied_base; + u32 ied_size; + msr_t smrr_base; + msr_t smrr_mask; +}; + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); + wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void asmlinkage cpu_smm_do_relocation(void *arg) +{ + em64t101_smm_state_save_area_t *save_state; + msr_t mtrr_cap; + struct smm_relocation_params *relo_params; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + relo_params = p->arg; + cpu = p->cpu; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* All threads need to set IEDBASE and SMBASE in the save state area. + * Since one thread runs at a time during the relocation the save state + * is the same for all cpus. */ + save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - + runtime->save_state_size); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + save_state->smbase = relo_params->smram_base - + cpu * runtime->save_state_size; + save_state->iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRRcap_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); + + southbridge_clear_smi_status(); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + u32 tseg_size; + u32 tsegmb; + u32 bgsm; + int phys_bits; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + /* Some of the range registers are dependent on the number of physical + * address bits supported. */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + /* The range bounded by the TSEGMB and BGSM registers encompasses the + * SMRAM range as well as the IED range. However, the SMRAM available + * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. + */ + tsegmb = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + bgsm = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_GTT_BASE); + tseg_size = bgsm - tsegmb; + + params->smram_base = tsegmb; + params->smram_size = 4 << 20; + params->ied_base = tsegmb + params->smram_size; + params->ied_size = tseg_size - params->smram_size; + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.hi = 0; +} + +static void make_apicid_map(int threads_per_package, int threads_per_core, struct smm_loader_params *relo_params) +{ + int i; + for (i = 0; i < threads_per_package; ++i) { + relo_params->runtime->apic_id_to_cpu[i] = (i % threads_per_core) + + ((i / threads_per_core) << 2); + } +} + +static int install_relocation_handler(int threads_per_package, int threads_per_core, + struct smm_relocation_params *relo_params) +{ + /* The default SMM entry happens serially at the default location. + * Therefore, there is only 1 concurrent save state area. Set the + * stack size to the save state size, and call into the + * do_relocation handler. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = threads_per_package, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = &cpu_smm_do_relocation, + .handler_arg = (void *)relo_params, + }; + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + make_apicid_map(threads_per_package, threads_per_core, &smm_params); + return 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); +} + +static int install_permanent_handler(int threads_per_package, int threads_per_core, + struct smm_relocation_params *relo_params) +{ + /* There are threads_per_package concurrent stacks and threads_per_package concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = threads_per_package, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = threads_per_package, + }; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_params->smram_base); + if (smm_load_module((void *)relo_params->smram_base, + relo_params->smram_size, &smm_params)) + return -1; + make_apicid_map(threads_per_package, threads_per_core, &smm_params); + return 0; +} + +static int cpu_smm_setup(void) +{ + device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); + struct cpuid_result result; + unsigned threads_per_package, threads_per_core; + + /* Logical processors (threads) per core */ + result = cpuid_ext(0xb, 0); + threads_per_core = result.ebx & 0xffff; + + /* Logical processors (threads) per package */ + result = cpuid_ext(0xb, 1); + threads_per_package = result.ebx & 0xffff; + + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + /* enable the SMM memory window */ + pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); + + fill_in_relocation_params(&smm_reloc_params); + + setup_ied_area(&smm_reloc_params); + + if (threads_per_package > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + threads_per_package, CONFIG_MAX_CPUS); + } + + if (install_relocation_handler(threads_per_package, threads_per_core, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); + return -1; + } + + if (install_permanent_handler(threads_per_package, threads_per_core, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + /* TODO(adurbin): Is this really needed? */ + wbinvd(); + + /* close the SMM memory window and enable normal SMM */ + pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG); + + return 0; +} + +void smm_init(void) +{ + /* Return early if CPU SMM setup failed. */ + if (cpu_smm_setup()) + return; + + southbridge_smm_init(); + + /* Initiate first SMI to kick off SMM-context relocation. Note: this + * SMI being triggered here queues up an SMI in the APs which are in + * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI + * at the SMM_DEFAULT_BASE before jumping to startup vector. */ + southbridge_trigger_smi(); + + printk(BIOS_DEBUG, "Relocation complete.\n"); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 3b29233..0ff7149 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -36,8 +36,6 @@ #include "../../../southbridge/intel/i82801dx/i82801dx.h" #elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK -#include "../../../southbridge/intel/bd82x6x/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X #include "../../../southbridge/intel/fsp_bd82x6x/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX @@ -48,17 +46,12 @@ #if CONFIG_SMM_TSEG -#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM -#include <northbridge/intel/nehalem/nehalem.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#else #if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE #include <northbridge/intel/fsp_sandybridge/northbridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #else #error "Northbridge must define TSEG_BAR." #endif -#endif #include <cpu/x86/mtrr.h> diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 550ef30..f066b35 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -43,7 +43,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_ibexpeak_config config_t; @@ -433,58 +432,20 @@ static void enable_clock_gating(device_t dev) RCBA32_OR(0x3564, 0x3); } -#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(struct device *dev) +static void pch_set_acpi_mode(void) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - - if (!acpi_is_wakeup_s3()) { + if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); // Enable ACPI mode + outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode printk(BIOS_DEBUG, "done.\n"); #else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); // Disable ACPI mode + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); #endif } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } -#endif static void pch_disable_smm_only_flashing(struct device *dev) { @@ -568,9 +529,7 @@ static void lpc_init(struct device *dev) pch_disable_smm_only_flashing(dev); -#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif + pch_set_acpi_mode(); pch_fixups(dev); } diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 72f2a5c..a73bb97 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,11 @@ void intel_pch_finalize_smm(void); #include "chip.h" void pch_enable(device_t dev); #endif +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); + int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 76da0d2..d1ec3f8 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -30,11 +30,6 @@ #include <string.h> #include "pch.h" -#include "northbridge/intel/nehalem/nehalem.h" - -extern unsigned char _binary_smm_start; -extern unsigned char _binary_smm_end; - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -230,15 +225,18 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); } -extern uint8_t smm_relocation_start, smm_relocation_end; - -static void smm_relocate(void) +void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; - printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_ELOG + /* Log events from chipset before clearing */ + pch_log_state(); +#endif + + printk(BIOS_DEBUG, "Initializing southbridge SMI..."); pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xff80; @@ -251,10 +249,6 @@ static void smm_relocate(void) return; } - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); @@ -303,7 +297,10 @@ static void smm_relocate(void) smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); +} +void southbridge_trigger_smi(void) +{ /** * There are several methods of raising a controlled SMI# via * software, among them: @@ -322,78 +319,16 @@ static void smm_relocate(void) outb(0x00, 0xb2); } -static int smm_handler_copied = 0; - -static void smm_install(void) -{ - device_t dev = PCI_DEV(0, 0, 0); - device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); - u32 smm_base = 0xa0000; - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = IED_SIZE, - .reserved = {0}, - }; - - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - /* enable the SMM memory window */ - pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); - -#if CONFIG_SMM_TSEG - smm_base = pci_read_config32(dev, TSEG) & ~1; -#endif - - /* copy the real SMM handler */ - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); - memcpy((void *)smm_base, &_binary_smm_start, - (size_t)(&_binary_smm_end - &_binary_smm_start)); - - /* copy the IED header into place */ - if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { - /* Top of TSEG region */ - smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; - printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); - memcpy((void *)smm_base, &ied, sizeof(ied)); - } - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) +void southbridge_clear_smi_status(void) { -#if CONFIG_ELOG - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - /* Put SMM code to 0xa0000 */ - smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + /* Clear SMI status */ + reset_smi_status(); + + /* Clear PM1 status */ + reset_pm1_status(); + + /* Set EOS bit so other SMIs can occur. */ + smi_set_eos(); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 2110169..6e1ee83 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -52,28 +52,12 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { return gnvs; } -#if CONFIG_SMM_TSEG -static u32 tseg_base = 0; -u32 smi_get_tseg_base(void) -{ - if (!tseg_base) - tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; - return tseg_base; -} -void tseg_relocate(void **ptr) -{ - /* Adjust pointer with TSEG base */ - if (*ptr && *ptr < (void*)smi_get_tseg_base()) - *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); -} -#endif - static void alt_gpi_mask(u16 clr, u16 set) { u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); @@ -422,7 +406,7 @@ static void xhci_sleep(u8 slp_typ) } -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_sleep(void) { u8 reg8; u32 reg32; @@ -437,8 +421,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outb(tmp70, 0x70); outb(tmp72, 0x72); - void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; - /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); reg8 &= ~SLP_SMI_EN; @@ -453,8 +435,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat xhci_sleep(slp_typ); /* Do any mainboard sleep handling */ - tseg_relocate((void **)&mainboard_sleep); - mainboard_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -530,13 +511,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; - u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET; int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = (em64t101_smm_state_save_area_t *) - (base - (node * 0x400)); + state = smm_get_save_state(node); /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) @@ -583,11 +562,10 @@ static void southbridge_smi_gsmi(void) } #endif -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_apmc(void) { u32 pmctrl; u8 reg8; - int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -640,11 +618,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state #endif } - tseg_relocate((void **)&mainboard_apmc); - mainboard_apmc(reg8); + mainboard_smi_apmc(reg8); } -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_pm1(void) { u16 pm1_sts; @@ -665,7 +642,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpe0(void) { u32 gpe0_sts; @@ -673,17 +650,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpi(void) { - void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - tseg_relocate((void **)&mainboard_gpi); - mainboard_gpi(reg16); + mainboard_smi_gpi(reg16); if (reg16) printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); @@ -691,7 +666,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_mc(void) { u32 reg32; @@ -706,7 +681,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_tco(void) { u32 tco_sts; @@ -743,7 +718,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_periodic(void) { u32 reg32; @@ -756,7 +731,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s printk(BIOS_DEBUG, "Periodic SMI.\n"); } -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -810,8 +785,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); +typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved @@ -853,7 +827,7 @@ static smi_handler_t southbridge_smi[32] = { * @param node * @param state_save */ -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { int i, dump = 0; u32 smi_sts; @@ -870,15 +844,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) { -#if CONFIG_SMM_TSEG - smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + - smi_get_tseg_base()); - if (handler) - handler(node, state_save); -#else - southbridge_smi[i](node, state_save); -#endif + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i);

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Patch merged into coreboot/master: a3e41c0 Migrate 206ax to SMM_MODULES
by gerrit＠coreboot.org 28 May '15

28 May '15

the following patch was just integrated into master: commit a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 28 16:04:17 2015 +0200 Migrate 206ax to SMM_MODULES This gets rid of ugly tseg_relocate for bd82x6x. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x. Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10351 for details. -gerrit

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coreboot-gerrit May 2015