Patch set updated for coreboot: c23871d Migrate 206ax to SMM_MODULES
by Vladimir Serbinenko 28 May '15
by Vladimir Serbinenko 28 May '15
28 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10351
-gerrit
commit c23871d8626a5967287992d73c2d59671ea8287d
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 28 16:04:17 2015 +0200
Migrate 206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for bd82x6x.
This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x.
Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/cpu/intel/model_206ax/Kconfig | 1 +
src/cpu/intel/model_206ax/Makefile.inc | 2 +
src/cpu/intel/model_206ax/model_206ax.h | 1 +
src/cpu/intel/model_206ax/smmrelocate.c | 333 ++++++++++++++++++++++++
src/cpu/x86/smm/smmrelocate.S | 7 +-
src/northbridge/intel/sandybridge/sandybridge.h | 1 +
src/southbridge/intel/bd82x6x/lpc.c | 51 +---
src/southbridge/intel/bd82x6x/pch.h | 5 +
src/southbridge/intel/bd82x6x/smi.c | 99 ++-----
src/southbridge/intel/bd82x6x/smihandler.c | 72 ++---
10 files changed, 385 insertions(+), 187 deletions(-)
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 490849b..1ecc911 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
+ select SMM_MODULES
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 32a5eff..c296fd9 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,3 +8,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 6b23750..671f359 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -103,6 +103,7 @@ void intel_model_206ax_finalize_smm(void);
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
+void smm_relocate(void);
#endif
#endif
diff --git a/src/cpu/intel/model_206ax/smmrelocate.c b/src/cpu/intel/model_206ax/smmrelocate.c
new file mode 100644
index 0000000..587fee9
--- /dev/null
+++ b/src/cpu/intel/model_206ax/smmrelocate.c
@@ -0,0 +1,333 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "model_206ax.h"
+
+#define EMRRphysBase_MSR 0x1f4
+#define EMRRphysMask_MSR 0x1f5
+#define UNCORE_EMRRphysBase_MSR 0x2f4
+#define UNCORE_EMRRphysMask_MSR 0x2f5
+
+#define CORE_THREAD_COUNT_MSR 0x35
+
+#define SMRR_SUPPORTED (1<<11)
+#define EMRR_SUPPORTED (1<<12)
+
+struct smm_relocation_params {
+ u32 smram_base;
+ u32 smram_size;
+ u32 ied_base;
+ u32 ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t emrr_base;
+ msr_t emrr_mask;
+ msr_t uncore_emrr_base;
+ msr_t uncore_emrr_mask;
+};
+
+/* This gets filled in and used during relocation. */
+static struct smm_relocation_params smm_reloc_params;
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
+ wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+}
+
+static inline void write_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
+ wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
+ wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
+}
+
+static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_emrr_base.lo,
+ relo_params->uncore_emrr_mask.lo);
+ wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
+ wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
+}
+
+/* The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here. */
+static void asmlinkage cpu_smm_do_relocation(void *arg)
+{
+ em64t101_smm_state_save_area_t *save_state;
+ msr_t mtrr_cap;
+ struct smm_relocation_params *relo_params;
+ const struct smm_module_params *p;
+ const struct smm_runtime *runtime;
+ int cpu;
+
+ p = arg;
+ runtime = p->runtime;
+ relo_params = p->arg;
+ cpu = p->cpu;
+
+ if (cpu >= CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Invalid CPU number assigned in SMM stub: %d\n", cpu);
+ return;
+ }
+
+ printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+
+ /* All threads need to set IEDBASE and SMBASE in the save state area.
+ * Since one thread runs at a time during the relocation the save state
+ * is the same for all cpus. */
+ save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
+ runtime->save_state_size);
+
+ /* The relocated handler runs with all CPUs concurrently. Therefore
+ * stagger the entry points adjusting SMBASE downwards by save state
+ * size * CPU num. */
+ save_state->smbase = relo_params->smram_base -
+ cpu * runtime->save_state_size;
+ save_state->iedbase = relo_params->ied_base;
+
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
+ save_state->smbase, save_state->iedbase, save_state);
+
+ /* Write EMRR and SMRR MSRs based on indicated support. */
+ mtrr_cap = rdmsr(MTRRcap_MSR);
+ if (mtrr_cap.lo & SMRR_SUPPORTED)
+ write_smrr(relo_params);
+
+ if (mtrr_cap.lo & EMRR_SUPPORTED) {
+ write_emrr(relo_params);
+ /* UNCORE_EMRR msrs are package level. Therefore, only
+ * configure these MSRs on the BSP. */
+ if (cpu == 0)
+ write_uncore_emrr(relo_params);
+ }
+
+ southbridge_clear_smi_status();
+}
+
+static u32 northbridge_get_base_reg(device_t dev, int reg)
+{
+ u32 value;
+
+ value = pci_read_config32(dev, reg);
+ /* Base registers are at 1MiB granularity. */
+ value &= ~((1 << 20) - 1);
+ return value;
+}
+
+static void fill_in_relocation_params(device_t dev,
+ struct smm_relocation_params *params)
+{
+ u32 tseg_size;
+ u32 tsegmb;
+ u32 bgsm;
+ u32 emrr_base;
+ u32 emrr_size;
+ int phys_bits;
+ /* All range registers are aligned to 4KiB */
+ const u32 rmask = ~((1 << 12) - 1);
+
+ /* Some of the range registers are dependent on the number of physical
+ * address bits supported. */
+ phys_bits = cpuid_eax(0x80000008) & 0xff;
+
+ /* The range bounded by the TSEGMB and BGSM registers encompasses the
+ * SMRAM range as well as the IED range. However, the SMRAM available
+ * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
+ */
+ tsegmb = northbridge_get_base_reg(dev, TSEG);
+ bgsm = northbridge_get_base_reg(dev, BGSM);
+ tseg_size = bgsm - tsegmb;
+
+ params->smram_base = tsegmb;
+ params->smram_size = 4 << 20;
+ params->ied_base = tsegmb + params->smram_size;
+ params->ied_size = tseg_size - params->smram_size;
+
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.hi = 0;
+
+ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
+ emrr_base = (params->ied_base + (2 << 20)) & rmask;
+ emrr_size = params->ied_size - (2 << 20);
+
+ /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
+ * on the number of physical address bits supported. */
+ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
+ params->emrr_base.hi = 0;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
+ params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
+
+ /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
+ params->uncore_emrr_base.lo = emrr_base;
+ params->uncore_emrr_base.hi = 0;
+ params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
+ MTRRphysMaskValid;
+ params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
+}
+
+static int install_relocation_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* The default SMM entry happens serially at the default location.
+ * Therefore, there is only 1 concurrent save state area. Set the
+ * stack size to the save state size, and call into the
+ * do_relocation handler. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = 1,
+ .handler = &cpu_smm_do_relocation,
+ .handler_arg = (void *)relo_params,
+ };
+
+ return smm_setup_relocation_handler(&smm_params);
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+ char *ied_base;
+
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = params->ied_size,
+ .reserved = {0},
+ };
+
+ ied_base = (void *)params->ied_base;
+
+ /* Place IED header at IEDBASE. */
+ memcpy(ied_base, &ied, sizeof(ied));
+
+ /* Zero out 32KiB at IEDBASE + 1MiB */
+ memset(ied_base + (1 << 20), 0, (32 << 10));
+}
+
+static int install_permanent_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* There are num_cpus concurrent stacks and num_cpus concurrent save
+ * state areas. Lastly, set the stack size to the save state size. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = num_cpus,
+ };
+
+ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
+ relo_params->smram_base);
+ return smm_load_module((void *)relo_params->smram_base,
+ relo_params->smram_size, &smm_params);
+}
+
+static int cpu_smm_setup(void)
+{
+ device_t dev;
+ int num_cpus;
+ msr_t msr;
+
+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ fill_in_relocation_params(dev, &smm_reloc_params);
+
+ setup_ied_area(&smm_reloc_params);
+
+ msr = rdmsr(CORE_THREAD_COUNT_MSR);
+ num_cpus = msr.lo & 0xffff;
+ if (num_cpus > CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
+ num_cpus, CONFIG_MAX_CPUS);
+ }
+
+ if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
+ return -1;
+ }
+
+ if (install_permanent_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
+ return -1;
+ }
+
+ /* Ensure the SMM handlers hit DRAM before performing first SMI. */
+ /* TODO(adurbin): Is this really needed? */
+ wbinvd();
+
+ return 0;
+}
+
+void smm_init(void)
+{
+ /* Return early if CPU SMM setup failed. */
+ if (cpu_smm_setup())
+ return;
+
+ southbridge_smm_init();
+
+ /* Initiate first SMI to kick off SMM-context relocation. Note: this
+ * SMI being triggered here queues up an SMI in the APs which are in
+ * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
+ * at the SMM_DEFAULT_BASE before jumping to startup vector. */
+ southbridge_trigger_smi();
+
+ printk(BIOS_DEBUG, "Relocation complete.\n");
+
+ /* Lock down the SMRAM space. */
+ smm_lock();
+}
+
+void smm_lock(void)
+{
+ /* LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+ D_LCK | G_SMRAME | C_BASE_SEG);
+}
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 79ef156..3b29233 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -36,7 +36,7 @@
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
#include "../../../southbridge/intel/sch/sch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
+#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
#include "../../../southbridge/intel/bd82x6x/pch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
@@ -48,10 +48,7 @@
#if CONFIG_SMM_TSEG
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
+#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM
#include <northbridge/intel/nehalem/nehalem.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6be14b8..09894f7 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -99,6 +99,7 @@
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
#define TSEG 0xb8 /* TSEG base */
#define TOLUD 0xbc /* Top of Low Used Memory */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 19e5407..842d9d9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -43,7 +43,6 @@
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
-#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -427,58 +426,20 @@ static void enable_clock_gating(device_t dev)
RCBA32_OR(0x3564, 0x3);
}
-#if CONFIG_HAVE_SMI_HANDLER
-static void pch_lock_smm(struct device *dev)
+static void pch_set_acpi_mode(void)
{
-#if TEST_SMM_FLASH_LOCKDOWN
- u8 reg8;
-#endif
-
- if (!acpi_is_wakeup_s3()) {
+ if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
- outb(0xe1, 0xb2); // Enable ACPI mode
+ outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(0x1e, 0xb2); // Disable ACPI mode
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#endif
}
-
- /* Don't allow evil boot loaders, kernels, or
- * userspace applications to deceive us:
- */
- smm_lock();
-
-#if TEST_SMM_FLASH_LOCKDOWN
- /* Now try this: */
- printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
- reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
- printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
-
- printk(BIOS_DEBUG, "Writing:\n");
- *(volatile u8 *)0xfff00000 = 0x00;
- printk(BIOS_DEBUG, "Testing:\n");
- reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
-
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- printk(BIOS_DEBUG, "Done.\n");
-#endif
}
-#endif
static void pch_disable_smm_only_flashing(struct device *dev)
{
@@ -572,9 +533,7 @@ static void lpc_init(struct device *dev)
pch_disable_smm_only_flashing(dev);
-#if CONFIG_HAVE_SMI_HANDLER
- pch_lock_smm(dev);
-#endif
+ pch_set_acpi_mode();
pch_fixups(dev);
}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3ce5d63..950dbc4 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,6 +66,11 @@ void intel_pch_finalize_smm(void);
#include "chip.h"
void pch_enable(device_t dev);
#endif
+/* These helpers are for performing SMM relocation. */
+void southbridge_smm_init(void);
+void southbridge_trigger_smi(void);
+void southbridge_clear_smi_status(void);
+
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index b60c364..59a9c01 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -28,10 +28,6 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include "pch.h"
-#include "northbridge/intel/sandybridge/sandybridge.h"
-
-extern unsigned char _binary_smm_start;
-extern unsigned char _binary_smm_end;
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@@ -228,15 +224,18 @@ static void smi_set_eos(void)
outb(reg8, pmbase + SMI_EN);
}
-extern uint8_t smm_relocation_start, smm_relocation_end;
-
-static void smm_relocate(void)
+void southbridge_smm_init(void)
{
u32 smi_en;
u16 pm1_en;
u32 gpe0_en;
- printk(BIOS_DEBUG, "Initializing SMM handler...");
+#if CONFIG_ELOG
+ /* Log events from chipset before clearing */
+ pch_log_state();
+#endif
+
+ printk(BIOS_DEBUG, "Initializing southbridge SMI...");
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
@@ -249,10 +248,6 @@ static void smm_relocate(void)
return;
}
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
-
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
@@ -301,7 +296,10 @@ static void smm_relocate(void)
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+}
+void southbridge_trigger_smi(void)
+{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@@ -320,79 +318,18 @@ static void smm_relocate(void)
outb(0x00, 0xb2);
}
-static int smm_handler_copied = 0;
-
-static void smm_install(void)
+void southbridge_clear_smi_status(void)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- u32 smm_base = 0xa0000;
- struct ied_header ied = {
- .signature = "INTEL RSVD",
- .size = IED_SIZE,
- .reserved = {0},
- };
-
- /* The first CPU running this gets to copy the SMM handler. But not all
- * of them.
- */
- if (smm_handler_copied)
- return;
- smm_handler_copied = 1;
-
- /* enable the SMM memory window */
- pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
-
-#if CONFIG_SMM_TSEG
- smm_base = pci_read_config32(dev, TSEG) & ~1;
-#endif
-
- /* copy the real SMM handler */
- printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
- memcpy((void *)smm_base, &_binary_smm_start,
- (size_t)(&_binary_smm_end - &_binary_smm_start));
-
- /* copy the IED header into place */
- if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
- /* Top of TSEG region */
- smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
- printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
- smm_base);
- memcpy((void *)smm_base, &ied, sizeof(ied));
- }
- wbinvd();
-
- /* close the SMM memory window and enable normal SMM */
- pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
-{
-#if CONFIG_ELOG
- /* Log events from chipset before clearing */
- pch_log_state();
-#endif
-
- /* Put SMM code to 0xa0000 */
- smm_install();
-
- /* Put relocation code to 0x38000 and relocate SMBASE */
- smm_relocate();
-
- /* We're done. Make sure SMIs can happen! */
+ /* Clear SMI status */
+ reset_smi_status();
+
+ /* Clear PM1 status */
+ reset_pm1_status();
+
+ /* Set EOS bit so other SMIs can occur. */
smi_set_eos();
}
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 3593c47..d9d63b7 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -31,10 +31,6 @@
#include "nvs.h"
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/pci_mmio_cfg.h>
#include <southbridge/intel/bd82x6x/me.h>
@@ -54,28 +50,12 @@ static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+static global_nvs_t *gnvs;
global_nvs_t *smm_get_gnvs(void)
{
return gnvs;
}
-#if CONFIG_SMM_TSEG
-static u32 tseg_base = 0;
-u32 smi_get_tseg_base(void)
-{
- if (!tseg_base)
- tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
- return tseg_base;
-}
-void tseg_relocate(void **ptr)
-{
- /* Adjust pointer with TSEG base */
- if (*ptr && *ptr < (void*)smi_get_tseg_base())
- *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
-}
-#endif
-
static void alt_gpi_mask(u16 clr, u16 set)
{
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
@@ -424,7 +404,7 @@ static void xhci_sleep(u8 slp_typ)
}
-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_sleep(void)
{
u8 reg8;
u32 reg32;
@@ -439,8 +419,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outb(tmp70, 0x70);
outb(tmp72, 0x72);
- void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
-
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
reg8 &= ~SLP_SMI_EN;
@@ -455,8 +433,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
xhci_sleep(slp_typ);
/* Do any mainboard sleep handling */
- tseg_relocate((void **)&mainboard_sleep);
- mainboard_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ-2);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
@@ -532,13 +509,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
{
em64t101_smm_state_save_area_t *state;
- u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
int node;
/* Check all nodes looking for the one that issued the IO */
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
- state = (em64t101_smm_state_save_area_t *)
- (base - (node * 0x400));
+ state = smm_get_save_state(node);
/* Check for Synchronous IO (bit0==1) */
if (!(state->io_misc_info & (1 << 0)))
@@ -587,11 +562,10 @@ static void southbridge_smi_gsmi(void)
static int mainboard_finalized = 0;
-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
- int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -657,11 +631,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
#endif
}
- tseg_relocate((void **)&mainboard_apmc);
- mainboard_apmc(reg8);
+ mainboard_smi_apmc(reg8);
}
-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
@@ -682,7 +655,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
@@ -690,17 +663,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
dump_gpe0_status(gpe0_sts);
}
-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpi(void)
{
- void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
- tseg_relocate((void **)&mainboard_gpi);
- mainboard_gpi(reg16);
+ mainboard_smi_gpi(reg16);
if (reg16)
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
@@ -708,7 +679,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
outw(reg16, pmbase + ALT_GP_SMI_STS);
}
-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_mc(void)
{
u32 reg32;
@@ -723,7 +694,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_tco(void)
{
u32 tco_sts;
@@ -760,7 +731,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_periodic(void)
{
u32 reg32;
@@ -773,7 +744,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
printk(BIOS_DEBUG, "Periodic SMI.\n");
}
-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_sts, trap_cycle;
@@ -827,8 +798,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
#undef IOTRAP
}
-typedef void (*smi_handler_t)(unsigned int node,
- smm_state_save_area_t *state_save);
+typedef void (*smi_handler_t)(void);
static smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
@@ -870,7 +840,7 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+void southbridge_smi_handler(void)
{
int i, dump = 0;
u32 smi_sts;
@@ -887,15 +857,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
-#if CONFIG_SMM_TSEG
- smi_handler_t handler = (smi_handler_t)
- ((u8*)southbridge_smi[i] +
- smi_get_tseg_base());
- if (handler)
- handler(node, state_save);
-#else
- southbridge_smi[i](node, state_save);
-#endif
+ southbridge_smi[i]();
} else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);
1
0
Patch set updated for coreboot: 902aff1 Migrate 206ax to SMM_MODULES
by Vladimir Serbinenko 28 May '15
by Vladimir Serbinenko 28 May '15
28 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10351
-gerrit
commit 902aff1da7d4e1847a4714b231f083ef66b122a5
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 28 16:04:17 2015 +0200
Migrate 206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for bd82x6x.
This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x.
Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/cpu/intel/haswell/smmrelocate.c | 5 -
src/cpu/intel/model_206ax/Kconfig | 1 +
src/cpu/intel/model_206ax/Makefile.inc | 2 +
src/cpu/intel/model_206ax/model_206ax.h | 1 +
src/cpu/intel/model_206ax/smmrelocate.c | 338 ++++++++++++++++++++++++
src/cpu/x86/smm/smmrelocate.S | 7 +-
src/northbridge/intel/sandybridge/sandybridge.h | 1 +
src/southbridge/intel/bd82x6x/lpc.c | 51 +---
src/southbridge/intel/bd82x6x/pch.h | 5 +
src/southbridge/intel/bd82x6x/smi.c | 99 ++-----
src/southbridge/intel/bd82x6x/smihandler.c | 72 ++---
11 files changed, 390 insertions(+), 192 deletions(-)
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index ab94f9a..37546e5 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -354,11 +354,6 @@ static void setup_ied_area(struct smm_relocation_params *params)
/* Zero out 32KiB at IEDBASE + 1MiB */
memset(ied_base + (1 << 20), 0, (32 << 10));
-
- /* According to the BWG MP init section 2MiB of memory at IEDBASE +
- * 2MiB should be zeroed as well. However, I suspect what is intended
- * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
- //memset(ied_base + (2 << 20), 0, (2 << 20));
}
static int install_permanent_handler(int num_cpus,
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 490849b..1ecc911 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
+ select SMM_MODULES
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 32a5eff..c296fd9 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,3 +8,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 6b23750..671f359 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -103,6 +103,7 @@ void intel_model_206ax_finalize_smm(void);
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
+void smm_relocate(void);
#endif
#endif
diff --git a/src/cpu/intel/model_206ax/smmrelocate.c b/src/cpu/intel/model_206ax/smmrelocate.c
new file mode 100644
index 0000000..b20370d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/smmrelocate.c
@@ -0,0 +1,338 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "model_206ax.h"
+
+#define EMRRphysBase_MSR 0x1f4
+#define EMRRphysMask_MSR 0x1f5
+#define UNCORE_EMRRphysBase_MSR 0x2f4
+#define UNCORE_EMRRphysMask_MSR 0x2f5
+
+#define CORE_THREAD_COUNT_MSR 0x35
+
+#define SMRR_SUPPORTED (1<<11)
+#define EMRR_SUPPORTED (1<<12)
+
+struct smm_relocation_params {
+ u32 smram_base;
+ u32 smram_size;
+ u32 ied_base;
+ u32 ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t emrr_base;
+ msr_t emrr_mask;
+ msr_t uncore_emrr_base;
+ msr_t uncore_emrr_mask;
+};
+
+/* This gets filled in and used during relocation. */
+static struct smm_relocation_params smm_reloc_params;
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
+ wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+}
+
+static inline void write_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
+ wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
+ wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
+}
+
+static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_emrr_base.lo,
+ relo_params->uncore_emrr_mask.lo);
+ wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
+ wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
+}
+
+/* The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here. */
+static void asmlinkage cpu_smm_do_relocation(void *arg)
+{
+ em64t101_smm_state_save_area_t *save_state;
+ msr_t mtrr_cap;
+ struct smm_relocation_params *relo_params;
+ const struct smm_module_params *p;
+ const struct smm_runtime *runtime;
+ int cpu;
+
+ p = arg;
+ runtime = p->runtime;
+ relo_params = p->arg;
+ cpu = p->cpu;
+
+ if (cpu >= CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Invalid CPU number assigned in SMM stub: %d\n", cpu);
+ return;
+ }
+
+ printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+
+ /* All threads need to set IEDBASE and SMBASE in the save state area.
+ * Since one thread runs at a time during the relocation the save state
+ * is the same for all cpus. */
+ save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
+ runtime->save_state_size);
+
+ /* The relocated handler runs with all CPUs concurrently. Therefore
+ * stagger the entry points adjusting SMBASE downwards by save state
+ * size * CPU num. */
+ save_state->smbase = relo_params->smram_base -
+ cpu * runtime->save_state_size;
+ save_state->iedbase = relo_params->ied_base;
+
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
+ save_state->smbase, save_state->iedbase, save_state);
+
+ /* Write EMRR and SMRR MSRs based on indicated support. */
+ mtrr_cap = rdmsr(MTRRcap_MSR);
+ if (mtrr_cap.lo & SMRR_SUPPORTED)
+ write_smrr(relo_params);
+
+ if (mtrr_cap.lo & EMRR_SUPPORTED) {
+ write_emrr(relo_params);
+ /* UNCORE_EMRR msrs are package level. Therefore, only
+ * configure these MSRs on the BSP. */
+ if (cpu == 0)
+ write_uncore_emrr(relo_params);
+ }
+
+ southbridge_clear_smi_status();
+}
+
+static u32 northbridge_get_base_reg(device_t dev, int reg)
+{
+ u32 value;
+
+ value = pci_read_config32(dev, reg);
+ /* Base registers are at 1MiB granularity. */
+ value &= ~((1 << 20) - 1);
+ return value;
+}
+
+static void fill_in_relocation_params(device_t dev,
+ struct smm_relocation_params *params)
+{
+ u32 tseg_size;
+ u32 tsegmb;
+ u32 bgsm;
+ u32 emrr_base;
+ u32 emrr_size;
+ int phys_bits;
+ /* All range registers are aligned to 4KiB */
+ const u32 rmask = ~((1 << 12) - 1);
+
+ /* Some of the range registers are dependent on the number of physical
+ * address bits supported. */
+ phys_bits = cpuid_eax(0x80000008) & 0xff;
+
+ /* The range bounded by the TSEGMB and BGSM registers encompasses the
+ * SMRAM range as well as the IED range. However, the SMRAM available
+ * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
+ */
+ tsegmb = northbridge_get_base_reg(dev, TSEG);
+ bgsm = northbridge_get_base_reg(dev, BGSM);
+ tseg_size = bgsm - tsegmb;
+
+ params->smram_base = tsegmb;
+ params->smram_size = 4 << 20;
+ params->ied_base = tsegmb + params->smram_size;
+ params->ied_size = tseg_size - params->smram_size;
+
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.hi = 0;
+
+ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
+ emrr_base = (params->ied_base + (2 << 20)) & rmask;
+ emrr_size = params->ied_size - (2 << 20);
+
+ /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
+ * on the number of physical address bits supported. */
+ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
+ params->emrr_base.hi = 0;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
+ params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
+
+ /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
+ params->uncore_emrr_base.lo = emrr_base;
+ params->uncore_emrr_base.hi = 0;
+ params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
+ MTRRphysMaskValid;
+ params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
+}
+
+static int install_relocation_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* The default SMM entry happens serially at the default location.
+ * Therefore, there is only 1 concurrent save state area. Set the
+ * stack size to the save state size, and call into the
+ * do_relocation handler. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = 1,
+ .handler = &cpu_smm_do_relocation,
+ .handler_arg = (void *)relo_params,
+ };
+
+ return smm_setup_relocation_handler(&smm_params);
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+ char *ied_base;
+
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = params->ied_size,
+ .reserved = {0},
+ };
+
+ ied_base = (void *)params->ied_base;
+
+ /* Place IED header at IEDBASE. */
+ memcpy(ied_base, &ied, sizeof(ied));
+
+ /* Zero out 32KiB at IEDBASE + 1MiB */
+ memset(ied_base + (1 << 20), 0, (32 << 10));
+
+ /* According to the BWG MP init section 2MiB of memory at IEDBASE +
+ * 2MiB should be zeroed as well. However, I suspect what is intended
+ * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
+ //memset(ied_base + (2 << 20), 0, (2 << 20));
+}
+
+static int install_permanent_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* There are num_cpus concurrent stacks and num_cpus concurrent save
+ * state areas. Lastly, set the stack size to the save state size. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = num_cpus,
+ };
+
+ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
+ relo_params->smram_base);
+ return smm_load_module((void *)relo_params->smram_base,
+ relo_params->smram_size, &smm_params);
+}
+
+static int cpu_smm_setup(void)
+{
+ device_t dev;
+ int num_cpus;
+ msr_t msr;
+
+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ fill_in_relocation_params(dev, &smm_reloc_params);
+
+ setup_ied_area(&smm_reloc_params);
+
+ msr = rdmsr(CORE_THREAD_COUNT_MSR);
+ num_cpus = msr.lo & 0xffff;
+ if (num_cpus > CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
+ num_cpus, CONFIG_MAX_CPUS);
+ }
+
+ if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
+ return -1;
+ }
+
+ if (install_permanent_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
+ return -1;
+ }
+
+ /* Ensure the SMM handlers hit DRAM before performing first SMI. */
+ /* TODO(adurbin): Is this really needed? */
+ wbinvd();
+
+ return 0;
+}
+
+void smm_init(void)
+{
+ /* Return early if CPU SMM setup failed. */
+ if (cpu_smm_setup())
+ return;
+
+ southbridge_smm_init();
+
+ /* Initiate first SMI to kick off SMM-context relocation. Note: this
+ * SMI being triggered here queues up an SMI in the APs which are in
+ * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
+ * at the SMM_DEFAULT_BASE before jumping to startup vector. */
+ southbridge_trigger_smi();
+
+ printk(BIOS_DEBUG, "Relocation complete.\n");
+
+ /* Lock down the SMRAM space. */
+ smm_lock();
+}
+
+void smm_lock(void)
+{
+ /* LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+ D_LCK | G_SMRAME | C_BASE_SEG);
+}
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 79ef156..3b29233 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -36,7 +36,7 @@
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
#include "../../../southbridge/intel/sch/sch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
+#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
#include "../../../southbridge/intel/bd82x6x/pch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
@@ -48,10 +48,7 @@
#if CONFIG_SMM_TSEG
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
+#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM
#include <northbridge/intel/nehalem/nehalem.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6be14b8..09894f7 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -99,6 +99,7 @@
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
#define TSEG 0xb8 /* TSEG base */
#define TOLUD 0xbc /* Top of Low Used Memory */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 19e5407..842d9d9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -43,7 +43,6 @@
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
-#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -427,58 +426,20 @@ static void enable_clock_gating(device_t dev)
RCBA32_OR(0x3564, 0x3);
}
-#if CONFIG_HAVE_SMI_HANDLER
-static void pch_lock_smm(struct device *dev)
+static void pch_set_acpi_mode(void)
{
-#if TEST_SMM_FLASH_LOCKDOWN
- u8 reg8;
-#endif
-
- if (!acpi_is_wakeup_s3()) {
+ if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
- outb(0xe1, 0xb2); // Enable ACPI mode
+ outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(0x1e, 0xb2); // Disable ACPI mode
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#endif
}
-
- /* Don't allow evil boot loaders, kernels, or
- * userspace applications to deceive us:
- */
- smm_lock();
-
-#if TEST_SMM_FLASH_LOCKDOWN
- /* Now try this: */
- printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
- reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
- printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
-
- printk(BIOS_DEBUG, "Writing:\n");
- *(volatile u8 *)0xfff00000 = 0x00;
- printk(BIOS_DEBUG, "Testing:\n");
- reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
-
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- printk(BIOS_DEBUG, "Done.\n");
-#endif
}
-#endif
static void pch_disable_smm_only_flashing(struct device *dev)
{
@@ -572,9 +533,7 @@ static void lpc_init(struct device *dev)
pch_disable_smm_only_flashing(dev);
-#if CONFIG_HAVE_SMI_HANDLER
- pch_lock_smm(dev);
-#endif
+ pch_set_acpi_mode();
pch_fixups(dev);
}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3ce5d63..950dbc4 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,6 +66,11 @@ void intel_pch_finalize_smm(void);
#include "chip.h"
void pch_enable(device_t dev);
#endif
+/* These helpers are for performing SMM relocation. */
+void southbridge_smm_init(void);
+void southbridge_trigger_smi(void);
+void southbridge_clear_smi_status(void);
+
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index b60c364..59a9c01 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -28,10 +28,6 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include "pch.h"
-#include "northbridge/intel/sandybridge/sandybridge.h"
-
-extern unsigned char _binary_smm_start;
-extern unsigned char _binary_smm_end;
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@@ -228,15 +224,18 @@ static void smi_set_eos(void)
outb(reg8, pmbase + SMI_EN);
}
-extern uint8_t smm_relocation_start, smm_relocation_end;
-
-static void smm_relocate(void)
+void southbridge_smm_init(void)
{
u32 smi_en;
u16 pm1_en;
u32 gpe0_en;
- printk(BIOS_DEBUG, "Initializing SMM handler...");
+#if CONFIG_ELOG
+ /* Log events from chipset before clearing */
+ pch_log_state();
+#endif
+
+ printk(BIOS_DEBUG, "Initializing southbridge SMI...");
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
@@ -249,10 +248,6 @@ static void smm_relocate(void)
return;
}
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
-
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
@@ -301,7 +296,10 @@ static void smm_relocate(void)
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+}
+void southbridge_trigger_smi(void)
+{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@@ -320,79 +318,18 @@ static void smm_relocate(void)
outb(0x00, 0xb2);
}
-static int smm_handler_copied = 0;
-
-static void smm_install(void)
+void southbridge_clear_smi_status(void)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- u32 smm_base = 0xa0000;
- struct ied_header ied = {
- .signature = "INTEL RSVD",
- .size = IED_SIZE,
- .reserved = {0},
- };
-
- /* The first CPU running this gets to copy the SMM handler. But not all
- * of them.
- */
- if (smm_handler_copied)
- return;
- smm_handler_copied = 1;
-
- /* enable the SMM memory window */
- pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
-
-#if CONFIG_SMM_TSEG
- smm_base = pci_read_config32(dev, TSEG) & ~1;
-#endif
-
- /* copy the real SMM handler */
- printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
- memcpy((void *)smm_base, &_binary_smm_start,
- (size_t)(&_binary_smm_end - &_binary_smm_start));
-
- /* copy the IED header into place */
- if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
- /* Top of TSEG region */
- smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
- printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
- smm_base);
- memcpy((void *)smm_base, &ied, sizeof(ied));
- }
- wbinvd();
-
- /* close the SMM memory window and enable normal SMM */
- pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
-{
-#if CONFIG_ELOG
- /* Log events from chipset before clearing */
- pch_log_state();
-#endif
-
- /* Put SMM code to 0xa0000 */
- smm_install();
-
- /* Put relocation code to 0x38000 and relocate SMBASE */
- smm_relocate();
-
- /* We're done. Make sure SMIs can happen! */
+ /* Clear SMI status */
+ reset_smi_status();
+
+ /* Clear PM1 status */
+ reset_pm1_status();
+
+ /* Set EOS bit so other SMIs can occur. */
smi_set_eos();
}
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 3593c47..d9d63b7 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -31,10 +31,6 @@
#include "nvs.h"
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/pci_mmio_cfg.h>
#include <southbridge/intel/bd82x6x/me.h>
@@ -54,28 +50,12 @@ static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+static global_nvs_t *gnvs;
global_nvs_t *smm_get_gnvs(void)
{
return gnvs;
}
-#if CONFIG_SMM_TSEG
-static u32 tseg_base = 0;
-u32 smi_get_tseg_base(void)
-{
- if (!tseg_base)
- tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
- return tseg_base;
-}
-void tseg_relocate(void **ptr)
-{
- /* Adjust pointer with TSEG base */
- if (*ptr && *ptr < (void*)smi_get_tseg_base())
- *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
-}
-#endif
-
static void alt_gpi_mask(u16 clr, u16 set)
{
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
@@ -424,7 +404,7 @@ static void xhci_sleep(u8 slp_typ)
}
-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_sleep(void)
{
u8 reg8;
u32 reg32;
@@ -439,8 +419,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outb(tmp70, 0x70);
outb(tmp72, 0x72);
- void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
-
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
reg8 &= ~SLP_SMI_EN;
@@ -455,8 +433,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
xhci_sleep(slp_typ);
/* Do any mainboard sleep handling */
- tseg_relocate((void **)&mainboard_sleep);
- mainboard_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ-2);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
@@ -532,13 +509,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
{
em64t101_smm_state_save_area_t *state;
- u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
int node;
/* Check all nodes looking for the one that issued the IO */
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
- state = (em64t101_smm_state_save_area_t *)
- (base - (node * 0x400));
+ state = smm_get_save_state(node);
/* Check for Synchronous IO (bit0==1) */
if (!(state->io_misc_info & (1 << 0)))
@@ -587,11 +562,10 @@ static void southbridge_smi_gsmi(void)
static int mainboard_finalized = 0;
-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
- int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -657,11 +631,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
#endif
}
- tseg_relocate((void **)&mainboard_apmc);
- mainboard_apmc(reg8);
+ mainboard_smi_apmc(reg8);
}
-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
@@ -682,7 +655,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
@@ -690,17 +663,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
dump_gpe0_status(gpe0_sts);
}
-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpi(void)
{
- void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
- tseg_relocate((void **)&mainboard_gpi);
- mainboard_gpi(reg16);
+ mainboard_smi_gpi(reg16);
if (reg16)
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
@@ -708,7 +679,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
outw(reg16, pmbase + ALT_GP_SMI_STS);
}
-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_mc(void)
{
u32 reg32;
@@ -723,7 +694,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_tco(void)
{
u32 tco_sts;
@@ -760,7 +731,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_periodic(void)
{
u32 reg32;
@@ -773,7 +744,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
printk(BIOS_DEBUG, "Periodic SMI.\n");
}
-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_sts, trap_cycle;
@@ -827,8 +798,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
#undef IOTRAP
}
-typedef void (*smi_handler_t)(unsigned int node,
- smm_state_save_area_t *state_save);
+typedef void (*smi_handler_t)(void);
static smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
@@ -870,7 +840,7 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+void southbridge_smi_handler(void)
{
int i, dump = 0;
u32 smi_sts;
@@ -887,15 +857,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
-#if CONFIG_SMM_TSEG
- smi_handler_t handler = (smi_handler_t)
- ((u8*)southbridge_smi[i] +
- smi_get_tseg_base());
- if (handler)
- handler(node, state_save);
-#else
- southbridge_smi[i](node, state_save);
-#endif
+ southbridge_smi[i]();
} else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);
1
0
New patch to review for coreboot: f0db339 Migrate 206ax to SMM_MODULES
by Vladimir Serbinenko 28 May '15
by Vladimir Serbinenko 28 May '15
28 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10351
-gerrit
commit f0db339187e743941526053fa1903b9acbc38af4
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 28 16:04:17 2015 +0200
Migrate 206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for bd82x6x.
This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x.
Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/cpu/intel/model_206ax/Kconfig | 1 +
src/cpu/intel/model_206ax/Makefile.inc | 2 +
src/cpu/intel/model_206ax/model_206ax.h | 1 +
src/cpu/intel/model_206ax/smmrelocate.c | 338 ++++++++++++++++++++++++
src/cpu/x86/smm/smmrelocate.S | 7 +-
src/northbridge/intel/sandybridge/sandybridge.h | 1 +
src/southbridge/intel/bd82x6x/lpc.c | 51 +---
src/southbridge/intel/bd82x6x/pch.h | 5 +
src/southbridge/intel/bd82x6x/smi.c | 99 ++-----
src/southbridge/intel/bd82x6x/smihandler.c | 72 ++---
10 files changed, 390 insertions(+), 187 deletions(-)
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 490849b..1ecc911 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
+ select SMM_MODULES
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 32a5eff..c296fd9 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -8,3 +8,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 6b23750..671f359 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -103,6 +103,7 @@ void intel_model_206ax_finalize_smm(void);
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
+void smm_relocate(void);
#endif
#endif
diff --git a/src/cpu/intel/model_206ax/smmrelocate.c b/src/cpu/intel/model_206ax/smmrelocate.c
new file mode 100644
index 0000000..b20370d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/smmrelocate.c
@@ -0,0 +1,338 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "model_206ax.h"
+
+#define EMRRphysBase_MSR 0x1f4
+#define EMRRphysMask_MSR 0x1f5
+#define UNCORE_EMRRphysBase_MSR 0x2f4
+#define UNCORE_EMRRphysMask_MSR 0x2f5
+
+#define CORE_THREAD_COUNT_MSR 0x35
+
+#define SMRR_SUPPORTED (1<<11)
+#define EMRR_SUPPORTED (1<<12)
+
+struct smm_relocation_params {
+ u32 smram_base;
+ u32 smram_size;
+ u32 ied_base;
+ u32 ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t emrr_base;
+ msr_t emrr_mask;
+ msr_t uncore_emrr_base;
+ msr_t uncore_emrr_mask;
+};
+
+/* This gets filled in and used during relocation. */
+static struct smm_relocation_params smm_reloc_params;
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
+ wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
+}
+
+static inline void write_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->emrr_base.lo, relo_params->emrr_mask.lo);
+ wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);
+ wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);
+}
+
+static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_emrr_base.lo,
+ relo_params->uncore_emrr_mask.lo);
+ wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);
+ wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);
+}
+
+/* The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here. */
+static void asmlinkage cpu_smm_do_relocation(void *arg)
+{
+ em64t101_smm_state_save_area_t *save_state;
+ msr_t mtrr_cap;
+ struct smm_relocation_params *relo_params;
+ const struct smm_module_params *p;
+ const struct smm_runtime *runtime;
+ int cpu;
+
+ p = arg;
+ runtime = p->runtime;
+ relo_params = p->arg;
+ cpu = p->cpu;
+
+ if (cpu >= CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Invalid CPU number assigned in SMM stub: %d\n", cpu);
+ return;
+ }
+
+ printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+
+ /* All threads need to set IEDBASE and SMBASE in the save state area.
+ * Since one thread runs at a time during the relocation the save state
+ * is the same for all cpus. */
+ save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
+ runtime->save_state_size);
+
+ /* The relocated handler runs with all CPUs concurrently. Therefore
+ * stagger the entry points adjusting SMBASE downwards by save state
+ * size * CPU num. */
+ save_state->smbase = relo_params->smram_base -
+ cpu * runtime->save_state_size;
+ save_state->iedbase = relo_params->ied_base;
+
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
+ save_state->smbase, save_state->iedbase, save_state);
+
+ /* Write EMRR and SMRR MSRs based on indicated support. */
+ mtrr_cap = rdmsr(MTRRcap_MSR);
+ if (mtrr_cap.lo & SMRR_SUPPORTED)
+ write_smrr(relo_params);
+
+ if (mtrr_cap.lo & EMRR_SUPPORTED) {
+ write_emrr(relo_params);
+ /* UNCORE_EMRR msrs are package level. Therefore, only
+ * configure these MSRs on the BSP. */
+ if (cpu == 0)
+ write_uncore_emrr(relo_params);
+ }
+
+ southbridge_clear_smi_status();
+}
+
+static u32 northbridge_get_base_reg(device_t dev, int reg)
+{
+ u32 value;
+
+ value = pci_read_config32(dev, reg);
+ /* Base registers are at 1MiB granularity. */
+ value &= ~((1 << 20) - 1);
+ return value;
+}
+
+static void fill_in_relocation_params(device_t dev,
+ struct smm_relocation_params *params)
+{
+ u32 tseg_size;
+ u32 tsegmb;
+ u32 bgsm;
+ u32 emrr_base;
+ u32 emrr_size;
+ int phys_bits;
+ /* All range registers are aligned to 4KiB */
+ const u32 rmask = ~((1 << 12) - 1);
+
+ /* Some of the range registers are dependent on the number of physical
+ * address bits supported. */
+ phys_bits = cpuid_eax(0x80000008) & 0xff;
+
+ /* The range bounded by the TSEGMB and BGSM registers encompasses the
+ * SMRAM range as well as the IED range. However, the SMRAM available
+ * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
+ */
+ tsegmb = northbridge_get_base_reg(dev, TSEG);
+ bgsm = northbridge_get_base_reg(dev, BGSM);
+ tseg_size = bgsm - tsegmb;
+
+ params->smram_base = tsegmb;
+ params->smram_size = 4 << 20;
+ params->ied_base = tsegmb + params->smram_size;
+ params->ied_size = tseg_size - params->smram_size;
+
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
+ params->smrr_mask.hi = 0;
+
+ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
+ emrr_base = (params->ied_base + (2 << 20)) & rmask;
+ emrr_size = params->ied_size - (2 << 20);
+
+ /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
+ * on the number of physical address bits supported. */
+ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
+ params->emrr_base.hi = 0;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid;
+ params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
+
+ /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
+ params->uncore_emrr_base.lo = emrr_base;
+ params->uncore_emrr_base.hi = 0;
+ params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
+ MTRRphysMaskValid;
+ params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
+}
+
+static int install_relocation_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* The default SMM entry happens serially at the default location.
+ * Therefore, there is only 1 concurrent save state area. Set the
+ * stack size to the save state size, and call into the
+ * do_relocation handler. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = 1,
+ .handler = &cpu_smm_do_relocation,
+ .handler_arg = (void *)relo_params,
+ };
+
+ return smm_setup_relocation_handler(&smm_params);
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+ char *ied_base;
+
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = params->ied_size,
+ .reserved = {0},
+ };
+
+ ied_base = (void *)params->ied_base;
+
+ /* Place IED header at IEDBASE. */
+ memcpy(ied_base, &ied, sizeof(ied));
+
+ /* Zero out 32KiB at IEDBASE + 1MiB */
+ memset(ied_base + (1 << 20), 0, (32 << 10));
+
+ /* According to the BWG MP init section 2MiB of memory at IEDBASE +
+ * 2MiB should be zeroed as well. However, I suspect what is intended
+ * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
+ //memset(ied_base + (2 << 20), 0, (2 << 20));
+}
+
+static int install_permanent_handler(int num_cpus,
+ struct smm_relocation_params *relo_params)
+{
+ /* There are num_cpus concurrent stacks and num_cpus concurrent save
+ * state areas. Lastly, set the stack size to the save state size. */
+ int save_state_size = sizeof(em64t101_smm_state_save_area_t);
+ struct smm_loader_params smm_params = {
+ .per_cpu_stack_size = save_state_size,
+ .num_concurrent_stacks = num_cpus,
+ .per_cpu_save_state_size = save_state_size,
+ .num_concurrent_save_states = num_cpus,
+ };
+
+ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
+ relo_params->smram_base);
+ return smm_load_module((void *)relo_params->smram_base,
+ relo_params->smram_size, &smm_params);
+}
+
+static int cpu_smm_setup(void)
+{
+ device_t dev;
+ int num_cpus;
+ msr_t msr;
+
+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ fill_in_relocation_params(dev, &smm_reloc_params);
+
+ setup_ied_area(&smm_reloc_params);
+
+ msr = rdmsr(CORE_THREAD_COUNT_MSR);
+ num_cpus = msr.lo & 0xffff;
+ if (num_cpus > CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT,
+ "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
+ num_cpus, CONFIG_MAX_CPUS);
+ }
+
+ if (install_relocation_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
+ return -1;
+ }
+
+ if (install_permanent_handler(num_cpus, &smm_reloc_params)) {
+ printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
+ return -1;
+ }
+
+ /* Ensure the SMM handlers hit DRAM before performing first SMI. */
+ /* TODO(adurbin): Is this really needed? */
+ wbinvd();
+
+ return 0;
+}
+
+void smm_init(void)
+{
+ /* Return early if CPU SMM setup failed. */
+ if (cpu_smm_setup())
+ return;
+
+ southbridge_smm_init();
+
+ /* Initiate first SMI to kick off SMM-context relocation. Note: this
+ * SMI being triggered here queues up an SMI in the APs which are in
+ * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
+ * at the SMM_DEFAULT_BASE before jumping to startup vector. */
+ southbridge_trigger_smi();
+
+ printk(BIOS_DEBUG, "Relocation complete.\n");
+
+ /* Lock down the SMRAM space. */
+ smm_lock();
+}
+
+void smm_lock(void)
+{
+ /* LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+ D_LCK | G_SMRAME | C_BASE_SEG);
+}
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 79ef156..3b29233 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -36,7 +36,7 @@
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
#include "../../../southbridge/intel/sch/sch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
+#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
#include "../../../southbridge/intel/bd82x6x/pch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
@@ -48,10 +48,7 @@
#if CONFIG_SMM_TSEG
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
+#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM
#include <northbridge/intel/nehalem/nehalem.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6be14b8..09894f7 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -99,6 +99,7 @@
#define TOM 0xa0
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
#define TSEG 0xb8 /* TSEG base */
#define TOLUD 0xbc /* Top of Low Used Memory */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 19e5407..842d9d9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -43,7 +43,6 @@
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
-#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -427,58 +426,20 @@ static void enable_clock_gating(device_t dev)
RCBA32_OR(0x3564, 0x3);
}
-#if CONFIG_HAVE_SMI_HANDLER
-static void pch_lock_smm(struct device *dev)
+static void pch_set_acpi_mode(void)
{
-#if TEST_SMM_FLASH_LOCKDOWN
- u8 reg8;
-#endif
-
- if (!acpi_is_wakeup_s3()) {
+ if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
- outb(0xe1, 0xb2); // Enable ACPI mode
+ outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(0x1e, 0xb2); // Disable ACPI mode
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#endif
}
-
- /* Don't allow evil boot loaders, kernels, or
- * userspace applications to deceive us:
- */
- smm_lock();
-
-#if TEST_SMM_FLASH_LOCKDOWN
- /* Now try this: */
- printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
- reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
- printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
-
- printk(BIOS_DEBUG, "Writing:\n");
- *(volatile u8 *)0xfff00000 = 0x00;
- printk(BIOS_DEBUG, "Testing:\n");
- reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
-
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
- (reg8&1)?"rw":"ro");
- printk(BIOS_DEBUG, "Done.\n");
-#endif
}
-#endif
static void pch_disable_smm_only_flashing(struct device *dev)
{
@@ -572,9 +533,7 @@ static void lpc_init(struct device *dev)
pch_disable_smm_only_flashing(dev);
-#if CONFIG_HAVE_SMI_HANDLER
- pch_lock_smm(dev);
-#endif
+ pch_set_acpi_mode();
pch_fixups(dev);
}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3ce5d63..950dbc4 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,6 +66,11 @@ void intel_pch_finalize_smm(void);
#include "chip.h"
void pch_enable(device_t dev);
#endif
+/* These helpers are for performing SMM relocation. */
+void southbridge_smm_init(void);
+void southbridge_trigger_smi(void);
+void southbridge_clear_smi_status(void);
+
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index b60c364..59a9c01 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -28,10 +28,6 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include "pch.h"
-#include "northbridge/intel/sandybridge/sandybridge.h"
-
-extern unsigned char _binary_smm_start;
-extern unsigned char _binary_smm_end;
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@@ -228,15 +224,18 @@ static void smi_set_eos(void)
outb(reg8, pmbase + SMI_EN);
}
-extern uint8_t smm_relocation_start, smm_relocation_end;
-
-static void smm_relocate(void)
+void southbridge_smm_init(void)
{
u32 smi_en;
u16 pm1_en;
u32 gpe0_en;
- printk(BIOS_DEBUG, "Initializing SMM handler...");
+#if CONFIG_ELOG
+ /* Log events from chipset before clearing */
+ pch_log_state();
+#endif
+
+ printk(BIOS_DEBUG, "Initializing southbridge SMI...");
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
@@ -249,10 +248,6 @@ static void smm_relocate(void)
return;
}
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
-
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
@@ -301,7 +296,10 @@ static void smm_relocate(void)
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
+}
+void southbridge_trigger_smi(void)
+{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@@ -320,79 +318,18 @@ static void smm_relocate(void)
outb(0x00, 0xb2);
}
-static int smm_handler_copied = 0;
-
-static void smm_install(void)
+void southbridge_clear_smi_status(void)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- u32 smm_base = 0xa0000;
- struct ied_header ied = {
- .signature = "INTEL RSVD",
- .size = IED_SIZE,
- .reserved = {0},
- };
-
- /* The first CPU running this gets to copy the SMM handler. But not all
- * of them.
- */
- if (smm_handler_copied)
- return;
- smm_handler_copied = 1;
-
- /* enable the SMM memory window */
- pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
-
-#if CONFIG_SMM_TSEG
- smm_base = pci_read_config32(dev, TSEG) & ~1;
-#endif
-
- /* copy the real SMM handler */
- printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
- memcpy((void *)smm_base, &_binary_smm_start,
- (size_t)(&_binary_smm_end - &_binary_smm_start));
-
- /* copy the IED header into place */
- if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
- /* Top of TSEG region */
- smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
- printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
- smm_base);
- memcpy((void *)smm_base, &ied, sizeof(ied));
- }
- wbinvd();
-
- /* close the SMM memory window and enable normal SMM */
- pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
-{
-#if CONFIG_ELOG
- /* Log events from chipset before clearing */
- pch_log_state();
-#endif
-
- /* Put SMM code to 0xa0000 */
- smm_install();
-
- /* Put relocation code to 0x38000 and relocate SMBASE */
- smm_relocate();
-
- /* We're done. Make sure SMIs can happen! */
+ /* Clear SMI status */
+ reset_smi_status();
+
+ /* Clear PM1 status */
+ reset_pm1_status();
+
+ /* Set EOS bit so other SMIs can occur. */
smi_set_eos();
}
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 3593c47..d9d63b7 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -31,10 +31,6 @@
#include "nvs.h"
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/pci_mmio_cfg.h>
#include <southbridge/intel/bd82x6x/me.h>
@@ -54,28 +50,12 @@ static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+static global_nvs_t *gnvs;
global_nvs_t *smm_get_gnvs(void)
{
return gnvs;
}
-#if CONFIG_SMM_TSEG
-static u32 tseg_base = 0;
-u32 smi_get_tseg_base(void)
-{
- if (!tseg_base)
- tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
- return tseg_base;
-}
-void tseg_relocate(void **ptr)
-{
- /* Adjust pointer with TSEG base */
- if (*ptr && *ptr < (void*)smi_get_tseg_base())
- *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
-}
-#endif
-
static void alt_gpi_mask(u16 clr, u16 set)
{
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
@@ -424,7 +404,7 @@ static void xhci_sleep(u8 slp_typ)
}
-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_sleep(void)
{
u8 reg8;
u32 reg32;
@@ -439,8 +419,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outb(tmp70, 0x70);
outb(tmp72, 0x72);
- void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
-
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
reg8 &= ~SLP_SMI_EN;
@@ -455,8 +433,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
xhci_sleep(slp_typ);
/* Do any mainboard sleep handling */
- tseg_relocate((void **)&mainboard_sleep);
- mainboard_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ-2);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
@@ -532,13 +509,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
{
em64t101_smm_state_save_area_t *state;
- u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
int node;
/* Check all nodes looking for the one that issued the IO */
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
- state = (em64t101_smm_state_save_area_t *)
- (base - (node * 0x400));
+ state = smm_get_save_state(node);
/* Check for Synchronous IO (bit0==1) */
if (!(state->io_misc_info & (1 << 0)))
@@ -587,11 +562,10 @@ static void southbridge_smi_gsmi(void)
static int mainboard_finalized = 0;
-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
- int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -657,11 +631,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
#endif
}
- tseg_relocate((void **)&mainboard_apmc);
- mainboard_apmc(reg8);
+ mainboard_smi_apmc(reg8);
}
-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
@@ -682,7 +655,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
@@ -690,17 +663,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
dump_gpe0_status(gpe0_sts);
}
-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_gpi(void)
{
- void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
- tseg_relocate((void **)&mainboard_gpi);
- mainboard_gpi(reg16);
+ mainboard_smi_gpi(reg16);
if (reg16)
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
@@ -708,7 +679,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
outw(reg16, pmbase + ALT_GP_SMI_STS);
}
-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_mc(void)
{
u32 reg32;
@@ -723,7 +694,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_tco(void)
{
u32 tco_sts;
@@ -760,7 +731,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
}
}
-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_periodic(void)
{
u32 reg32;
@@ -773,7 +744,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
printk(BIOS_DEBUG, "Periodic SMI.\n");
}
-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_sts, trap_cycle;
@@ -827,8 +798,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
#undef IOTRAP
}
-typedef void (*smi_handler_t)(unsigned int node,
- smm_state_save_area_t *state_save);
+typedef void (*smi_handler_t)(void);
static smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
@@ -870,7 +840,7 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+void southbridge_smi_handler(void)
{
int i, dump = 0;
u32 smi_sts;
@@ -887,15 +857,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
-#if CONFIG_SMM_TSEG
- smi_handler_t handler = (smi_handler_t)
- ((u8*)southbridge_smi[i] +
- smi_get_tseg_base());
- if (handler)
- handler(node, state_save);
-#else
- southbridge_smi[i](node, state_save);
-#endif
+ southbridge_smi[i]();
} else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);
1
0
Patch set updated for coreboot: 5b6df62 tpm: Add Infineon TPM 1.2 support
by Patrick Georgi 28 May '15
by Patrick Georgi 28 May '15
28 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10302
-gerrit
commit 5b6df626f321d62e9ac7a1e1b8b2f064bc2d27d5
Author: Subrata <subrata.banik(a)intel.com>
Date: Thu May 14 14:38:07 2015 +0530
tpm: Add Infineon TPM 1.2 support
This patch provides support for TPM Infineon TT1.2
devices by enumerating the TT1.2 ID in the Infineon
device list.
BRANCH=None
BUG=None
TEST=Built for sklrvp and tested on RVP3.
Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a
Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901
Original-Signed-off-by: Subrata <subrata.banik(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271256
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com>
---
src/drivers/pc80/tpm/tpm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index 12eba28..1013c05 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -127,6 +127,7 @@ static const struct device_name atmel_devices[] = {
static const struct device_name infineon_devices[] = {
{0x000b, "SLB9635 TT 1.2"},
+ {0x001a, "SLB9660 TT 1.2"},
{0xffff}
};
1
0
Patch set updated for coreboot: 1cd2923 tpm: Fix multiple device support
by Patrick Georgi 28 May '15
by Patrick Georgi 28 May '15
28 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10303
-gerrit
commit 1cd29231c926fae2d01213411620e5c600e99c07
Author: Subrata <subrata.banik(a)intel.com>
Date: Thu May 14 14:38:07 2015 +0530
tpm: Fix multiple device support
Current TPM driver does not support multiple devices for
a given vendor. As the device object never takes the 2nd
ID in the list. This patch fixes the same.
BRANCH=None
BUG=None
TEST=Built for sklrvp and tested on RVP3.
Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab
Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2
Original-Signed-off-by: Subrata <subrata.banik(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271727
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com>
Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar(a)intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar(a)intel.com>
---
src/drivers/pc80/tpm/tpm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index 1013c05..0ee3a90 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -404,6 +404,7 @@ static u32 tis_probe(void)
break;
}
j++;
+ dev = &vendor_names[i].dev_names[j];
}
break;
}
1
0
Patch set updated for coreboot: eded61f arm64: Decouple MMU functions from memranges
by Patrick Georgi 28 May '15
by Patrick Georgi 28 May '15
28 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10304
-gerrit
commit eded61f473498f0f724dd88399a9978e9d7944c6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon May 18 13:11:12 2015 -0700
arm64: Decouple MMU functions from memranges
The current arm64 MMU interface is difficult to use in pre-RAM
environments. It is based on the memranges API which makes use of
malloc(), and early stages usually don't have a heap. It is also built
as a one-shot interface that requires all memory ranges to be laid out
beforehand, which is a problem when existing areas need to change (e.g.
after initializing DRAM).
The long-term goal of this patch is to completely switch to a
configure-as-you-go interface based on the mmu_config_range() function,
similar to what ARM32 does. As a first step this feature is added
side-by-side to the existing interface so that existing SoC
implementations continue to work and can be slowly ported over one by
one. Like the ARM32 version it does not garbage collect page tables that
become unused, so repeated mapping at different granularities will
exhaust the available table space (this is presumed to be a reasonable
limitation for a firmware environment and keeps the code much simpler).
Also do some cleanup, align comments between coreboot and libpayload for
easier diffing, and change all error cases to assert()s. Right now the
code just propagates error codes up the stack until it eventually
reaches a function that doesn't check them anymore. MMU configuration
errors (essentially just misaligned requests and running out of table
space) should always be compile-time programming errors, so failing hard
and fast seems like the best way to deal with them.
BRANCH=None
BUG=None
TEST=Compile-tested rush_ryu. Booted on Oak and hacked MMU init to use
mmu_config_range() insted of memranges. Confirmed that CRCs over all page
tables before and after the change are equal.
Change-Id: I93585b44a277c1d96d31ee9c3dd2522b5e10085b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f10fcba107aba1f3ea239471cb5a4f9239809539
Original-Change-Id: I6a2a11e3b94e6ae9e1553871f0cccd3b556b3e65
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271991
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
payloads/libpayload/arch/arm64/mmu.c | 193 ++++++++++---------------
payloads/libpayload/include/arm64/arch/cache.h | 16 --
payloads/libpayload/include/arm64/arch/mmu.h | 3 +
src/arch/arm64/armv8/mmu.c | 169 ++++++++++------------
src/arch/arm64/include/armv8/arch/mmu.h | 2 +
5 files changed, 153 insertions(+), 230 deletions(-)
diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c
index f0781f5..e2a0cb1 100644
--- a/payloads/libpayload/arch/arm64/mmu.c
+++ b/payloads/libpayload/arch/arm64/mmu.c
@@ -44,6 +44,12 @@ static uint64_t *xlat_addr;
static int free_idx;
static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)));
+static const char * const tag_to_string[] = {
+ [TYPE_NORMAL_MEM] = "normal",
+ [TYPE_DEV_MEM] = "device",
+ [TYPE_DMA_MEM] = "uncached",
+};
+
/*
* The usedmem_ranges is used to describe all the memory ranges that are
* actually used by payload i.e. _start -> _end in linker script and the
@@ -56,25 +62,12 @@ static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE)
*/
static struct mmu_ranges usedmem_ranges;
-static const uint64_t level_to_addr_mask[] = {
- L1_ADDR_MASK,
- L2_ADDR_MASK,
- L3_ADDR_MASK,
-};
-
-static const uint64_t level_to_addr_shift[] = {
- L1_ADDR_SHIFT,
- L2_ADDR_SHIFT,
- L3_ADDR_SHIFT,
-};
-
static void __attribute__((noreturn)) mmu_error(void)
{
halt();
}
-/*
- * Func : get_block_attr
+/* Func : get_block_attr
* Desc : Get block descriptor attributes based on the value of tag in memrange
* region
*/
@@ -107,21 +100,7 @@ static uint64_t get_block_attr(unsigned long tag)
return attr;
}
-/*
- * Func : get_index_from_addr
- * Desc : Get index into table at a given level using appropriate bits from the
- * base address
- */
-static uint64_t get_index_from_addr(uint64_t addr, uint8_t level)
-{
- uint64_t mask = level_to_addr_mask[level-1];
- uint8_t shift = level_to_addr_shift[level-1];
-
- return ((addr & mask) >> shift);
-}
-
-/*
- * Func : table_desc_valid
+/* Func : table_desc_valid
* Desc : Check if a table entry contains valid desc
*/
static uint64_t table_desc_valid(uint64_t desc)
@@ -129,29 +108,34 @@ static uint64_t table_desc_valid(uint64_t desc)
return((desc & TABLE_DESC) == TABLE_DESC);
}
-/*
- * Func : get_new_table
- * Desc : Return the next free XLAT table from ttb buffer
+/* Func : setup_new_table
+ * Desc : Get next free table from TTB and set it up to match old parent entry.
*/
-static uint64_t *get_new_table(void)
+static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size)
{
- uint64_t *new;
+ uint64_t *new, *entry;
- if (free_idx >= max_tables) {
- printf("ARM64 MMU: No free table\n");
- return NULL;
- }
+ assert(free_idx < max_tables);
new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE);
free_idx++;
- memset(new, 0, GRANULE_SIZE);
+ if (!desc) {
+ memset(new, 0, GRANULE_SIZE);
+ } else {
+ /* Can reuse old parent entry, but may need to adjust type. */
+ if (xlat_size == L3_XLAT_SIZE)
+ desc |= PAGE_DESC;
+
+ for (entry = new; (u8 *)entry < (u8 *)new + GRANULE_SIZE;
+ entry++, desc += xlat_size)
+ *entry = desc;
+ }
return new;
}
-/*
- * Func : get_table_from_desc
+/* Func : get_table_from_desc
* Desc : Get next level table address from table descriptor
*/
static uint64_t *get_table_from_desc(uint64_t desc)
@@ -160,27 +144,23 @@ static uint64_t *get_table_from_desc(uint64_t desc)
return ptr;
}
-/*
- * Func: get_next_level_table
- * Desc: Check if the table entry is a valid descriptor. If not, allocate new
+/* Func: get_next_level_table
+ * Desc: Check if the table entry is a valid descriptor. If not, initialize new
* table, update the entry and return the table addr. If valid, return the addr.
*/
-static uint64_t *get_next_level_table(uint64_t *ptr)
+static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size)
{
uint64_t desc = *ptr;
if (!table_desc_valid(desc)) {
- uint64_t *new_table = get_new_table();
- if (new_table == NULL)
- return NULL;
+ uint64_t *new_table = setup_new_table(desc, xlat_size);
desc = ((uint64_t)new_table) | TABLE_DESC;
*ptr = desc;
}
return get_table_from_desc(desc);
}
-/*
- * Func : init_xlat_table
+/* Func : init_xlat_table
* Desc : Given a base address and size, it identifies the indices within
* different level XLAT tables which map the given base addr. Similar to table
* walk, except that all invalid entries during the walk are updated
@@ -191,18 +171,16 @@ static uint64_t init_xlat_table(uint64_t base_addr,
uint64_t size,
uint64_t tag)
{
- uint64_t l1_index = get_index_from_addr(base_addr,1);
- uint64_t l2_index = get_index_from_addr(base_addr,2);
- uint64_t l3_index = get_index_from_addr(base_addr,3);
+ uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT;
+ uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT;
+ uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT;
uint64_t *table = xlat_addr;
uint64_t desc;
uint64_t attr = get_block_attr(tag);
- /*
- * L1 table lookup
+ /* L1 table lookup
* If VA has bits more than L2 can resolve, lookup starts at L1
- * Assumption: we don't need L0 table in coreboot
- */
+ * Assumption: we don't need L0 table in coreboot */
if (BITS_PER_VA > L1_ADDR_SHIFT) {
if ((size >= L1_XLAT_SIZE) &&
IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {
@@ -213,94 +191,71 @@ static uint64_t init_xlat_table(uint64_t base_addr,
table[l1_index] = desc;
/* L2 lookup is not required */
return L1_XLAT_SIZE;
- } else {
- table = get_next_level_table(&table[l1_index]);
- if (!table)
- return 0;
}
+ table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);
}
- /*
- * L2 table lookup
+ /* L2 table lookup
* If lookup was performed at L1, L2 table addr is obtained from L1 desc
- * else, lookup starts at ttbr address
- */
+ * else, lookup starts at ttbr address */
if ((size >= L2_XLAT_SIZE) &&
IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {
- /*
- * If block address is aligned and size is greater than or equal
- * to size addressed by each L2 entry, we can
- * directly store a block desc
- */
+ /* If block address is aligned and size is greater than
+ * or equal to size addressed by each L2 entry, we can
+ * directly store a block desc */
desc = base_addr | BLOCK_DESC | attr;
table[l2_index] = desc;
/* L3 lookup is not required */
return L2_XLAT_SIZE;
- } else {
- /* L2 entry stores a table descriptor */
- table = get_next_level_table(&table[l2_index]);
- if (!table)
- return 0;
}
+ /* L2 entry stores a table descriptor */
+ table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE);
+
/* L3 table lookup */
desc = base_addr | PAGE_DESC | attr;
table[l3_index] = desc;
return L3_XLAT_SIZE;
}
-/*
- * Func : sanity_check
- * Desc : Check if the address is aligned and size is atleast the granule size
+/* Func : sanity_check
+ * Desc : Check address/size alignment of a table or page.
*/
-static uint64_t sanity_check(uint64_t addr,
- uint64_t size)
+static void sanity_check(uint64_t addr, uint64_t size)
{
- /* Address should be atleast 64 KiB aligned */
- if (addr & GRANULE_SIZE_MASK)
- return 1;
-
- /* Size should be atleast granule size */
- if (size < GRANULE_SIZE)
- return 1;
-
- return 0;
+ assert(!(addr & GRANULE_SIZE_MASK) &&
+ !(size & GRANULE_SIZE_MASK) &&
+ size >= GRANULE_SIZE);
}
-/*
- * Func : init_mmap_entry
- * Desc : For each mmap entry, this function calls init_xlat_table with the base
+/* Func : mmu_config_range
+ * Desc : This function repeatedly calls init_xlat_table with the base
* address. Based on size returned from init_xlat_table, base_addr is updated
* and subsequent calls are made for initializing the xlat table until the whole
* region is initialized.
*/
-static void init_mmap_entry(struct mmu_memrange *r)
+void mmu_config_range(void *start, size_t size, uint64_t tag)
{
- uint64_t base_addr = r->base;
- uint64_t size = r->size;
- uint64_t tag = r->type;
+ uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- while (temp_size) {
- uint64_t ret;
-
- if (sanity_check(base_addr,temp_size)) {
- printf("Libpayload: ARM64 MMU: sanity check failed\n");
- return;
- }
-
- ret = init_xlat_table(base_addr + (size - temp_size),
- temp_size, tag);
+ assert(tag < ARRAY_SIZE(tag_to_string));
+ printf("Libpayload: ARM64 MMU: Mapping address range [%p:%p) as %s\n",
+ start, start + size, tag_to_string[tag]);
+ sanity_check(base_addr, temp_size);
- if (ret == 0)
- return;
+ while (temp_size)
+ temp_size -= init_xlat_table(base_addr + (size - temp_size),
+ temp_size, tag);
- temp_size -= ret;
- }
+ /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */
+ dsb();
+ tlbiall_current();
+ dsb();
+ isb();
}
-/*
- * Func : mmu_init
+/* Func : mmu_init
* Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as
* the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of
* tables that can be used
@@ -308,8 +263,6 @@ static void init_mmap_entry(struct mmu_memrange *r)
*/
uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
{
- struct mmu_memrange devrange = { 0, 0x80000000, TYPE_DEV_MEM };
-
int i = 0;
xlat_addr = (uint64_t *)&ttb_buffer;
@@ -321,11 +274,12 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n",
(void*)xlat_addr, max_tables);
- init_mmap_entry(&devrange);
+ mmu_config_range(NULL, 0x80000000, TYPE_DEV_MEM);
- for (; i < mmu_ranges->used; i++) {
- init_mmap_entry(&mmu_ranges->entries[i]);
- }
+ for (; i < mmu_ranges->used; i++)
+ mmu_config_range((void *)mmu_ranges->entries[i].base,
+ mmu_ranges->entries[i].size,
+ mmu_ranges->entries[i].type);
printf("Libpayload ARM64: MMU init done\n");
return 0;
@@ -388,8 +342,7 @@ void mmu_enable(void)
/* Initialize TTBR */
raw_write_ttbr0_current((uintptr_t)xlat_addr);
- /* Ensure all translation table writes are committed before enabling MMU */
- dsb();
+ /* Ensure system register writes are committed before enabling MMU */
isb();
/* Enable MMU */
diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h
index 7248869..de68cee 100644
--- a/payloads/libpayload/include/arm64/arch/cache.h
+++ b/payloads/libpayload/include/arm64/arch/cache.h
@@ -117,20 +117,4 @@ static inline void icache_invalidate_all(void)
: : : "memory");
}
-/*
- * Generalized setup/init functions
- */
-
-enum dcache_policy {
- DCACHE_OFF,
- DCACHE_WRITEBACK,
- DCACHE_WRITETHROUGH,
-};
-
-/* disable the mmu for a range. Primarily useful to lock out address 0. */
-void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
-/* mmu range configuration (set dcache policy) */
-void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
- enum dcache_policy policy);
-
#endif /* ARM64_CACHE_H */
diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h
index 79bc783..30a1973 100644
--- a/payloads/libpayload/include/arm64/arch/mmu.h
+++ b/payloads/libpayload/include/arm64/arch/mmu.h
@@ -175,6 +175,9 @@ void mmu_enable(void);
/* Disable mmu */
void mmu_disable(void);
+/* Change a memory type for a range of bytes at runtime. */
+void mmu_config_range(void *start, size_t size, uint64_t tag);
+
/*
* Based on the memory ranges provided in coreboot tables,
* initialize the mmu_memranges used for mmu initialization
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 99c97fb..0bd678a 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -27,10 +27,12 @@
* SUCH DAMAGE.
*/
+#include <assert.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
+#include <console/console.h>
#include <memrange.h>
#include <arch/mmu.h>
#include <arch/lib_helpers.h>
@@ -42,17 +44,17 @@ static unsigned int max_tables;
static uint64_t *xlat_addr;
static int free_idx;
-static const uint64_t level_to_addr_mask[] = {
- L1_ADDR_MASK,
- L2_ADDR_MASK,
- L3_ADDR_MASK,
-};
-
-static const uint64_t level_to_addr_shift[] = {
- L1_ADDR_SHIFT,
- L2_ADDR_SHIFT,
- L3_ADDR_SHIFT,
-};
+static void print_tag(int level, uint64_t tag)
+{
+ printk(level, tag & MA_MEM_NC ? " cacheable | " :
+ "non-cacheable | ");
+ printk(level, tag & MA_RO ? "read-only | " :
+ "read-write | ");
+ printk(level, tag & MA_NS ? "non-secure | " :
+ " secure | ");
+ printk(level, tag & MA_MEM ? "normal\n" :
+ "device\n");
+}
/* Func : get_block_attr
* Desc : Get block descriptor attributes based on the value of tag in memrange
@@ -79,18 +81,6 @@ static uint64_t get_block_attr(unsigned long tag)
return attr;
}
-/* Func : get_index_from_addr
- * Desc : Get index into table at a given level using appropriate bits from the
- * base address
- */
-static uint64_t get_index_from_addr(uint64_t addr, uint8_t level)
-{
- uint64_t mask = level_to_addr_mask[level-1];
- uint8_t shift = level_to_addr_shift[level-1];
-
- return ((addr & mask) >> shift);
-}
-
/* Func : table_desc_valid
* Desc : Check if a table entry contains valid desc
*/
@@ -99,21 +89,29 @@ static uint64_t table_desc_valid(uint64_t desc)
return((desc & TABLE_DESC) == TABLE_DESC);
}
-/* Func : get_new_table
- * Desc : Return the next free XLAT table from ttb buffer
+/* Func : setup_new_table
+ * Desc : Get next free table from TTB and set it up to match old parent entry.
*/
-static uint64_t *get_new_table(void)
+static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size)
{
- uint64_t *new;
+ uint64_t *new, *entry;
- if (free_idx >= max_tables) {
- return NULL;
- }
+ assert(free_idx < max_tables);
new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE);
free_idx++;
- memset(new, 0, GRANULE_SIZE);
+ if (!desc) {
+ memset(new, 0, GRANULE_SIZE);
+ } else {
+ /* Can reuse old parent entry, but may need to adjust type. */
+ if (xlat_size == L3_XLAT_SIZE)
+ desc |= PAGE_DESC;
+
+ for (entry = new; (u8 *)entry < (u8 *)new + GRANULE_SIZE;
+ entry++, desc += xlat_size)
+ *entry = desc;
+ }
return new;
}
@@ -128,17 +126,15 @@ static uint64_t *get_table_from_desc(uint64_t desc)
}
/* Func: get_next_level_table
- * Desc: Check if the table entry is a valid descriptor. If not, allocate new
+ * Desc: Check if the table entry is a valid descriptor. If not, initialize new
* table, update the entry and return the table addr. If valid, return the addr
*/
-static uint64_t *get_next_level_table(uint64_t *ptr)
+static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size)
{
uint64_t desc = *ptr;
if (!table_desc_valid(desc)) {
- uint64_t *new_table = get_new_table();
- if (new_table == NULL)
- return NULL;
+ uint64_t *new_table = setup_new_table(desc, xlat_size);
desc = ((uint64_t)new_table) | TABLE_DESC;
*ptr = desc;
}
@@ -150,22 +146,22 @@ static uint64_t *get_next_level_table(uint64_t *ptr)
* different level XLAT tables which map the given base addr. Similar to table
* walk, except that all invalid entries during the walk are updated
* accordingly. On success, it returns the size of the block/page addressed by
- * the final table
+ * the final table.
*/
static uint64_t init_xlat_table(uint64_t base_addr,
uint64_t size,
uint64_t tag)
{
- uint64_t l1_index = get_index_from_addr(base_addr,1);
- uint64_t l2_index = get_index_from_addr(base_addr,2);
- uint64_t l3_index = get_index_from_addr(base_addr,3);
+ uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT;
+ uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT;
+ uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT;
uint64_t *table = xlat_addr;
uint64_t desc;
uint64_t attr = get_block_attr(tag);
- /* L1 table lookup */
- /* If VA has bits more than L2 can resolve, lookup starts at L1
- Assumption: we don't need L0 table in coreboot */
+ /* L1 table lookup
+ * If VA has bits more than L2 can resolve, lookup starts at L1
+ * Assumption: we don't need L0 table in coreboot */
if (BITS_PER_VA > L1_ADDR_SHIFT) {
if ((size >= L1_XLAT_SIZE) &&
IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {
@@ -176,16 +172,13 @@ static uint64_t init_xlat_table(uint64_t base_addr,
table[l1_index] = desc;
/* L2 lookup is not required */
return L1_XLAT_SIZE;
- } else {
- table = get_next_level_table(&table[l1_index]);
- if (!table)
- return 0;
}
+ table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);
}
- /* L2 table lookup */
- /* If lookup was performed at L1, L2 table addr is obtained from L1 desc
- else, lookup starts at ttbr address */
+ /* L2 table lookup
+ * If lookup was performed at L1, L2 table addr is obtained from L1 desc
+ * else, lookup starts at ttbr address */
if ((size >= L2_XLAT_SIZE) &&
IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {
/* If block address is aligned and size is greater than
@@ -195,13 +188,11 @@ static uint64_t init_xlat_table(uint64_t base_addr,
table[l2_index] = desc;
/* L3 lookup is not required */
return L2_XLAT_SIZE;
- } else {
- /* L2 entry stores a table descriptor */
- table = get_next_level_table(&table[l2_index]);
- if (!table)
- return 0;
}
+ /* L2 entry stores a table descriptor */
+ table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE);
+
/* L3 table lookup */
desc = base_addr | PAGE_DESC | attr;
table[l3_index] = desc;
@@ -209,50 +200,40 @@ static uint64_t init_xlat_table(uint64_t base_addr,
}
/* Func : sanity_check
- * Desc : Check if the address is aligned and size is atleast the granule size
+ * Desc : Check address/size alignment of a table or page.
*/
-static uint64_t sanity_check(uint64_t addr,
- uint64_t size)
+static void sanity_check(uint64_t addr, uint64_t size)
{
- /* Address should be atleast 64 KiB aligned */
- if (addr & GRANULE_SIZE_MASK)
- return 1;
-
- /* Size should be atleast granule size */
- if (size < GRANULE_SIZE)
- return 1;
-
- return 0;
+ assert(!(addr & GRANULE_SIZE_MASK) &&
+ !(size & GRANULE_SIZE_MASK) &&
+ size >= GRANULE_SIZE);
}
-/* Func : init_mmap_entry
- * Desc : For each mmap entry, this function calls init_xlat_table with the base
+/* Func : mmu_config_range
+ * Desc : This function repeatedly calls init_xlat_table with the base
* address. Based on size returned from init_xlat_table, base_addr is updated
* and subsequent calls are made for initializing the xlat table until the whole
* region is initialized.
*/
-static void init_mmap_entry(struct range_entry *r)
+void mmu_config_range(void *start, size_t size, uint64_t tag)
{
- uint64_t base_addr = range_entry_base(r);
- uint64_t size = range_entry_size(r);
- uint64_t tag = range_entry_tag(r);
+ uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- while (temp_size) {
- uint64_t ret;
-
- if (sanity_check(base_addr,temp_size)) {
- return;
- }
+ printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
+ start, start + size);
+ print_tag(BIOS_INFO, tag);
+ sanity_check(base_addr, temp_size);
- ret = init_xlat_table(base_addr + (size - temp_size),
- temp_size,tag);
+ while (temp_size)
+ temp_size -= init_xlat_table(base_addr + (size - temp_size),
+ temp_size, tag);
- if (ret == 0)
- return;
-
- temp_size -= ret;
- }
+ /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */
+ dsb();
+ tlbiall_current();
+ dsb();
+ isb();
}
/* Func : mmu_init
@@ -266,18 +247,19 @@ void mmu_init(struct memranges *mmap_ranges,
{
struct range_entry *mmap_entry;
- if (sanity_check((uint64_t)ttb_buffer, ttb_size)) {
- return;
- }
+ sanity_check((uint64_t)ttb_buffer, ttb_size);
memset((void*)ttb_buffer, 0, GRANULE_SIZE);
max_tables = (ttb_size >> GRANULE_SIZE_SHIFT);
xlat_addr = ttb_buffer;
free_idx = 1;
- memranges_each_entry(mmap_entry, mmap_ranges) {
- init_mmap_entry(mmap_entry);
- }
+ if (mmap_ranges)
+ memranges_each_entry(mmap_entry, mmap_ranges) {
+ mmu_config_range((void *)range_entry_base(mmap_entry),
+ range_entry_size(mmap_entry),
+ range_entry_tag(mmap_entry));
+ }
}
void mmu_enable(void)
@@ -298,8 +280,7 @@ void mmu_enable(void)
/* Initialize TTBR */
raw_write_ttbr0_el3((uintptr_t)xlat_addr);
- /* Ensure all translation table writes are committed before enabling MMU */
- dsb();
+ /* Ensure system register writes are committed before enabling MMU */
isb();
/* Enable MMU */
diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h
index c487c1f..f5111ae 100644
--- a/src/arch/arm64/include/armv8/arch/mmu.h
+++ b/src/arch/arm64/include/armv8/arch/mmu.h
@@ -148,5 +148,7 @@
void mmu_init(struct memranges *ranges, uint64_t *ttb, uint64_t ttb_size);
/* Enable the mmu based on previous mmu_init(). */
void mmu_enable(void);
+/* Change a memory type for a range of bytes at runtime. */
+void mmu_config_range(void *start, size_t size, uint64_t tag);
#endif // __ARCH_ARM64_MMU_H__
1
0
28 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10311
-gerrit
commit 2df7fc991dc4eaac985cdb70ae94a6d56642d1aa
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed May 20 17:10:55 2015 -0700
arm64: Guard prints in mmu.c
We have observed issues with enabling CONFIG_SMP and adding prints
before MMU is enabled on Tegra-based SoCs. This seems to be related
to the hardware assisted locks and the restrictions laid down by ARMv8
spec.
BUG=None
BRANCH=None
TEST=Boots to kernel prompt on smaug.
Change-Id: I29a52f5a972baf396c01faba3ae3e5ecd27563e9
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f52ee4b5b2e9b7f54eee0d105cb7e17f9a7e1613
Original-Change-Id: I432895560f468903c7beef00e78b6d38275a619c
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272449
Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/armv8/mmu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 0bd678a..e16ee71 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -220,9 +220,12 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
- start, start + size);
- print_tag(BIOS_INFO, tag);
+ if (!IS_ENABLED(CONFIG_SMP)) {
+ printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
+ start, start + size);
+ print_tag(BIOS_INFO, tag);
+ }
+
sanity_check(base_addr, temp_size);
while (temp_size)
1
0
Patch set updated for coreboot: 4254e6b ipq806x: clear the RPM initialization Acknowledge bit
by Patrick Georgi 28 May '15
by Patrick Georgi 28 May '15
28 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10310
-gerrit
commit 4254e6be021e06027e81e2f8c1cd2564d742e941
Author: Sourabh Banerjee <sbanerje(a)codeaurora.org>
Date: Fri Apr 24 22:54:18 2015 +0530
ipq806x: clear the RPM initialization Acknowledge bit
The RPM initialization Acknowledge is cleared by writing 1
into bit-10 of the RPM_INT_ACK register.
The existing code got it wrong and is writing zero to that bit.
BRANCH=storm
BUG=chrome-os-partner:39231
TEST=with this patch and an RPM firmware update, an SP4 device
survived more than 1000 reboots in a row.
Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7
Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524
Original-Signed-off-by: Viswanath Kraleti <vkraleti(a)codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/266969
Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com>
---
src/soc/qualcomm/ipq806x/blobs_init.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
index dc52200..ae7e4d4 100644
--- a/src/soc/qualcomm/ipq806x/blobs_init.c
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -131,7 +131,11 @@ void start_rpm(void)
printk(BIOS_INFO, "Starting RPM\n");
/* Clear 'ready' indication. */
- write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask);
+ /*
+ * RPM_INT_ACK is clear-on-write type register,
+ * read-modify-write is not recommended.
+ */
+ write32(RPM_INT_ACK, ready_mask);
/* Set RPM entry address */
write32(RPM_SIGNAL_ENTRY, load_addr);
1
0
Patch set updated for coreboot: b4a2b32 Revert fmap and boot_device commits
by Vladimir Serbinenko 28 May '15
by Vladimir Serbinenko 28 May '15
28 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10350
-gerrit
commit b4a2b32cb30c2ccb064b63837cb7aa239d0616be
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 28 14:24:09 2015 +0200
Revert fmap and boot_device commits
Those commits miss tseg_relocate somewhere and so SMI hangs on shutdown.
Revert the commit until we figure out where is the mistake or switch
sandy/ivy/nehalem to SMM modules (preffered).
This reverts commit 0424c95a6dafdb65070538d6c5aa394b75eb9850.
This reverts commit c6588c5af94e568bddd8111c3fca736f464042cf.
Change-Id: I1e330c2730092e9b81d98ee861605bc32a6a7ab3
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/Kconfig | 9 --
src/arch/riscv/rom_media.c | 66 ++++++------
src/arch/x86/lib/Makefile.inc | 3 -
src/arch/x86/lib/mmap_boot.c | 31 ------
src/arch/x86/lib/rom_media.c | 57 +++++-----
src/cpu/allwinner/a10/bootblock_media.c | 8 +-
src/cpu/ti/am335x/bootblock_media.c | 47 ++------
src/cpu/ti/am335x/nand.c | 10 +-
src/drivers/elog/elog.c | 49 ++++++---
src/include/boot_device.h | 41 -------
src/include/fmap.h | 35 ------
src/include/fmap_serialized.h | 73 -------------
src/lib/Makefile.inc | 11 --
src/lib/boot_device.c | 38 -------
src/lib/cbfs_spi.c | 97 +++++------------
src/lib/fmap.c | 119 ---------------------
src/mainboard/emulation/qemu-armv7/media.c | 45 ++------
src/mainboard/google/butterfly/mainboard.c | 41 +++----
src/mainboard/google/panther/lan.c | 25 ++---
src/northbridge/intel/haswell/mrccache.c | 28 +++--
src/northbridge/intel/sandybridge/mrccache.c | 29 +++--
src/soc/intel/common/mrc_cache.c | 27 ++---
src/soc/nvidia/tegra124/Makefile.inc | 4 +
src/soc/nvidia/tegra124/cbfs.c | 29 +++++
src/soc/nvidia/tegra124/include/soc/spi.h | 5 +
src/soc/nvidia/tegra124/spi.c | 116 +++++++-------------
src/soc/nvidia/tegra132/Makefile.inc | 4 +
src/soc/nvidia/tegra132/cbfs.c | 28 +++++
src/soc/nvidia/tegra132/include/soc/spi.h | 5 +
src/soc/nvidia/tegra132/spi.c | 116 +++++++-------------
src/soc/samsung/exynos5250/alternate_cbfs.c | 118 +++++++-------------
src/soc/samsung/exynos5250/include/soc/spi.h | 9 +-
src/soc/samsung/exynos5250/spi.c | 85 +++++++++------
src/soc/samsung/exynos5420/alternate_cbfs.c | 118 +++++++-------------
src/soc/samsung/exynos5420/include/soc/spi.h | 9 +-
src/soc/samsung/exynos5420/spi.c | 78 ++++++++++----
src/vendorcode/google/chromeos/Kconfig | 9 ++
src/vendorcode/google/chromeos/Makefile.inc | 4 +
src/vendorcode/google/chromeos/cros_vpd.c | 30 +++---
src/vendorcode/google/chromeos/fmap.h | 79 ++++++++++++++
.../google/chromeos/vboot2/vboot_handoff.c | 2 +-
41 files changed, 665 insertions(+), 1072 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 26e1194..5cfb06f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -244,15 +244,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
-config FLASHMAP_OFFSET
- hex "Flash Map Offset"
- default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
- default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
- default CBFS_SIZE if !ARCH_X86
- default 0
- help
- Offset of flash map in firmware image
-
choice
prompt "Bootblock behaviour"
default BOOTBLOCK_SIMPLE
diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c
index f18030c..8d3376c 100644
--- a/src/arch/riscv/rom_media.c
+++ b/src/arch/riscv/rom_media.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2015 Google Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -17,59 +17,40 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
-#include <console/console.h>
#include <string.h>
-/* This assumes that the CBFS resides at 0x0, which is true for the default
- * configuration. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
+#ifdef LIBPAYLOAD
+# define printk(x...)
+# define init_default_cbfs_media libpayload_init_default_cbfs_media
+ extern int libpayload_init_default_cbfs_media(struct cbfs_media *media);
+#else
+# include <console/console.h>
+#endif
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
+// Implementation of memory-mapped ROM media source on X86.
static int rom_media_open(struct cbfs_media *media) {
return 0;
}
static void *rom_media_map(struct cbfs_media *media, size_t offset, size_t count) {
- const struct region_device *boot_dev;
void *ptr;
-
printk(BIOS_INFO, "%s: media %p, offset %lx, size %ld.\n", __func__, media, offset, count);
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
+ ptr = (void*)offset;
return ptr;
}
static void *rom_media_unmap(struct cbfs_media *media, const void *address) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t rom_media_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
+ void *ptr = rom_media_map(media, offset, count);
+ memcpy(dest, ptr, count);
+ rom_media_unmap(media, ptr);
return count;
}
@@ -78,8 +59,25 @@ static int rom_media_close(struct cbfs_media *media) {
}
static int init_rom_media_cbfs(struct cbfs_media *media) {
- boot_device_init();
- media->context = (void *)boot_device_ro();
+ /* this assumes that the CBFS resides at 0x0,
+ * which is true for the default configuration
+ */
+ int32_t *cbfs_header_ptr = (int32_t*)(uintptr_t)(CONFIG_CBFS_SIZE - 4);
+ uint64_t cbfs_header_offset = CONFIG_CBFS_SIZE + *cbfs_header_ptr;
+ struct cbfs_header *header = (struct cbfs_header*) cbfs_header_offset;
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ printk(BIOS_ERR, "Expected %08lx and got %08lx\n", (unsigned long) CBFS_HEADER_MAGIC, (unsigned long) ntohl(header->magic));
+ return -1;
+ } else {
+ uint32_t romsize = ntohl(header->romsize);
+ media->context = (void*)(uintptr_t)romsize;
+#if defined(CONFIG_ROM_SIZE)
+ if (CONFIG_ROM_SIZE != romsize)
+ printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ CONFIG_ROM_SIZE, romsize);
+#endif
+ }
media->open = rom_media_open;
media->close = rom_media_close;
media->map = rom_media_map;
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index e308be9..c7e8b62 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -6,7 +6,6 @@ romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += rom_media.c
-romstage-y += mmap_boot.c
endif # CONFIG_ARCH_ROMSTAGE_X86_32
@@ -23,7 +22,6 @@ ramstage-y += memcpy.c
ramstage-y += memmove.c
ramstage-y += ebda.c
ramstage-y += rom_media.c
-ramstage-y += mmap_boot.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -34,7 +32,6 @@ smm-y += memset.c
smm-y += memcpy.c
smm-y += memmove.c
smm-y += rom_media.c
-smm-y += mmap_boot.c
rmodules_x86_32-y += memset.c
rmodules_x86_32-y += memcpy.c
diff --git a/src/arch/x86/lib/mmap_boot.c b/src/arch/x86/lib/mmap_boot.c
deleted file mode 100644
index eb7b23e..0000000
--- a/src/arch/x86/lib/mmap_boot.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-
-/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
-#define rom_base ((void *)(uintptr_t)(-(int32_t)CONFIG_ROM_SIZE))
-
-static const struct mem_region_device boot_dev =
- MEM_REGION_DEV_INIT(rom_base, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &boot_dev.rdev;
-}
diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c
index d4663c7..659e5e4 100644
--- a/src/arch/x86/lib/rom_media.c
+++ b/src/arch/x86/lib/rom_media.c
@@ -17,8 +17,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
-
-#include <boot_device.h>
#include <cbfs.h>
#include <string.h>
@@ -38,19 +36,14 @@ static int x86_rom_open(struct cbfs_media *media) {
static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) {
void *ptr;
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
+ // Some address (ex, pointer to master header) may be given in memory
+ // mapped location. To workaround that, we handle >0xf0000000 as real
+ // memory pointer.
- /* Extremely large offsets are considered relative to end of region. */
if ((uint32_t)offset > (uint32_t)0xf0000000)
- offset += region_device_sz(boot_dev);
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
+ ptr = (void*)offset;
+ else
+ ptr = (void*)(0 - (uint32_t)media->context + offset);
return ptr;
}
@@ -60,13 +53,7 @@ static void *x86_rom_unmap(struct cbfs_media *media, const void *address) {
static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count) {
- void *ptr;
-
- ptr = x86_rom_map(media, offset, count);
-
- if (ptr == (void *)-1)
- return 0;
-
+ void *ptr = x86_rom_map(media, offset, count);
memcpy(dest, ptr, count);
x86_rom_unmap(media, ptr);
return count;
@@ -76,14 +63,30 @@ static int x86_rom_close(struct cbfs_media *media) {
return 0;
}
-static int init_x86rom_cbfs_media(struct cbfs_media *media) {
- boot_device_init();
-
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
+int init_x86rom_cbfs_media(struct cbfs_media *media);
+int init_x86rom_cbfs_media(struct cbfs_media *media) {
+ // On X86, we always keep a reference of pointer to CBFS header in
+ // 0xfffffffc, and the pointer is still a memory-mapped address.
+ // Since the CBFS core always use ROM offset, we need to figure out
+ // header->romsize even before media is initialized.
+ struct cbfs_header *header = (struct cbfs_header*)
+ *(uint32_t*)(0xfffffffc);
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+#if defined(CONFIG_ROM_SIZE)
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ media->context = (void*)CONFIG_ROM_SIZE;
+#else
return -1;
-
+#endif
+ } else {
+ uint32_t romsize = ntohl(header->romsize);
+ media->context = (void*)romsize;
+#if defined(CONFIG_ROM_SIZE)
+ if (CONFIG_ROM_SIZE != romsize)
+ printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ CONFIG_ROM_SIZE, romsize);
+#endif
+ }
media->open = x86_rom_open;
media->close = x86_rom_close;
media->map = x86_rom_map;
diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c
index a585bca..a5863b6 100644
--- a/src/cpu/allwinner/a10/bootblock_media.c
+++ b/src/cpu/allwinner/a10/bootblock_media.c
@@ -4,17 +4,11 @@
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
* Subject to the GNU GPL v2, or (at your option) any later version.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
-const struct region_device *boot_device_ro(void)
-{
- return NULL;
-}
-
int init_default_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet.");
- return -1;
+ return 0;
}
diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c
index 79724ee..9824fc3 100644
--- a/src/cpu/ti/am335x/bootblock_media.c
+++ b/src/cpu/ti/am335x/bootblock_media.c
@@ -17,21 +17,11 @@
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <symbols.h>
-/* FIXME: No idea how big the internal SRAM actually is. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT(_dram, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
-
static int dummy_open(struct cbfs_media *media)
{
return 0;
@@ -45,48 +35,33 @@ static int dummy_close(struct cbfs_media *media)
static void * on_chip_memory_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ return _dram + offset;
}
static void * dummy_unmap(struct cbfs_media *media, const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t on_chip_memory_read(struct cbfs_media *media, void *dest,
size_t offset, size_t count)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
+ void *ptr = media->map(media, offset, count);
+ memcpy(dest, ptr, count);
+ media->unmap(media, ptr);
return count;
}
int init_default_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ struct cbfs_header *header =
+ (struct cbfs_header *)(_dram + CONFIG_CBFS_HEADER_ROM_OFFSET);
+
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ return -1;
+ }
- media->context = (void *)boot_device_ro();
media->open = dummy_open;
media->close = dummy_close;
media->map = on_chip_memory_map;
diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c
index dd05fb6..a8c945b 100644
--- a/src/cpu/ti/am335x/nand.c
+++ b/src/cpu/ti/am335x/nand.c
@@ -17,16 +17,10 @@
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
-const struct region_device *boot_device_ro(void)
-{
- return NULL;
-}
-
int init_default_cbfs_media(struct cbfs_media *media)
{
- /* FIXME: add support for reading coreboot from NAND */
- return -1;
+ /* FIXME: add support for reading coreboot from NAND */
+ return 0;
}
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 8dce86b..da1f6fa 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -26,7 +26,6 @@
#include <pc80/mc146818rtc.h>
#endif
#include <bcd.h>
-#include <fmap.h>
#include <rtc.h>
#include <smbios.h>
#include <spi-generic.h>
@@ -36,6 +35,7 @@
#include <elog.h>
#include "elog_internal.h"
+#include <vendorcode/google/chromeos/fmap.h>
#if !IS_ENABLED(CONFIG_CHROMEOS) && CONFIG_ELOG_FLASH_BASE == 0
#error "CONFIG_ELOG_FLASH_BASE is invalid"
@@ -86,6 +86,26 @@ static inline u32 get_rom_size(void)
}
/*
+ * Convert a memory mapped flash address into a flash offset
+ */
+static inline u32 elog_flash_address_to_offset(u8 *address)
+{
+#if CONFIG_ARCH_X86
+ /* For x86, assume address is memory-mapped near 4GB */
+ u32 rom_size;
+
+ if (!elog_spi)
+ return 0;
+
+ rom_size = get_rom_size();
+
+ return (u32)address - ((u32)~0UL - rom_size + 1);
+#else
+ return (u32)(uintptr_t)address;
+#endif
+}
+
+/*
* Pointer to an event log header in the event data area
*/
static inline struct event_header*
@@ -497,22 +517,21 @@ static void elog_find_flash(void)
{
elog_debug("elog_find_flash()\n");
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- /* Find the ELOG base and size in FMAP */
- struct region r;
-
- if (fmap_locate_area("RW_ELOG", &r) < 0) {
- printk(BIOS_WARNING,
- "ELOG: Unable to find RW_ELOG in FMAP\n");
- flash_base = total_size = 0;
- } else {
- flash_base = region_offset(&r);
- total_size = MIN(region_sz(&r), CONFIG_ELOG_AREA_SIZE);
- }
+#if CONFIG_CHROMEOS
+ /* Find the ELOG base and size in FMAP */
+ u8 *flash_base_ptr;
+ int fmap_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr);
+ if (fmap_size < 0) {
+ printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP\n");
+ flash_base = total_size = 0;
} else {
- flash_base = CONFIG_ELOG_FLASH_BASE;
- total_size = CONFIG_ELOG_AREA_SIZE;
+ flash_base = elog_flash_address_to_offset(flash_base_ptr);
+ total_size = MIN(fmap_size, CONFIG_ELOG_AREA_SIZE);
}
+#else
+ flash_base = CONFIG_ELOG_FLASH_BASE;
+ total_size = CONFIG_ELOG_AREA_SIZE;
+#endif
log_size = total_size - sizeof(struct elog_header);
full_threshold = log_size - ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE;
shrink_size = MIN(total_size * ELOG_SHRINK_PERCENTAGE / 100,
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
deleted file mode 100644
index 0848ea5..0000000
--- a/src/include/boot_device.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _BOOT_DEVICE_H_
-#define _BOOT_DEVICE_H_
-
-#include <region.h>
-
-/* Return the region_device for the read-only boot device. */
-const struct region_device *boot_device_ro(void);
-
-/*
- * Create a sub-region of the read-only boot device.
- * Returns 0 on success, < 0 on error.
- */
-int boot_device_ro_subregion(const struct region *sub,
- struct region_device *subrd);
-
-/*
- * Initialize the boot device. This may be called multiple times within
- * a stage so boot device implementations should account for this behavior.
- **/
-void boot_device_init(void);
-
-#endif /* _BOOT_DEVICE_H_ */
diff --git a/src/include/fmap.h b/src/include/fmap.h
deleted file mode 100644
index e575bbf..0000000
--- a/src/include/fmap.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _FMAP_H_
-#define _FMAP_H_
-
-#include <region.h>
-
-/* Locate the named area in the fmap and fill in a region device representing
- * that area. The region is a sub-region of the readonly boot media. Return
- * 0 on success, < 0 on error. */
-int fmap_locate_area_as_rdev(const char *name, struct region_device *area);
-
-/* Locate the named area in the fmap and fill in a region with the
- * offset and size of that area within the boot media. Return 0 on success,
- * < 0 on error. */
-int fmap_locate_area(const char *name, struct region *r);
-
-#endif
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE "__FMAP__"
-#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
-#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
-#define FMAP_STRLEN 32 /* maximum length for strings, */
- /* including null-terminator */
-
-enum fmap_flags {
- FMAP_AREA_STATIC = 1 << 0,
- FMAP_AREA_COMPRESSED = 1 << 1,
- FMAP_AREA_RO = 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
- uint32_t offset; /* offset relative to base */
- uint32_t size; /* size in bytes */
- uint8_t name[FMAP_STRLEN]; /* descriptive name */
- uint16_t flags; /* flags for this area */
-} __attribute__((packed));
-
-struct fmap {
- uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
- uint8_t ver_major; /* major version */
- uint8_t ver_minor; /* minor version */
- uint64_t base; /* address of the firmware binary */
- uint32_t size; /* size of firmware binary in bytes */
- uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
- uint16_t nareas; /* number of areas described by
- fmap_areas[] below */
- struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5ec9de7..11562bd 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -31,19 +31,15 @@ bootblock-y += memchr.c
bootblock-y += memcmp.c
bootblock-y += mem_pool.c
bootblock-y += region.c
-bootblock-y += boot_device.c
-bootblock-y += fmap.c
verstage-y += prog_ops.c
verstage-y += delay.c
verstage-y += cbfs.c
verstage-y += cbfs_core.c
verstage-y += halt.c
-verstage-y += fmap.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
verstage-y += region.c
-verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -64,7 +60,6 @@ $(foreach arch,$(ARCH_SUPPORTED),\
$(eval rmodules_$(arch)-y += memcmp.c) \
$(eval rmodules_$(arch)-y += rmodule.ld))
-romstage-y += fmap.c
romstage-$(CONFIG_I2C_TPM) += delay.c
romstage-y += cbfs.c cbfs_core.c
romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -92,7 +87,6 @@ ramstage-y += hardwaremain.c
ramstage-y += selfboot.c
ramstage-y += coreboot_table.c
ramstage-y += bootmem.c
-ramstage-y += fmap.c
ramstage-y += memchr.c
ramstage-y += memcmp.c
ramstage-y += malloc.c
@@ -147,12 +141,7 @@ ramstage-y += mem_pool.c
romstage-y += region.c
ramstage-y += region.c
-romstage-y += boot_device.c
-ramstage-y += boot_device.c
-smm-y += region.c
-smm-y += boot_device.c
-smm-y += fmap.c
smm-y += cbfs.c cbfs_core.c memcmp.c
smm-$(CONFIG_COMPILER_GCC) += gcc.c
diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c
deleted file mode 100644
index e0353fc..0000000
--- a/src/lib/boot_device.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-
-void __attribute__((weak)) boot_device_init(void)
-{
- /* Provide weak do-nothing init. */
-}
-
-int boot_device_ro_subregion(const struct region *sub,
- struct region_device *subrd)
-{
- const struct region_device *boot_dev;
-
- boot_dev = boot_device_ro();
-
- if (boot_dev == NULL)
- return -1;
-
- return rdev_chain(subrd, boot_dev, region_offset(sub), region_sz(sub));
-}
diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c
index 6758220..6c8d78d 100644
--- a/src/lib/cbfs_spi.c
+++ b/src/lib/cbfs_spi.c
@@ -23,52 +23,17 @@
* SPI.
*/
-#include <boot_device.h>
#include <cbfs.h>
-#include <region.h>
#include <spi_flash.h>
#include <symbols.h>
-static struct spi_flash *spi_flash_info;
-
-static ssize_t spi_readat(const struct region_device *rd, void *b,
- size_t offset, size_t size)
-{
- if (spi_flash_info->read(spi_flash_info, offset, size, b))
- return -1;
- return size;
-}
-
-static const struct region_device_ops spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = spi_readat,
+/* SPI flash as CBFS media. */
+struct cbfs_spi_context {
+ struct spi_flash *spi_flash_info;
+ struct cbfs_simple_buffer buffer;
};
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
-
-void boot_device_init(void)
-{
- int bus = CONFIG_BOOT_MEDIA_SPI_BUS;
- int cs = 0;
-
- if (spi_flash_info != NULL)
- return;
-
- spi_flash_info = spi_flash_probe(bus, cs);
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
-
-/* Return the CBFS boot device. */
-const struct region_device *boot_device_ro(void)
-{
- if (spi_flash_info == NULL)
- return NULL;
-
- return &mdev.rdev;
-}
+static struct cbfs_spi_context spi_context;
static int cbfs_media_open(struct cbfs_media *media)
{
@@ -84,58 +49,52 @@ static size_t cbfs_media_read(struct cbfs_media *media,
void *dest, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct cbfs_spi_context *context = media->context;
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ return context->spi_flash_info->read
+ (context->spi_flash_info, offset, count, dest) ? 0 : count;
}
static void *cbfs_media_map(struct cbfs_media *media,
size_t offset, size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
+ struct cbfs_spi_context *context = media->context;
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ return cbfs_simple_buffer_map(&context->buffer, media, offset, count);
}
static void *cbfs_media_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
+ struct cbfs_spi_context *context = media->context;
- return NULL;
+ return cbfs_simple_buffer_unmap(&context->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int init_cbfs_media_context(void)
{
- boot_device_init();
+ if (!spi_context.spi_flash_info) {
+
+ spi_context.spi_flash_info = spi_flash_probe
+ (CONFIG_BOOT_MEDIA_SPI_BUS, 0);
- media->context = (void *)boot_device_ro();
+ if (!spi_context.spi_flash_info)
+ return -1;
- if (media->context == NULL)
- return -1;
+ spi_context.buffer.buffer = (void *)_cbfs_cache;
+ spi_context.buffer.size = _cbfs_cache_size;
+ }
+ return 0;
+}
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ media->context = &spi_context;
media->open = cbfs_media_open;
media->close = cbfs_media_close;
media->read = cbfs_media_read;
media->map = cbfs_media_map;
media->unmap = cbfs_media_unmap;
- return 0;
+ return init_cbfs_media_context();
}
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
deleted file mode 100644
index 0f48cdc..0000000
--- a/src/lib/fmap.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012-2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-#include <console/console.h>
-#include <fmap.h>
-#include <fmap_serialized.h>
-#include <stddef.h>
-#include <string.h>
-
-/*
- * See http://code.google.com/p/flashmap/ for more information on FMAP.
- */
-
-static int find_fmap_directory(struct region_device *fmrd)
-{
- const struct region_device *boot;
- struct fmap *fmap;
- size_t fmap_size;
- size_t offset = CONFIG_FLASHMAP_OFFSET;
-
- boot_device_init();
- boot = boot_device_ro();
-
- if (boot == NULL)
- return -1;
-
- fmap_size = sizeof(struct fmap);
-
- fmap = rdev_mmap(boot, offset, fmap_size);
-
- if (fmap == NULL)
- return -1;
-
- if (memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature))) {
- printk(BIOS_DEBUG, "No FMAP found at %zx offset.\n", offset);
- rdev_munmap(boot, fmap);
- return -1;
- }
-
- printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
- fmap->name, fmap->ver_major, fmap->ver_minor, offset);
- printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
- (long long)fmap->base, fmap->size, fmap->nareas);
-
- fmap_size += fmap->nareas * sizeof(struct fmap_area);
-
- rdev_munmap(boot, fmap);
-
- return rdev_chain(fmrd, boot, offset, fmap_size);
-}
-
-int fmap_locate_area_as_rdev(const char *name, struct region_device *area)
-{
- struct region ar;
-
- if (fmap_locate_area(name, &ar))
- return -1;
-
- return boot_device_ro_subregion(&ar, area);
-}
-
-int fmap_locate_area(const char *name, struct region *ar)
-{
- struct region_device fmrd;
- size_t offset;
-
- if (find_fmap_directory(&fmrd))
- return -1;
-
- /* Start reading the areas just after fmap header. */
- offset = sizeof(struct fmap);
-
- while (1) {
- struct fmap_area *area;
-
- area = rdev_mmap(&fmrd, offset, sizeof(*area));
-
- if (area == NULL)
- return -1;
-
- if (strcmp((const char *)area->name, name)) {
- rdev_munmap(&fmrd, area);
- offset += sizeof(struct fmap_area);
- continue;
- }
-
- printk(BIOS_DEBUG, "FMAP: area %s found\n", name);
- printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset);
- printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size);
-
- ar->offset = area->offset;
- ar->size = area->size;
-
- rdev_munmap(&fmrd, area);
-
- return 0;
- }
-
- printk(BIOS_DEBUG, "FMAP: area %s not found\n", name);
-
- return -1;
-}
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index e0f2251..8c71263 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -12,20 +12,12 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
-/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
+/* Simple memory-mapped ROM emulation. */
static int emu_rom_open(struct cbfs_media *media)
{
@@ -34,40 +26,26 @@ static int emu_rom_open(struct cbfs_media *media)
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ if (offset + count > CONFIG_ROM_SIZE)
+ return (void *)-1;
+ return (void*)(offset + 0x10000);
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ void *ptr = emu_rom_map(media, offset, count);
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
+ if (ptr == (void *)-1)
return 0;
+ memcpy(dest, ptr, count);
+ emu_rom_unmap(media, ptr);
return count;
}
@@ -76,11 +54,10 @@ static int emu_rom_close(struct cbfs_media *media)
return 0;
}
-static int init_emu_rom_cbfs_media(struct cbfs_media *media)
-{
- boot_device_init();
+int init_emu_rom_cbfs_media(struct cbfs_media *media);
- media->context = (void *)boot_device_ro();
+int init_emu_rom_cbfs_media(struct cbfs_media *media)
+{
media->open = emu_rom_open;
media->close = emu_rom_close;
media->map = emu_rom_map;
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index e09336d..bd2fbd5 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -20,13 +20,11 @@
#include <types.h>
#include <string.h>
-#include <cbfs.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <fmap.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
@@ -38,6 +36,11 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/ene_kb3940q/ec.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#else
+#include <cbfs.h>
+#endif
static unsigned int search(char *p, char *a, unsigned int lengthp,
unsigned int lengtha)
@@ -197,30 +200,20 @@ static void mainboard_init(device_t dev)
size_t search_length = -1;
u16 io_base = 0;
struct device *ethernet_dev = NULL;
- void *vpd_file;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
- vpd_file = rdev_mmap_full(&rdev);
-
- if (vpd_file != NULL) {
- search_length = region_device_sz(&rdev);
- search_address = (uintptr_t)vpd_file;
- }
- }
+#if CONFIG_CHROMEOS
+ char **vpd_region_ptr = NULL;
+ search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
+ search_address = (unsigned long)(*vpd_region_ptr);
+#else
+ void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
+ CBFS_TYPE_RAW, &search_length);
+ if (vpd_file) {
+ search_address = (unsigned long)vpd_file;
} else {
- vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "vpd.bin", CBFS_TYPE_RAW,
- &search_length);
- if (vpd_file) {
- search_address = (unsigned long)vpd_file;
- } else {
- search_length = -1;
- search_address = 0;
- }
+ search_length = -1;
+ search_address = 0;
}
+#endif
/* Initialize the Embedded Controller */
butterfly_ec_init();
diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c
index 8a648cb..9fd325f 100644
--- a/src/mainboard/google/panther/lan.c
+++ b/src/mainboard/google/panther/lan.c
@@ -24,8 +24,8 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fmap.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/fmap.h>
#include "onboard.h"
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
@@ -117,24 +117,15 @@ static void program_mac_address(u16 io_base)
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
- search_address = rdev_mmap_full(&rdev);
-
- if (search_address != NULL)
- search_length = region_device_sz(&rdev);
- }
- } else {
- search_address = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "vpd.bin",
- CBFS_TYPE_RAW,
- &search_length);
- }
+#if CONFIG_CHROMEOS
+ search_length = find_fmap_entry("RO_VPD", &search_address);
+#else
+ search_address = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
+ CBFS_TYPE_RAW, &search_length);
+#endif
if (search_length <= 0)
- printk(BIOS_ERR, "LAN: VPD not found.\n");
+ printk(BIOS_ERR, "LAN: find_fmap_entry returned -1.\n");
else
get_mac_address(&high_dword, &low_dword, search_address,
search_length);
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index d72c2c3..3bb7fa5 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -22,7 +22,6 @@
#include <bootstate.h>
#include <console/console.h>
#include <cbfs.h>
-#include <fmap.h>
#include <ip_checksum.h>
#include <device/device.h>
#include <cbmem.h>
@@ -30,6 +29,9 @@
#include "haswell.h"
#include <spi-generic.h>
#include <spi_flash.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
/* convert a pointer to flash area into the offset inside the flash */
static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
@@ -64,22 +66,16 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
*/
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- size_t region_size = 0;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
- region_size = region_device_sz(&rdev);
- *mrc_region_ptr = rdev_mmap_full(&rdev);
- }
- } else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
- }
+#if CONFIG_CHROMEOS
+ return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
+#else
+ size_t region_size;
+ *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ "mrc.cache",
+ CBFS_TYPE_MRC_CACHE,
+ ®ion_size);
return region_size;
+#endif
}
/*
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e17c54b..e5f74e8 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -22,7 +22,6 @@
#include <bootstate.h>
#include <console/console.h>
#include <cbfs.h>
-#include <fmap.h>
#include <ip_checksum.h>
#include <device/device.h>
#include <cbmem.h>
@@ -30,6 +29,9 @@
#include "sandybridge.h"
#include <spi-generic.h>
#include <spi_flash.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
/* convert a pointer to flash area into the offset inside the flash */
static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
@@ -64,22 +66,17 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
*/
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- size_t region_size = 0;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
- region_size = region_device_sz(&rdev);
- *mrc_region_ptr = rdev_mmap_full(&rdev);
- }
- } else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
- }
+#if CONFIG_CHROMEOS
+ return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
+#else
+ size_t region_size;
+ *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ "mrc.cache",
+ CBFS_TYPE_MRC_CACHE,
+ ®ion_size);
return region_size;
+#endif
+
}
/*
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 6783f18..9366aa5 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -20,8 +20,10 @@
#include <string.h>
#include <console/console.h>
#include <cbmem.h>
-#include <fmap.h>
#include <ip_checksum.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
#include "mrc_cache.h"
#define MRC_DATA_ALIGN 0x1000
@@ -37,23 +39,16 @@ struct mrc_data_region {
/* common code */
static int mrc_cache_get_region(struct mrc_data_region *region)
{
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev))
- return -1;
-
- region->size = region_device_sz(&rdev);
- region->base = rdev_mmap_full(&rdev);
-
- if (region->base == NULL)
- return -1;
-
+#if CONFIG_CHROMEOS
+ int ret;
+ ret = find_fmap_entry("RW_MRC_CACHE", ®ion->base);
+ if (ret >= 0) {
+ region->size = ret;
return 0;
- } else {
- region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE;
- region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE;
}
+#endif
+ region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE;
+ region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE;
return 0;
}
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..78054f4 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_NVIDIA_TEGRA124),y)
bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
+bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += dma.c
bootblock-y += i2c.c
@@ -21,6 +22,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
verstage-y += verstage.c
+verstage-y += cbfs.c
verstage-y += dma.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
@@ -32,6 +34,7 @@ verstage-y += clock.c
verstage-y += i2c.c
verstage-y += cache.c
+romstage-y += cbfs.c
romstage-y += cbmem.c
romstage-y += clock.c
romstage-y += dma.c
@@ -48,6 +51,7 @@ romstage-y += ../tegra/pinmux.c
romstage-y += cache.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += cbfs.c
ramstage-y += cbmem.c
ramstage-y += clock.c
ramstage-y += display.c
diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c
new file mode 100644
index 0000000..d82ca9a
--- /dev/null
+++ b/src/soc/nvidia/tegra124/cbfs.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <soc/spi.h>
+#include <symbols.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return initialize_tegra_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h
index cfa3cd2..ab04632 100644
--- a/src/soc/nvidia/tegra124/include/soc/spi.h
+++ b/src/soc/nvidia/tegra124/include/soc/spi.h
@@ -61,6 +61,11 @@ struct tegra_spi_channel {
enum spi_xfer_mode xfer_mode;
};
+struct cbfs_media;
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+
struct tegra_spi_channel *tegra_spi_init(unsigned int bus);
#endif /* __NVIDIA_TEGRA124_SPI_H__ */
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 0cf5495..683edd1 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -21,7 +21,6 @@
#include <arch/cache.h>
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <console/console.h>
#include <cbfs.h>
#include <delay.h>
@@ -34,7 +33,6 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#include <timer.h>
@@ -802,6 +800,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
+/* SPI as CBFS media. */
+struct tegra_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
static int tegra_spi_cbfs_open(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_open\n");
@@ -819,17 +823,16 @@ static int tegra_spi_cbfs_close(struct cbfs_media *media)
#define JEDEC_FAST_READ_DUAL 0x3b
#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context;
u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
unsigned int read_cmd_bytes;
int ret = count;
struct tegra_spi_channel *channel;
- channel = to_tegra_spi(boot_slave->bus);
+ channel = to_tegra_spi(spi->slave->bus);
if (channel->dual_mode) {
/*
@@ -850,9 +853,9 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
- spi_claim_bus(boot_slave);
+ spi_claim_bus(spi->slave);
- if (spi_xfer(boot_slave, spi_read_cmd,
+ if (spi_xfer(spi->slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
@@ -863,7 +866,7 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
if (channel->dual_mode) {
setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
}
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
+ if (spi_xfer(spi->slave, NULL, 0, dest, count)) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
__func__, count);
@@ -873,70 +876,56 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
-static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count)
-{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- printk(BIOS_ERR, "%s: reading %zx bytes from %zx\n",
- __func__, count, offset);
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ spi_release_bus(spi->slave);
+ return (ret < 0) ? 0 : ret;
}
static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
void *map;
-
DEBUG_SPI("tegra_spi_cbfs_map\n");
-
- boot_dev = media->context;
-
- map = rdev_mmap(boot_dev, offset, count);
-
- if (map == NULL)
- map = (void *)-1;
-
+ map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
return map;
}
static void *tegra_spi_cbfs_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
DEBUG_SPI("tegra_spi_cbfs_unmap\n");
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
- return NULL;
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- DEBUG_SPI("Initializing CBFS media on SPI\n");
+ // TODO Replace static variable to support multiple streams.
+ static struct tegra_spi_media context;
+ static struct tegra_spi_channel *channel;
+
+ channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
+ channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
- boot_device_init();
+ DEBUG_SPI("Initializing CBFS media on SPI\n");
- media->context = (void *)boot_device_ro();
+ context.slave = &channel->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
media->open = tegra_spi_cbfs_open;
media->close = tegra_spi_cbfs_close;
media->read = tegra_spi_cbfs_read;
media->map = tegra_spi_cbfs_map;
media->unmap = tegra_spi_cbfs_unmap;
+#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
+ channel->dual_mode = 1;
+#endif
+
return 0;
}
@@ -948,32 +937,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..365dab3 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y)
bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
+bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += spi.c
bootblock-y += i2c.c
@@ -22,6 +23,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
verstage-y += verstage.c
+verstage-y += cbfs.c
verstage-y += dma.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
@@ -37,6 +39,7 @@ verstage-y += i2c.c
romstage-y += 32bit_reset.S
romstage-y += romstage_asm.S
romstage-y += addressmap.c
+romstage-y += cbfs.c
romstage-y += cbmem.c
romstage-y += ccplex.c
romstage-y += clock.c
@@ -60,6 +63,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += 32bit_reset.S
ramstage-y += addressmap.c
+ramstage-y += cbfs.c
ramstage-y += cbmem.c
ramstage-y += cpu.c
ramstage-y += cpu_lib.S
diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c
new file mode 100644
index 0000000..7aeb59b
--- /dev/null
+++ b/src/soc/nvidia/tegra132/cbfs.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <soc/spi.h>
+#include <symbols.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return initialize_tegra_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/spi.h b/src/soc/nvidia/tegra132/include/soc/spi.h
index 4c91c27..2fd9562 100644
--- a/src/soc/nvidia/tegra132/include/soc/spi.h
+++ b/src/soc/nvidia/tegra132/include/soc/spi.h
@@ -62,6 +62,11 @@ struct tegra_spi_channel {
enum spi_xfer_mode xfer_mode;
};
+struct cbfs_media;
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+
struct tegra_spi_channel *tegra_spi_init(unsigned int bus);
#endif /* __NVIDIA_TEGRA132_SPI_H__ */
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index 1650057..7ca66e1 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -21,7 +21,6 @@
#include <arch/cache.h>
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
#include <delay.h>
@@ -34,7 +33,6 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#include <timer.h>
@@ -817,6 +815,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
+/* SPI as CBFS media. */
+struct tegra_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
static int tegra_spi_cbfs_open(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_open\n");
@@ -834,17 +838,16 @@ static int tegra_spi_cbfs_close(struct cbfs_media *media)
#define JEDEC_FAST_READ_DUAL 0x3b
#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context;
u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
unsigned int read_cmd_bytes;
int ret = count;
struct tegra_spi_channel *channel;
- channel = to_tegra_spi(boot_slave->bus);
+ channel = to_tegra_spi(spi->slave->bus);
if (channel->dual_mode) {
/*
@@ -865,9 +868,9 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
- spi_claim_bus(boot_slave);
+ spi_claim_bus(spi->slave);
- if (spi_xfer(boot_slave, spi_read_cmd,
+ if (spi_xfer(spi->slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n",
@@ -878,7 +881,7 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
if (channel->dual_mode) {
setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
}
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
+ if (spi_xfer(spi->slave, NULL, 0, dest, count)) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n",
__func__, count);
@@ -888,70 +891,56 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
-static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count)
-{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- DEBUG_SPI("%s: reading %zx bytes from %zx\n", __func__, count, offset);
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ spi_release_bus(spi->slave);
+ return (ret < 0) ? 0 : ret;
}
static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
void *map;
-
DEBUG_SPI("tegra_spi_cbfs_map\n");
-
- boot_dev = media->context;
-
- map = rdev_mmap(boot_dev, offset, count);
-
- if (map == NULL)
- map = (void *)-1;
-
+ map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
return map;
}
static void *tegra_spi_cbfs_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
DEBUG_SPI("tegra_spi_cbfs_unmap\n");
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
- return NULL;
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- DEBUG_SPI("Initializing CBFS media on SPI\n");
+ // TODO Replace static variable to support multiple streams.
+ static struct tegra_spi_media context;
+ static struct tegra_spi_channel *channel;
+
+ channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
+ channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
- boot_device_init();
+ DEBUG_SPI("Initializing CBFS media on SPI\n");
- media->context = (void *)boot_device_ro();
+ context.slave = &channel->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
media->open = tegra_spi_cbfs_open;
media->close = tegra_spi_cbfs_close;
media->read = tegra_spi_cbfs_read;
media->map = tegra_spi_cbfs_map;
media->unmap = tegra_spi_cbfs_unmap;
+#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
+ channel->dual_mode = 1;
+#endif
+
return 0;
}
@@ -963,32 +952,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index 546018a..2e2aeec 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -19,7 +19,6 @@
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <console/console.h>
#include <soc/alternate_cbfs.h>
@@ -46,7 +45,7 @@
* rest of the firmware's lifetime and all subsequent stages (which will not
* have __PRE_RAM__ defined) can just directly reference it there.
*/
-static int usb_cbfs_open(void)
+static int usb_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
static int first_run = 1;
@@ -81,7 +80,7 @@ static int usb_cbfs_open(void)
* this seems like a safer approach. It also makes it easy to pass our image
* down to payloads.
*/
-static int sdmmc_cbfs_open(void)
+static int sdmmc_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
/*
@@ -112,109 +111,66 @@ static int sdmmc_cbfs_open(void)
return 0;
}
-static int exynos_cbfs_open(struct cbfs_media *media) {
- return 0;
-}
-
-static int exynos_cbfs_close(struct cbfs_media *media) {
- return 0;
-}
-
-static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ memcpy(dest, _cbfs_cache + offset, count);
return count;
}
-static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset,
- size_t count) {
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ return _cbfs_cache + offset;
}
-static void *exynos_cbfs_unmap(struct cbfs_media *media,
- const void *address) {
- const struct region_device *boot_dev;
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
- boot_dev = media->context;
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- rdev_munmap(boot_dev, (void *)address);
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
- return NULL;
+ return 0;
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
- return -1;
-
- media->open = exynos_cbfs_open;
- media->close = exynos_cbfs_close;
- media->read = exynos_cbfs_read;
- media->map = exynos_cbfs_map;
- media->unmap = exynos_cbfs_unmap;
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
return 0;
}
-static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0);
-
-const struct region_device *boot_device_ro(void)
+int init_default_cbfs_media(struct cbfs_media *media)
{
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
- return &alternate_rdev.rdev;
-
- switch (exynos_power->om_stat & OM_STAT_MASK) {
- case OM_STAT_SDMMC:
- return &alternate_rdev.rdev;
- case OM_STAT_SPI:
- return exynos_spi_boot_device();
- default:
- printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
- exynos_power->om_stat);
- return NULL;
- }
-}
-
-void boot_device_init(void)
-{
- mem_region_device_init(&alternate_rdev, _cbfs_cache, _cbfs_cache_size);
-
- if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- usb_cbfs_open();
- return;
- }
+ return initialize_exynos_usb_cbfs_media(media);
switch (exynos_power->om_stat & OM_STAT_MASK) {
case OM_STAT_SDMMC:
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- sdmmc_cbfs_open();
- break;
+ return initialize_exynos_sdmmc_cbfs_media(media);
case OM_STAT_SPI:
- exynos_init_spi_boot_device();
- break;
+ return initialize_exynos_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
default:
printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
exynos_power->om_stat);
+ return 1;
}
}
diff --git a/src/soc/samsung/exynos5250/include/soc/spi.h b/src/soc/samsung/exynos5250/include/soc/spi.h
index 298db1a..92236ae 100644
--- a/src/soc/samsung/exynos5250/include/soc/spi.h
+++ b/src/soc/samsung/exynos5250/include/soc/spi.h
@@ -20,7 +20,8 @@
#ifndef CPU_SAMSUNG_EXYNOS5250_SPI_H
#define CPU_SAMSUNG_EXYNOS5250_SPI_H
-#include <boot_device.h>
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
@@ -91,6 +92,8 @@ int exynos_spi_open(struct exynos_spi *regs);
int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off);
int exynos_spi_close(struct exynos_spi *regs);
-void exynos_init_spi_boot_device(void);
-const struct region_device *exynos_spi_boot_device(void);
+/* Serve as CBFS media source */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
#endif
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c
index adf31e4..4f32487 100644
--- a/src/soc/samsung/exynos5250/spi.c
+++ b/src/soc/samsung/exynos5250/spi.c
@@ -20,13 +20,11 @@
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <console/console.h>
#include <soc/clk.h>
#include <soc/gpio.h>
#include <soc/spi.h>
#include <stdlib.h>
-#include <symbols.h>
#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x)
@@ -146,47 +144,70 @@ int exynos_spi_close(struct exynos_spi *regs)
return 0;
}
-static struct exynos_spi *boot_slave_regs;
+// SPI as CBFS media.
+struct exynos_spi_media {
+ struct exynos_spi *regs;
+ struct cbfs_simple_buffer buffer;
+};
-static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
-{
+static int exynos_spi_cbfs_open(struct cbfs_media *media) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_open\n");
+ return exynos_spi_open(spi->regs);
+}
+
+static int exynos_spi_cbfs_close(struct cbfs_media *media) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_close\n");
+ return exynos_spi_close(spi->regs);
+}
+
+static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
int bytes;
DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
- exynos_spi_open(boot_slave_regs);
- bytes = exynos_spi_read(boot_slave_regs, dest, count, offset);
- exynos_spi_close(boot_slave_regs);
+ bytes = exynos_spi_read(spi->regs, dest, count, offset);
+ // Flush and re-open the device.
+ exynos_spi_close(spi->regs);
+ exynos_spi_open(spi->regs);
return bytes;
}
-static void *exynos_spi_map(const struct region_device *rdev,
- size_t offset, size_t count)
-{
+static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
DEBUG_SPI("exynos_spi_cbfs_map\n");
- // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
- // requires buffer memory address to be aligned.
+ // See exynos_spi_rx_tx for I/O alignment limitation.
if (count % 4)
count += 4 - (count % 4);
- return mmap_helper_rdev_mmap(rdev, offset, count);
+ return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
}
-static const struct region_device_ops exynos_spi_ops = {
- .mmap = exynos_spi_map,
- .munmap = mmap_helper_rdev_munmap,
- .readat = exynos_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE);
-
-void exynos_init_spi_boot_device(void)
-{
- boot_slave_regs = (void *)EXYNOS5_SPI1_BASE;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+static void *exynos_spi_cbfs_unmap(struct cbfs_media *media,
+ const void *address) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_unmap\n");
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-const struct region_device *exynos_spi_boot_device(void)
-{
- return &mdev.rdev;
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size) {
+ // TODO Replace static variable to support multiple streams.
+ static struct exynos_spi_media context;
+ DEBUG_SPI("initialize_exynos_spi_cbfs_media\n");
+
+ context.regs = (void*)EXYNOS5_SPI1_BASE;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
+ media->open = exynos_spi_cbfs_open;
+ media->close = exynos_spi_cbfs_close;
+ media->read = exynos_spi_cbfs_read;
+ media->map = exynos_spi_cbfs_map;
+ media->unmap = exynos_spi_cbfs_unmap;
+
+ return 0;
}
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c
index 9bba748..b30ed6b 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.c
@@ -20,7 +20,6 @@
#include <arch/cache.h>
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <console/console.h>
#include <soc/alternate_cbfs.h>
@@ -47,7 +46,7 @@
* rest of the firmware's lifetime and all subsequent stages (which will not
* have __PRE_RAM__ defined) can just directly reference it there.
*/
-static int usb_cbfs_open(void)
+static int usb_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
static int first_run = 1;
@@ -85,7 +84,7 @@ static int usb_cbfs_open(void)
* this seems like a safer approach. It also makes it easy to pass our image
* down to payloads.
*/
-static int sdmmc_cbfs_open(void)
+static int sdmmc_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
/*
@@ -119,109 +118,66 @@ static int sdmmc_cbfs_open(void)
return 0;
}
-static int exynos_cbfs_open(struct cbfs_media *media) {
- return 0;
-}
-
-static int exynos_cbfs_close(struct cbfs_media *media) {
- return 0;
-}
-
-static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ memcpy(dest, _cbfs_cache + offset, count);
return count;
}
-static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset,
- size_t count) {
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ return _cbfs_cache + offset;
}
-static void *exynos_cbfs_unmap(struct cbfs_media *media,
- const void *address) {
- const struct region_device *boot_dev;
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
- boot_dev = media->context;
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- rdev_munmap(boot_dev, (void *)address);
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
- return NULL;
+ return 0;
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
- return -1;
-
- media->open = exynos_cbfs_open;
- media->close = exynos_cbfs_close;
- media->read = exynos_cbfs_read;
- media->map = exynos_cbfs_map;
- media->unmap = exynos_cbfs_unmap;
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
return 0;
}
-static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0);
-
-const struct region_device *boot_device_ro(void)
+int init_default_cbfs_media(struct cbfs_media *media)
{
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
- return &alternate_rdev.rdev;
-
- switch (exynos_power->om_stat & OM_STAT_MASK) {
- case OM_STAT_SDMMC:
- return &alternate_rdev.rdev;
- case OM_STAT_SPI:
- return exynos_spi_boot_device();
- default:
- printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
- exynos_power->om_stat);
- return NULL;
- }
-}
-
-void boot_device_init(void)
-{
- mem_region_device_init(&alternate_rdev, _cbfs_cache, _cbfs_cache_size);
-
- if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- usb_cbfs_open();
- return;
- }
+ return initialize_exynos_usb_cbfs_media(media);
switch (exynos_power->om_stat & OM_STAT_MASK) {
case OM_STAT_SDMMC:
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- sdmmc_cbfs_open();
- break;
+ return initialize_exynos_sdmmc_cbfs_media(media);
case OM_STAT_SPI:
- exynos_init_spi_boot_device();
- break;
+ return initialize_exynos_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
default:
printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
exynos_power->om_stat);
+ return 1;
}
}
diff --git a/src/soc/samsung/exynos5420/include/soc/spi.h b/src/soc/samsung/exynos5420/include/soc/spi.h
index 77d5ffc..cf77800 100644
--- a/src/soc/samsung/exynos5420/include/soc/spi.h
+++ b/src/soc/samsung/exynos5420/include/soc/spi.h
@@ -20,7 +20,8 @@
#ifndef CPU_SAMSUNG_EXYNOS5420_SPI_H
#define CPU_SAMSUNG_EXYNOS5420_SPI_H
-#include <boot_device.h>
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
@@ -90,6 +91,8 @@ check_member(exynos_spi, fb_clk, 0x2c);
#define SPI_RX_BYTE_SWAP (1 << 6)
#define SPI_RX_HWORD_SWAP (1 << 7)
-void exynos_init_spi_boot_device(void);
-const struct region_device *exynos_spi_boot_device(void);
+/* Serve as CBFS media source */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
#endif
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 2edc337..5f29803 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -26,7 +26,6 @@
#include <spi_flash.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535)
@@ -243,43 +242,76 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
return len;
}
-static struct exynos_spi_slave *boot_slave;
+// SPI as CBFS media.
+struct exynos_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
+static int exynos_spi_cbfs_open(struct cbfs_media *media)
+{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_open\n");
+ return spi_claim_bus(spi->slave);
+}
+
+static int exynos_spi_cbfs_close(struct cbfs_media *media)
+{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_close\n");
+ spi_release_bus(spi->slave);
+ return 0;
+}
-static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ int bytes;
DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
- return exynos_spi_read(&boot_slave->slave, dest, count, offset);
+ bytes = exynos_spi_read(spi->slave, dest, count, offset);
+ return bytes;
}
-static void *exynos_spi_map(const struct region_device *rdev,
- size_t offset, size_t count)
+static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
DEBUG_SPI("exynos_spi_cbfs_map\n");
// exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
// requires buffer memory address to be aligned.
if (count % 4)
count += 4 - (count % 4);
- return mmap_helper_rdev_mmap(rdev, offset, count);
+ return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
}
-static const struct region_device_ops exynos_spi_ops = {
- .mmap = exynos_spi_map,
- .munmap = mmap_helper_rdev_munmap,
- .readat = exynos_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE);
-
-void exynos_init_spi_boot_device(void)
+static void *exynos_spi_cbfs_unmap(struct cbfs_media *media,
+ const void *address)
{
- boot_slave = &exynos_spi_slaves[1];
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_unmap\n");
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-const struct region_device *exynos_spi_boot_device(void)
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- return &mdev.rdev;
+ // TODO Replace static variable to support multiple streams.
+ static struct exynos_spi_media context;
+ static struct exynos_spi_slave *eslave = &exynos_spi_slaves[1];
+ DEBUG_SPI("initialize_exynos_spi_cbfs_media\n");
+
+ context.slave = &eslave->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
+ media->open = exynos_spi_cbfs_open;
+ media->close = exynos_spi_cbfs_close;
+ media->read = exynos_spi_cbfs_read;
+ media->map = exynos_spi_cbfs_map;
+ media->unmap = exynos_spi_cbfs_unmap;
+
+ return 0;
}
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 0b0b862..0fc0d54 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -94,6 +94,15 @@ config CHROMEOS_RAMOOPS_RAM_SIZE
default 0x00100000
depends on CHROMEOS_RAMOOPS
+config FLASHMAP_OFFSET
+ hex "Flash Map Offset"
+ default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default CBFS_SIZE if !ARCH_X86
+ default 0
+ help
+ Offset of flash map in firmware image
+
config EC_SOFTWARE_SYNC
bool "Enable EC software sync"
default n
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index df24435..6e416ee 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -34,7 +34,11 @@ ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
+verstage-y += fmap.c
+romstage-y += fmap.c
+ramstage-y += fmap.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
+smm-y += fmap.c
romstage-y += vpd_decode.c cros_vpd.c
ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c
ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),)
diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c
index fed1d82..c0e4830 100644
--- a/src/vendorcode/google/chromeos/cros_vpd.c
+++ b/src/vendorcode/google/chromeos/cros_vpd.c
@@ -6,11 +6,12 @@
#include <console/console.h>
-#include <fmap.h>
+#include <cbfs.h>
#include <stdlib.h>
#include <string.h>
#include "cros_vpd.h"
+#include "fmap.h"
#include "lib_vpd.h"
#include "vpd_tables.h"
@@ -34,7 +35,9 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size)
MAYBE_STATIC int result = -1;
struct google_vpd_info info;
int32_t base;
- struct region_device vpd;
+
+ const struct fmap_area *area;
+ struct cbfs_media media;
if (cached) {
*vpd_address = cached_address;
@@ -43,31 +46,32 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size)
}
cached = 1;
- if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) {
+ area = find_fmap_area(fmap_find(), "RO_VPD");
+ if (!area) {
printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__);
return result;
}
-
- base = 0;
- cached_size = region_device_sz(&vpd);
-
- if ((cached_size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) ||
- rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
- cached_size - GOOGLE_VPD_2_0_OFFSET)) {
+ if (area->size <= GOOGLE_VPD_2_0_OFFSET + sizeof(info)) {
printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n",
- __func__, cached_size);
+ __func__, area->size);
return result;
}
+ base = area->offset + GOOGLE_VPD_2_0_OFFSET;
+ cached_size = area->size - GOOGLE_VPD_2_0_OFFSET;
+ init_default_cbfs_media(&media);
+ media.open(&media);
+
/* Try if we can find a google_vpd_info, otherwise read whole VPD. */
- if (rdev_readat(&vpd, &info, base, sizeof(info)) == sizeof(info) &&
+ if (media.read(&media, &info, base, sizeof(info)) == sizeof(info) &&
memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic))
== 0 && cached_size >= info.size + sizeof(info)) {
base += sizeof(info);
cached_size = info.size;
}
- cached_address = rdev_mmap(&vpd, base, cached_size);
+ cached_address = media.map(&media, base, cached_size);
+ media.close(&media);
if (cached_address) {
*vpd_address = cached_address;
*vpd_size = cached_size;
diff --git a/src/vendorcode/google/chromeos/fmap.h b/src/vendorcode/google/chromeos/fmap.h
new file mode 100644
index 0000000..05d3fb6
--- /dev/null
+++ b/src/vendorcode/google/chromeos/fmap.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_LIB_FMAP_H__
+#define FLASHMAP_LIB_FMAP_H__
+
+#include <stdint.h>
+
+#define FMAP_REVERSED_SIGNATURE "__PAMF__" /* avoid magic number in .rodata */
+#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
+#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
+#define FMAP_STRLEN 32 /* maximum length for strings, */
+ /* including null-terminator */
+
+enum fmap_flags {
+ FMAP_AREA_STATIC = 1 << 0,
+ FMAP_AREA_COMPRESSED = 1 << 1,
+ FMAP_AREA_RO = 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+ uint32_t offset; /* offset relative to base */
+ uint32_t size; /* size in bytes */
+ uint8_t name[FMAP_STRLEN]; /* descriptive name */
+ uint16_t flags; /* flags for this area */
+} __attribute__((packed));
+
+struct fmap {
+ uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
+ uint8_t ver_major; /* major version */
+ uint8_t ver_minor; /* minor version */
+ uint64_t base; /* address of the firmware binary */
+ uint32_t size; /* size of firmware binary in bytes */
+ uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
+ uint16_t nareas; /* number of areas described by
+ fmap_areas[] below */
+ struct fmap_area areas[];
+} __attribute__((packed));
+
+
+/* coreboot specific function prototypes */
+const struct fmap *fmap_find(void);
+const struct fmap_area *find_fmap_area(const struct fmap *fmap,
+ const char name[]);
+int find_fmap_entry(const char name[], void **pointer);
+#endif /* FLASHMAP_LIB_FMAP_H__*/
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index 955d72f..6b3d7dc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -26,13 +26,13 @@
#include <cbmem.h>
#include <console/console.h>
#include <console/vtxprintf.h>
-#include <fmap.h>
#include <stdlib.h>
#include <timestamp.h>
#define NEED_VB20_INTERNALS /* TODO: remove me! */
#include <vb2_api.h>
#include <vboot_struct.h>
#include "../chromeos.h"
+#include "../fmap.h"
#include "../vboot_handoff.h"
#include "misc.h"
1
0
New patch to review for coreboot: 925ab0c Revert fmap and boot_device commits
by Vladimir Serbinenko 28 May '15
by Vladimir Serbinenko 28 May '15
28 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10350
-gerrit
commit 925ab0c60b0c7ae78f0ac384f475a60b3928e304
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 28 14:24:09 2015 +0200
Revert fmap and boot_device commits
Those commits miss tseg_relocate somewhere and so SMI hangs on shutdown.
Revert the commit until we figure out where is the mistake or switch
sandy/ivy/nehalem to SMM modules (preffered)
This reverts commit 0424c95a6dafdb65070538d6c5aa394b75eb9850.
This reverts commit c6588c5af94e568bddd8111c3fca736f464042cf.
Change-Id: I1e330c2730092e9b81d98ee861605bc32a6a7ab3
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/Kconfig | 9 --
src/arch/riscv/rom_media.c | 66 ++++++------
src/arch/x86/lib/Makefile.inc | 3 -
src/arch/x86/lib/mmap_boot.c | 31 ------
src/arch/x86/lib/rom_media.c | 57 +++++-----
src/cpu/allwinner/a10/bootblock_media.c | 8 +-
src/cpu/ti/am335x/bootblock_media.c | 47 ++------
src/cpu/ti/am335x/nand.c | 10 +-
src/drivers/elog/elog.c | 49 ++++++---
src/include/boot_device.h | 41 -------
src/include/fmap.h | 35 ------
src/include/fmap_serialized.h | 73 -------------
src/lib/Makefile.inc | 11 --
src/lib/boot_device.c | 38 -------
src/lib/cbfs_spi.c | 97 +++++------------
src/lib/fmap.c | 119 ---------------------
src/mainboard/emulation/qemu-armv7/media.c | 45 ++------
src/mainboard/google/butterfly/mainboard.c | 41 +++----
src/mainboard/google/panther/lan.c | 25 ++---
src/northbridge/intel/haswell/mrccache.c | 28 +++--
src/northbridge/intel/sandybridge/mrccache.c | 29 +++--
src/soc/intel/common/mrc_cache.c | 27 ++---
src/soc/nvidia/tegra124/Makefile.inc | 4 +
src/soc/nvidia/tegra124/cbfs.c | 29 +++++
src/soc/nvidia/tegra124/include/soc/spi.h | 5 +
src/soc/nvidia/tegra124/spi.c | 116 +++++++-------------
src/soc/nvidia/tegra132/Makefile.inc | 4 +
src/soc/nvidia/tegra132/cbfs.c | 28 +++++
src/soc/nvidia/tegra132/include/soc/spi.h | 5 +
src/soc/nvidia/tegra132/spi.c | 116 +++++++-------------
src/soc/samsung/exynos5250/alternate_cbfs.c | 118 +++++++-------------
src/soc/samsung/exynos5250/include/soc/spi.h | 9 +-
src/soc/samsung/exynos5250/spi.c | 85 +++++++++------
src/soc/samsung/exynos5420/alternate_cbfs.c | 118 +++++++-------------
src/soc/samsung/exynos5420/include/soc/spi.h | 9 +-
src/soc/samsung/exynos5420/spi.c | 78 ++++++++++----
src/vendorcode/google/chromeos/Kconfig | 9 ++
src/vendorcode/google/chromeos/Makefile.inc | 4 +
src/vendorcode/google/chromeos/cros_vpd.c | 30 +++---
src/vendorcode/google/chromeos/fmap.h | 79 ++++++++++++++
.../google/chromeos/vboot2/vboot_handoff.c | 2 +-
41 files changed, 665 insertions(+), 1072 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 26e1194..5cfb06f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -244,15 +244,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
-config FLASHMAP_OFFSET
- hex "Flash Map Offset"
- default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
- default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
- default CBFS_SIZE if !ARCH_X86
- default 0
- help
- Offset of flash map in firmware image
-
choice
prompt "Bootblock behaviour"
default BOOTBLOCK_SIMPLE
diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c
index f18030c..8d3376c 100644
--- a/src/arch/riscv/rom_media.c
+++ b/src/arch/riscv/rom_media.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2015 Google Inc.
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -17,59 +17,40 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
-#include <console/console.h>
#include <string.h>
-/* This assumes that the CBFS resides at 0x0, which is true for the default
- * configuration. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE);
+#ifdef LIBPAYLOAD
+# define printk(x...)
+# define init_default_cbfs_media libpayload_init_default_cbfs_media
+ extern int libpayload_init_default_cbfs_media(struct cbfs_media *media);
+#else
+# include <console/console.h>
+#endif
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
+// Implementation of memory-mapped ROM media source on X86.
static int rom_media_open(struct cbfs_media *media) {
return 0;
}
static void *rom_media_map(struct cbfs_media *media, size_t offset, size_t count) {
- const struct region_device *boot_dev;
void *ptr;
-
printk(BIOS_INFO, "%s: media %p, offset %lx, size %ld.\n", __func__, media, offset, count);
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
+ ptr = (void*)offset;
return ptr;
}
static void *rom_media_unmap(struct cbfs_media *media, const void *address) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t rom_media_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
+ void *ptr = rom_media_map(media, offset, count);
+ memcpy(dest, ptr, count);
+ rom_media_unmap(media, ptr);
return count;
}
@@ -78,8 +59,25 @@ static int rom_media_close(struct cbfs_media *media) {
}
static int init_rom_media_cbfs(struct cbfs_media *media) {
- boot_device_init();
- media->context = (void *)boot_device_ro();
+ /* this assumes that the CBFS resides at 0x0,
+ * which is true for the default configuration
+ */
+ int32_t *cbfs_header_ptr = (int32_t*)(uintptr_t)(CONFIG_CBFS_SIZE - 4);
+ uint64_t cbfs_header_offset = CONFIG_CBFS_SIZE + *cbfs_header_ptr;
+ struct cbfs_header *header = (struct cbfs_header*) cbfs_header_offset;
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ printk(BIOS_ERR, "Expected %08lx and got %08lx\n", (unsigned long) CBFS_HEADER_MAGIC, (unsigned long) ntohl(header->magic));
+ return -1;
+ } else {
+ uint32_t romsize = ntohl(header->romsize);
+ media->context = (void*)(uintptr_t)romsize;
+#if defined(CONFIG_ROM_SIZE)
+ if (CONFIG_ROM_SIZE != romsize)
+ printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ CONFIG_ROM_SIZE, romsize);
+#endif
+ }
media->open = rom_media_open;
media->close = rom_media_close;
media->map = rom_media_map;
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index e308be9..c7e8b62 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -6,7 +6,6 @@ romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += rom_media.c
-romstage-y += mmap_boot.c
endif # CONFIG_ARCH_ROMSTAGE_X86_32
@@ -23,7 +22,6 @@ ramstage-y += memcpy.c
ramstage-y += memmove.c
ramstage-y += ebda.c
ramstage-y += rom_media.c
-ramstage-y += mmap_boot.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -34,7 +32,6 @@ smm-y += memset.c
smm-y += memcpy.c
smm-y += memmove.c
smm-y += rom_media.c
-smm-y += mmap_boot.c
rmodules_x86_32-y += memset.c
rmodules_x86_32-y += memcpy.c
diff --git a/src/arch/x86/lib/mmap_boot.c b/src/arch/x86/lib/mmap_boot.c
deleted file mode 100644
index eb7b23e..0000000
--- a/src/arch/x86/lib/mmap_boot.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-
-/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
-#define rom_base ((void *)(uintptr_t)(-(int32_t)CONFIG_ROM_SIZE))
-
-static const struct mem_region_device boot_dev =
- MEM_REGION_DEV_INIT(rom_base, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &boot_dev.rdev;
-}
diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c
index d4663c7..659e5e4 100644
--- a/src/arch/x86/lib/rom_media.c
+++ b/src/arch/x86/lib/rom_media.c
@@ -17,8 +17,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
-
-#include <boot_device.h>
#include <cbfs.h>
#include <string.h>
@@ -38,19 +36,14 @@ static int x86_rom_open(struct cbfs_media *media) {
static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) {
void *ptr;
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
+ // Some address (ex, pointer to master header) may be given in memory
+ // mapped location. To workaround that, we handle >0xf0000000 as real
+ // memory pointer.
- /* Extremely large offsets are considered relative to end of region. */
if ((uint32_t)offset > (uint32_t)0xf0000000)
- offset += region_device_sz(boot_dev);
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
+ ptr = (void*)offset;
+ else
+ ptr = (void*)(0 - (uint32_t)media->context + offset);
return ptr;
}
@@ -60,13 +53,7 @@ static void *x86_rom_unmap(struct cbfs_media *media, const void *address) {
static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count) {
- void *ptr;
-
- ptr = x86_rom_map(media, offset, count);
-
- if (ptr == (void *)-1)
- return 0;
-
+ void *ptr = x86_rom_map(media, offset, count);
memcpy(dest, ptr, count);
x86_rom_unmap(media, ptr);
return count;
@@ -76,14 +63,30 @@ static int x86_rom_close(struct cbfs_media *media) {
return 0;
}
-static int init_x86rom_cbfs_media(struct cbfs_media *media) {
- boot_device_init();
-
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
+int init_x86rom_cbfs_media(struct cbfs_media *media);
+int init_x86rom_cbfs_media(struct cbfs_media *media) {
+ // On X86, we always keep a reference of pointer to CBFS header in
+ // 0xfffffffc, and the pointer is still a memory-mapped address.
+ // Since the CBFS core always use ROM offset, we need to figure out
+ // header->romsize even before media is initialized.
+ struct cbfs_header *header = (struct cbfs_header*)
+ *(uint32_t*)(0xfffffffc);
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+#if defined(CONFIG_ROM_SIZE)
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ media->context = (void*)CONFIG_ROM_SIZE;
+#else
return -1;
-
+#endif
+ } else {
+ uint32_t romsize = ntohl(header->romsize);
+ media->context = (void*)romsize;
+#if defined(CONFIG_ROM_SIZE)
+ if (CONFIG_ROM_SIZE != romsize)
+ printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
+ CONFIG_ROM_SIZE, romsize);
+#endif
+ }
media->open = x86_rom_open;
media->close = x86_rom_close;
media->map = x86_rom_map;
diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c
index a585bca..a5863b6 100644
--- a/src/cpu/allwinner/a10/bootblock_media.c
+++ b/src/cpu/allwinner/a10/bootblock_media.c
@@ -4,17 +4,11 @@
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
* Subject to the GNU GPL v2, or (at your option) any later version.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
-const struct region_device *boot_device_ro(void)
-{
- return NULL;
-}
-
int init_default_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet.");
- return -1;
+ return 0;
}
diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c
index 79724ee..9824fc3 100644
--- a/src/cpu/ti/am335x/bootblock_media.c
+++ b/src/cpu/ti/am335x/bootblock_media.c
@@ -17,21 +17,11 @@
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <symbols.h>
-/* FIXME: No idea how big the internal SRAM actually is. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT(_dram, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
-
static int dummy_open(struct cbfs_media *media)
{
return 0;
@@ -45,48 +35,33 @@ static int dummy_close(struct cbfs_media *media)
static void * on_chip_memory_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ return _dram + offset;
}
static void * dummy_unmap(struct cbfs_media *media, const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t on_chip_memory_read(struct cbfs_media *media, void *dest,
size_t offset, size_t count)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
+ void *ptr = media->map(media, offset, count);
+ memcpy(dest, ptr, count);
+ media->unmap(media, ptr);
return count;
}
int init_default_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ struct cbfs_header *header =
+ (struct cbfs_header *)(_dram + CONFIG_CBFS_HEADER_ROM_OFFSET);
+
+ if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
+ printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
+ return -1;
+ }
- media->context = (void *)boot_device_ro();
media->open = dummy_open;
media->close = dummy_close;
media->map = on_chip_memory_map;
diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c
index dd05fb6..a8c945b 100644
--- a/src/cpu/ti/am335x/nand.c
+++ b/src/cpu/ti/am335x/nand.c
@@ -17,16 +17,10 @@
* Foundation, Inc.
*/
-#include <boot_device.h>
#include <cbfs.h>
-const struct region_device *boot_device_ro(void)
-{
- return NULL;
-}
-
int init_default_cbfs_media(struct cbfs_media *media)
{
- /* FIXME: add support for reading coreboot from NAND */
- return -1;
+ /* FIXME: add support for reading coreboot from NAND */
+ return 0;
}
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 8dce86b..da1f6fa 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -26,7 +26,6 @@
#include <pc80/mc146818rtc.h>
#endif
#include <bcd.h>
-#include <fmap.h>
#include <rtc.h>
#include <smbios.h>
#include <spi-generic.h>
@@ -36,6 +35,7 @@
#include <elog.h>
#include "elog_internal.h"
+#include <vendorcode/google/chromeos/fmap.h>
#if !IS_ENABLED(CONFIG_CHROMEOS) && CONFIG_ELOG_FLASH_BASE == 0
#error "CONFIG_ELOG_FLASH_BASE is invalid"
@@ -86,6 +86,26 @@ static inline u32 get_rom_size(void)
}
/*
+ * Convert a memory mapped flash address into a flash offset
+ */
+static inline u32 elog_flash_address_to_offset(u8 *address)
+{
+#if CONFIG_ARCH_X86
+ /* For x86, assume address is memory-mapped near 4GB */
+ u32 rom_size;
+
+ if (!elog_spi)
+ return 0;
+
+ rom_size = get_rom_size();
+
+ return (u32)address - ((u32)~0UL - rom_size + 1);
+#else
+ return (u32)(uintptr_t)address;
+#endif
+}
+
+/*
* Pointer to an event log header in the event data area
*/
static inline struct event_header*
@@ -497,22 +517,21 @@ static void elog_find_flash(void)
{
elog_debug("elog_find_flash()\n");
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- /* Find the ELOG base and size in FMAP */
- struct region r;
-
- if (fmap_locate_area("RW_ELOG", &r) < 0) {
- printk(BIOS_WARNING,
- "ELOG: Unable to find RW_ELOG in FMAP\n");
- flash_base = total_size = 0;
- } else {
- flash_base = region_offset(&r);
- total_size = MIN(region_sz(&r), CONFIG_ELOG_AREA_SIZE);
- }
+#if CONFIG_CHROMEOS
+ /* Find the ELOG base and size in FMAP */
+ u8 *flash_base_ptr;
+ int fmap_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr);
+ if (fmap_size < 0) {
+ printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP\n");
+ flash_base = total_size = 0;
} else {
- flash_base = CONFIG_ELOG_FLASH_BASE;
- total_size = CONFIG_ELOG_AREA_SIZE;
+ flash_base = elog_flash_address_to_offset(flash_base_ptr);
+ total_size = MIN(fmap_size, CONFIG_ELOG_AREA_SIZE);
}
+#else
+ flash_base = CONFIG_ELOG_FLASH_BASE;
+ total_size = CONFIG_ELOG_AREA_SIZE;
+#endif
log_size = total_size - sizeof(struct elog_header);
full_threshold = log_size - ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE;
shrink_size = MIN(total_size * ELOG_SHRINK_PERCENTAGE / 100,
diff --git a/src/include/boot_device.h b/src/include/boot_device.h
deleted file mode 100644
index 0848ea5..0000000
--- a/src/include/boot_device.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _BOOT_DEVICE_H_
-#define _BOOT_DEVICE_H_
-
-#include <region.h>
-
-/* Return the region_device for the read-only boot device. */
-const struct region_device *boot_device_ro(void);
-
-/*
- * Create a sub-region of the read-only boot device.
- * Returns 0 on success, < 0 on error.
- */
-int boot_device_ro_subregion(const struct region *sub,
- struct region_device *subrd);
-
-/*
- * Initialize the boot device. This may be called multiple times within
- * a stage so boot device implementations should account for this behavior.
- **/
-void boot_device_init(void);
-
-#endif /* _BOOT_DEVICE_H_ */
diff --git a/src/include/fmap.h b/src/include/fmap.h
deleted file mode 100644
index e575bbf..0000000
--- a/src/include/fmap.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _FMAP_H_
-#define _FMAP_H_
-
-#include <region.h>
-
-/* Locate the named area in the fmap and fill in a region device representing
- * that area. The region is a sub-region of the readonly boot media. Return
- * 0 on success, < 0 on error. */
-int fmap_locate_area_as_rdev(const char *name, struct region_device *area);
-
-/* Locate the named area in the fmap and fill in a region with the
- * offset and size of that area within the boot media. Return 0 on success,
- * < 0 on error. */
-int fmap_locate_area(const char *name, struct region *r);
-
-#endif
diff --git a/src/include/fmap_serialized.h b/src/include/fmap_serialized.h
deleted file mode 100644
index 3585f0b..0000000
--- a/src/include/fmap_serialized.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Google Inc. nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- */
-
-#ifndef FLASHMAP_SERIALIZED_H__
-#define FLASHMAP_SERIALIZED_H__
-
-#include <stdint.h>
-
-#define FMAP_SIGNATURE "__FMAP__"
-#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
-#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
-#define FMAP_STRLEN 32 /* maximum length for strings, */
- /* including null-terminator */
-
-enum fmap_flags {
- FMAP_AREA_STATIC = 1 << 0,
- FMAP_AREA_COMPRESSED = 1 << 1,
- FMAP_AREA_RO = 1 << 2,
-};
-
-/* Mapping of volatile and static regions in firmware binary */
-struct fmap_area {
- uint32_t offset; /* offset relative to base */
- uint32_t size; /* size in bytes */
- uint8_t name[FMAP_STRLEN]; /* descriptive name */
- uint16_t flags; /* flags for this area */
-} __attribute__((packed));
-
-struct fmap {
- uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
- uint8_t ver_major; /* major version */
- uint8_t ver_minor; /* minor version */
- uint64_t base; /* address of the firmware binary */
- uint32_t size; /* size of firmware binary in bytes */
- uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
- uint16_t nareas; /* number of areas described by
- fmap_areas[] below */
- struct fmap_area areas[];
-} __attribute__((packed));
-
-#endif /* FLASHMAP_SERIALIZED_H__ */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5ec9de7..11562bd 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -31,19 +31,15 @@ bootblock-y += memchr.c
bootblock-y += memcmp.c
bootblock-y += mem_pool.c
bootblock-y += region.c
-bootblock-y += boot_device.c
-bootblock-y += fmap.c
verstage-y += prog_ops.c
verstage-y += delay.c
verstage-y += cbfs.c
verstage-y += cbfs_core.c
verstage-y += halt.c
-verstage-y += fmap.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
verstage-y += region.c
-verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -64,7 +60,6 @@ $(foreach arch,$(ARCH_SUPPORTED),\
$(eval rmodules_$(arch)-y += memcmp.c) \
$(eval rmodules_$(arch)-y += rmodule.ld))
-romstage-y += fmap.c
romstage-$(CONFIG_I2C_TPM) += delay.c
romstage-y += cbfs.c cbfs_core.c
romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
@@ -92,7 +87,6 @@ ramstage-y += hardwaremain.c
ramstage-y += selfboot.c
ramstage-y += coreboot_table.c
ramstage-y += bootmem.c
-ramstage-y += fmap.c
ramstage-y += memchr.c
ramstage-y += memcmp.c
ramstage-y += malloc.c
@@ -147,12 +141,7 @@ ramstage-y += mem_pool.c
romstage-y += region.c
ramstage-y += region.c
-romstage-y += boot_device.c
-ramstage-y += boot_device.c
-smm-y += region.c
-smm-y += boot_device.c
-smm-y += fmap.c
smm-y += cbfs.c cbfs_core.c memcmp.c
smm-$(CONFIG_COMPILER_GCC) += gcc.c
diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c
deleted file mode 100644
index e0353fc..0000000
--- a/src/lib/boot_device.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-
-void __attribute__((weak)) boot_device_init(void)
-{
- /* Provide weak do-nothing init. */
-}
-
-int boot_device_ro_subregion(const struct region *sub,
- struct region_device *subrd)
-{
- const struct region_device *boot_dev;
-
- boot_dev = boot_device_ro();
-
- if (boot_dev == NULL)
- return -1;
-
- return rdev_chain(subrd, boot_dev, region_offset(sub), region_sz(sub));
-}
diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c
index 6758220..6c8d78d 100644
--- a/src/lib/cbfs_spi.c
+++ b/src/lib/cbfs_spi.c
@@ -23,52 +23,17 @@
* SPI.
*/
-#include <boot_device.h>
#include <cbfs.h>
-#include <region.h>
#include <spi_flash.h>
#include <symbols.h>
-static struct spi_flash *spi_flash_info;
-
-static ssize_t spi_readat(const struct region_device *rd, void *b,
- size_t offset, size_t size)
-{
- if (spi_flash_info->read(spi_flash_info, offset, size, b))
- return -1;
- return size;
-}
-
-static const struct region_device_ops spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = spi_readat,
+/* SPI flash as CBFS media. */
+struct cbfs_spi_context {
+ struct spi_flash *spi_flash_info;
+ struct cbfs_simple_buffer buffer;
};
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
-
-void boot_device_init(void)
-{
- int bus = CONFIG_BOOT_MEDIA_SPI_BUS;
- int cs = 0;
-
- if (spi_flash_info != NULL)
- return;
-
- spi_flash_info = spi_flash_probe(bus, cs);
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
-
-/* Return the CBFS boot device. */
-const struct region_device *boot_device_ro(void)
-{
- if (spi_flash_info == NULL)
- return NULL;
-
- return &mdev.rdev;
-}
+static struct cbfs_spi_context spi_context;
static int cbfs_media_open(struct cbfs_media *media)
{
@@ -84,58 +49,52 @@ static size_t cbfs_media_read(struct cbfs_media *media,
void *dest, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct cbfs_spi_context *context = media->context;
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ return context->spi_flash_info->read
+ (context->spi_flash_info, offset, count, dest) ? 0 : count;
}
static void *cbfs_media_map(struct cbfs_media *media,
size_t offset, size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
+ struct cbfs_spi_context *context = media->context;
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ return cbfs_simple_buffer_map(&context->buffer, media, offset, count);
}
static void *cbfs_media_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
+ struct cbfs_spi_context *context = media->context;
- return NULL;
+ return cbfs_simple_buffer_unmap(&context->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int init_cbfs_media_context(void)
{
- boot_device_init();
+ if (!spi_context.spi_flash_info) {
+
+ spi_context.spi_flash_info = spi_flash_probe
+ (CONFIG_BOOT_MEDIA_SPI_BUS, 0);
- media->context = (void *)boot_device_ro();
+ if (!spi_context.spi_flash_info)
+ return -1;
- if (media->context == NULL)
- return -1;
+ spi_context.buffer.buffer = (void *)_cbfs_cache;
+ spi_context.buffer.size = _cbfs_cache_size;
+ }
+ return 0;
+}
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ media->context = &spi_context;
media->open = cbfs_media_open;
media->close = cbfs_media_close;
media->read = cbfs_media_read;
media->map = cbfs_media_map;
media->unmap = cbfs_media_unmap;
- return 0;
+ return init_cbfs_media_context();
}
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
deleted file mode 100644
index 0f48cdc..0000000
--- a/src/lib/fmap.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012-2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot_device.h>
-#include <console/console.h>
-#include <fmap.h>
-#include <fmap_serialized.h>
-#include <stddef.h>
-#include <string.h>
-
-/*
- * See http://code.google.com/p/flashmap/ for more information on FMAP.
- */
-
-static int find_fmap_directory(struct region_device *fmrd)
-{
- const struct region_device *boot;
- struct fmap *fmap;
- size_t fmap_size;
- size_t offset = CONFIG_FLASHMAP_OFFSET;
-
- boot_device_init();
- boot = boot_device_ro();
-
- if (boot == NULL)
- return -1;
-
- fmap_size = sizeof(struct fmap);
-
- fmap = rdev_mmap(boot, offset, fmap_size);
-
- if (fmap == NULL)
- return -1;
-
- if (memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature))) {
- printk(BIOS_DEBUG, "No FMAP found at %zx offset.\n", offset);
- rdev_munmap(boot, fmap);
- return -1;
- }
-
- printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %zx.\n",
- fmap->name, fmap->ver_major, fmap->ver_minor, offset);
- printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
- (long long)fmap->base, fmap->size, fmap->nareas);
-
- fmap_size += fmap->nareas * sizeof(struct fmap_area);
-
- rdev_munmap(boot, fmap);
-
- return rdev_chain(fmrd, boot, offset, fmap_size);
-}
-
-int fmap_locate_area_as_rdev(const char *name, struct region_device *area)
-{
- struct region ar;
-
- if (fmap_locate_area(name, &ar))
- return -1;
-
- return boot_device_ro_subregion(&ar, area);
-}
-
-int fmap_locate_area(const char *name, struct region *ar)
-{
- struct region_device fmrd;
- size_t offset;
-
- if (find_fmap_directory(&fmrd))
- return -1;
-
- /* Start reading the areas just after fmap header. */
- offset = sizeof(struct fmap);
-
- while (1) {
- struct fmap_area *area;
-
- area = rdev_mmap(&fmrd, offset, sizeof(*area));
-
- if (area == NULL)
- return -1;
-
- if (strcmp((const char *)area->name, name)) {
- rdev_munmap(&fmrd, area);
- offset += sizeof(struct fmap_area);
- continue;
- }
-
- printk(BIOS_DEBUG, "FMAP: area %s found\n", name);
- printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset);
- printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size);
-
- ar->offset = area->offset;
- ar->size = area->size;
-
- rdev_munmap(&fmrd, area);
-
- return 0;
- }
-
- printk(BIOS_DEBUG, "FMAP: area %s not found\n", name);
-
- return -1;
-}
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index e0f2251..8c71263 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -12,20 +12,12 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#include <boot_device.h>
#include <cbfs.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
-/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */
-static const struct mem_region_device gboot_dev =
- MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &gboot_dev.rdev;
-}
+/* Simple memory-mapped ROM emulation. */
static int emu_rom_open(struct cbfs_media *media)
{
@@ -34,40 +26,26 @@ static int emu_rom_open(struct cbfs_media *media)
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
{
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+ if (offset + count > CONFIG_ROM_SIZE)
+ return (void *)-1;
+ return (void*)(offset + 0x10000);
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address)
{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
return NULL;
}
static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ void *ptr = emu_rom_map(media, offset, count);
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
+ if (ptr == (void *)-1)
return 0;
+ memcpy(dest, ptr, count);
+ emu_rom_unmap(media, ptr);
return count;
}
@@ -76,11 +54,10 @@ static int emu_rom_close(struct cbfs_media *media)
return 0;
}
-static int init_emu_rom_cbfs_media(struct cbfs_media *media)
-{
- boot_device_init();
+int init_emu_rom_cbfs_media(struct cbfs_media *media);
- media->context = (void *)boot_device_ro();
+int init_emu_rom_cbfs_media(struct cbfs_media *media)
+{
media->open = emu_rom_open;
media->close = emu_rom_close;
media->map = emu_rom_map;
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index e09336d..bd2fbd5 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -20,13 +20,11 @@
#include <types.h>
#include <string.h>
-#include <cbfs.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <fmap.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
@@ -38,6 +36,11 @@
#include <smbios.h>
#include <device/pci.h>
#include <ec/quanta/ene_kb3940q/ec.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#else
+#include <cbfs.h>
+#endif
static unsigned int search(char *p, char *a, unsigned int lengthp,
unsigned int lengtha)
@@ -197,30 +200,20 @@ static void mainboard_init(device_t dev)
size_t search_length = -1;
u16 io_base = 0;
struct device *ethernet_dev = NULL;
- void *vpd_file;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
- vpd_file = rdev_mmap_full(&rdev);
-
- if (vpd_file != NULL) {
- search_length = region_device_sz(&rdev);
- search_address = (uintptr_t)vpd_file;
- }
- }
+#if CONFIG_CHROMEOS
+ char **vpd_region_ptr = NULL;
+ search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
+ search_address = (unsigned long)(*vpd_region_ptr);
+#else
+ void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
+ CBFS_TYPE_RAW, &search_length);
+ if (vpd_file) {
+ search_address = (unsigned long)vpd_file;
} else {
- vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "vpd.bin", CBFS_TYPE_RAW,
- &search_length);
- if (vpd_file) {
- search_address = (unsigned long)vpd_file;
- } else {
- search_length = -1;
- search_address = 0;
- }
+ search_length = -1;
+ search_address = 0;
}
+#endif
/* Initialize the Embedded Controller */
butterfly_ec_init();
diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c
index 8a648cb..9fd325f 100644
--- a/src/mainboard/google/panther/lan.c
+++ b/src/mainboard/google/panther/lan.c
@@ -24,8 +24,8 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fmap.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/fmap.h>
#include "onboard.h"
static unsigned int search(char *p, u8 *a, unsigned int lengthp,
@@ -117,24 +117,15 @@ static void program_mac_address(u16 io_base)
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
- search_address = rdev_mmap_full(&rdev);
-
- if (search_address != NULL)
- search_length = region_device_sz(&rdev);
- }
- } else {
- search_address = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "vpd.bin",
- CBFS_TYPE_RAW,
- &search_length);
- }
+#if CONFIG_CHROMEOS
+ search_length = find_fmap_entry("RO_VPD", &search_address);
+#else
+ search_address = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
+ CBFS_TYPE_RAW, &search_length);
+#endif
if (search_length <= 0)
- printk(BIOS_ERR, "LAN: VPD not found.\n");
+ printk(BIOS_ERR, "LAN: find_fmap_entry returned -1.\n");
else
get_mac_address(&high_dword, &low_dword, search_address,
search_length);
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index d72c2c3..3bb7fa5 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -22,7 +22,6 @@
#include <bootstate.h>
#include <console/console.h>
#include <cbfs.h>
-#include <fmap.h>
#include <ip_checksum.h>
#include <device/device.h>
#include <cbmem.h>
@@ -30,6 +29,9 @@
#include "haswell.h"
#include <spi-generic.h>
#include <spi_flash.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
/* convert a pointer to flash area into the offset inside the flash */
static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
@@ -64,22 +66,16 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
*/
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- size_t region_size = 0;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
- region_size = region_device_sz(&rdev);
- *mrc_region_ptr = rdev_mmap_full(&rdev);
- }
- } else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
- }
+#if CONFIG_CHROMEOS
+ return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
+#else
+ size_t region_size;
+ *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ "mrc.cache",
+ CBFS_TYPE_MRC_CACHE,
+ ®ion_size);
return region_size;
+#endif
}
/*
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e17c54b..e5f74e8 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -22,7 +22,6 @@
#include <bootstate.h>
#include <console/console.h>
#include <cbfs.h>
-#include <fmap.h>
#include <ip_checksum.h>
#include <device/device.h>
#include <cbmem.h>
@@ -30,6 +29,9 @@
#include "sandybridge.h"
#include <spi-generic.h>
#include <spi_flash.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
/* convert a pointer to flash area into the offset inside the flash */
static inline u32 to_flash_offset(struct spi_flash *flash, void *p) {
@@ -64,22 +66,17 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache)
*/
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- size_t region_size = 0;
-
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
- region_size = region_device_sz(&rdev);
- *mrc_region_ptr = rdev_mmap_full(&rdev);
- }
- } else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
- }
+#if CONFIG_CHROMEOS
+ return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
+#else
+ size_t region_size;
+ *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ "mrc.cache",
+ CBFS_TYPE_MRC_CACHE,
+ ®ion_size);
return region_size;
+#endif
+
}
/*
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 6783f18..9366aa5 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -20,8 +20,10 @@
#include <string.h>
#include <console/console.h>
#include <cbmem.h>
-#include <fmap.h>
#include <ip_checksum.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#endif
#include "mrc_cache.h"
#define MRC_DATA_ALIGN 0x1000
@@ -37,23 +39,16 @@ struct mrc_data_region {
/* common code */
static int mrc_cache_get_region(struct mrc_data_region *region)
{
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
- struct region_device rdev;
-
- if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev))
- return -1;
-
- region->size = region_device_sz(&rdev);
- region->base = rdev_mmap_full(&rdev);
-
- if (region->base == NULL)
- return -1;
-
+#if CONFIG_CHROMEOS
+ int ret;
+ ret = find_fmap_entry("RW_MRC_CACHE", ®ion->base);
+ if (ret >= 0) {
+ region->size = ret;
return 0;
- } else {
- region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE;
- region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE;
}
+#endif
+ region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE;
+ region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE;
return 0;
}
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 46ce59d..78054f4 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_NVIDIA_TEGRA124),y)
bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
+bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += dma.c
bootblock-y += i2c.c
@@ -21,6 +22,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
verstage-y += verstage.c
+verstage-y += cbfs.c
verstage-y += dma.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
@@ -32,6 +34,7 @@ verstage-y += clock.c
verstage-y += i2c.c
verstage-y += cache.c
+romstage-y += cbfs.c
romstage-y += cbmem.c
romstage-y += clock.c
romstage-y += dma.c
@@ -48,6 +51,7 @@ romstage-y += ../tegra/pinmux.c
romstage-y += cache.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += cbfs.c
ramstage-y += cbmem.c
ramstage-y += clock.c
ramstage-y += display.c
diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c
new file mode 100644
index 0000000..d82ca9a
--- /dev/null
+++ b/src/soc/nvidia/tegra124/cbfs.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <soc/spi.h>
+#include <symbols.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return initialize_tegra_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/soc/nvidia/tegra124/include/soc/spi.h b/src/soc/nvidia/tegra124/include/soc/spi.h
index cfa3cd2..ab04632 100644
--- a/src/soc/nvidia/tegra124/include/soc/spi.h
+++ b/src/soc/nvidia/tegra124/include/soc/spi.h
@@ -61,6 +61,11 @@ struct tegra_spi_channel {
enum spi_xfer_mode xfer_mode;
};
+struct cbfs_media;
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+
struct tegra_spi_channel *tegra_spi_init(unsigned int bus);
#endif /* __NVIDIA_TEGRA124_SPI_H__ */
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 0cf5495..683edd1 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -21,7 +21,6 @@
#include <arch/cache.h>
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <console/console.h>
#include <cbfs.h>
#include <delay.h>
@@ -34,7 +33,6 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#include <timer.h>
@@ -802,6 +800,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
+/* SPI as CBFS media. */
+struct tegra_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
static int tegra_spi_cbfs_open(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_open\n");
@@ -819,17 +823,16 @@ static int tegra_spi_cbfs_close(struct cbfs_media *media)
#define JEDEC_FAST_READ_DUAL 0x3b
#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context;
u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
unsigned int read_cmd_bytes;
int ret = count;
struct tegra_spi_channel *channel;
- channel = to_tegra_spi(boot_slave->bus);
+ channel = to_tegra_spi(spi->slave->bus);
if (channel->dual_mode) {
/*
@@ -850,9 +853,9 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
- spi_claim_bus(boot_slave);
+ spi_claim_bus(spi->slave);
- if (spi_xfer(boot_slave, spi_read_cmd,
+ if (spi_xfer(spi->slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
@@ -863,7 +866,7 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
if (channel->dual_mode) {
setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
}
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
+ if (spi_xfer(spi->slave, NULL, 0, dest, count)) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
__func__, count);
@@ -873,70 +876,56 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
-static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count)
-{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- printk(BIOS_ERR, "%s: reading %zx bytes from %zx\n",
- __func__, count, offset);
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ spi_release_bus(spi->slave);
+ return (ret < 0) ? 0 : ret;
}
static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
void *map;
-
DEBUG_SPI("tegra_spi_cbfs_map\n");
-
- boot_dev = media->context;
-
- map = rdev_mmap(boot_dev, offset, count);
-
- if (map == NULL)
- map = (void *)-1;
-
+ map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
return map;
}
static void *tegra_spi_cbfs_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
DEBUG_SPI("tegra_spi_cbfs_unmap\n");
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
- return NULL;
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- DEBUG_SPI("Initializing CBFS media on SPI\n");
+ // TODO Replace static variable to support multiple streams.
+ static struct tegra_spi_media context;
+ static struct tegra_spi_channel *channel;
+
+ channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
+ channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
- boot_device_init();
+ DEBUG_SPI("Initializing CBFS media on SPI\n");
- media->context = (void *)boot_device_ro();
+ context.slave = &channel->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
media->open = tegra_spi_cbfs_open;
media->close = tegra_spi_cbfs_close;
media->read = tegra_spi_cbfs_read;
media->map = tegra_spi_cbfs_map;
media->unmap = tegra_spi_cbfs_unmap;
+#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
+ channel->dual_mode = 1;
+#endif
+
return 0;
}
@@ -948,32 +937,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index c192055..365dab3 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y)
bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
+bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += spi.c
bootblock-y += i2c.c
@@ -22,6 +23,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
verstage-y += verstage.c
+verstage-y += cbfs.c
verstage-y += dma.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
@@ -37,6 +39,7 @@ verstage-y += i2c.c
romstage-y += 32bit_reset.S
romstage-y += romstage_asm.S
romstage-y += addressmap.c
+romstage-y += cbfs.c
romstage-y += cbmem.c
romstage-y += ccplex.c
romstage-y += clock.c
@@ -60,6 +63,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += 32bit_reset.S
ramstage-y += addressmap.c
+ramstage-y += cbfs.c
ramstage-y += cbmem.c
ramstage-y += cpu.c
ramstage-y += cpu_lib.S
diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c
new file mode 100644
index 0000000..7aeb59b
--- /dev/null
+++ b/src/soc/nvidia/tegra132/cbfs.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <soc/spi.h>
+#include <symbols.h>
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ return initialize_tegra_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/spi.h b/src/soc/nvidia/tegra132/include/soc/spi.h
index 4c91c27..2fd9562 100644
--- a/src/soc/nvidia/tegra132/include/soc/spi.h
+++ b/src/soc/nvidia/tegra132/include/soc/spi.h
@@ -62,6 +62,11 @@ struct tegra_spi_channel {
enum spi_xfer_mode xfer_mode;
};
+struct cbfs_media;
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+
struct tegra_spi_channel *tegra_spi_init(unsigned int bus);
#endif /* __NVIDIA_TEGRA132_SPI_H__ */
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index 1650057..7ca66e1 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -21,7 +21,6 @@
#include <arch/cache.h>
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
#include <delay.h>
@@ -34,7 +33,6 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#include <timer.h>
@@ -817,6 +815,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret;
}
+/* SPI as CBFS media. */
+struct tegra_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
static int tegra_spi_cbfs_open(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_open\n");
@@ -834,17 +838,16 @@ static int tegra_spi_cbfs_close(struct cbfs_media *media)
#define JEDEC_FAST_READ_DUAL 0x3b
#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
-static struct spi_slave *boot_slave;
-
-static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context;
u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
unsigned int read_cmd_bytes;
int ret = count;
struct tegra_spi_channel *channel;
- channel = to_tegra_spi(boot_slave->bus);
+ channel = to_tegra_spi(spi->slave->bus);
if (channel->dual_mode) {
/*
@@ -865,9 +868,9 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
- spi_claim_bus(boot_slave);
+ spi_claim_bus(spi->slave);
- if (spi_xfer(boot_slave, spi_read_cmd,
+ if (spi_xfer(spi->slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n",
@@ -878,7 +881,7 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
if (channel->dual_mode) {
setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
}
- if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
+ if (spi_xfer(spi->slave, NULL, 0, dest, count)) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n",
__func__, count);
@@ -888,70 +891,56 @@ static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
- spi_release_bus(boot_slave);
- return ret;
-}
-
-static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count)
-{
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- DEBUG_SPI("%s: reading %zx bytes from %zx\n", __func__, count, offset);
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
-
- return count;
+ spi_release_bus(spi->slave);
+ return (ret < 0) ? 0 : ret;
}
static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
size_t count)
{
- const struct region_device *boot_dev;
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
void *map;
-
DEBUG_SPI("tegra_spi_cbfs_map\n");
-
- boot_dev = media->context;
-
- map = rdev_mmap(boot_dev, offset, count);
-
- if (map == NULL)
- map = (void *)-1;
-
+ map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
return map;
}
static void *tegra_spi_cbfs_unmap(struct cbfs_media *media,
const void *address)
{
- const struct region_device *boot_dev;
-
+ struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
DEBUG_SPI("tegra_spi_cbfs_unmap\n");
-
- boot_dev = media->context;
-
- rdev_munmap(boot_dev, (void *)address);
-
- return NULL;
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-int init_default_cbfs_media(struct cbfs_media *media)
+int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- DEBUG_SPI("Initializing CBFS media on SPI\n");
+ // TODO Replace static variable to support multiple streams.
+ static struct tegra_spi_media context;
+ static struct tegra_spi_channel *channel;
+
+ channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
+ channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
- boot_device_init();
+ DEBUG_SPI("Initializing CBFS media on SPI\n");
- media->context = (void *)boot_device_ro();
+ context.slave = &channel->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
media->open = tegra_spi_cbfs_open;
media->close = tegra_spi_cbfs_close;
media->read = tegra_spi_cbfs_read;
media->map = tegra_spi_cbfs_map;
media->unmap = tegra_spi_cbfs_unmap;
+#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
+ channel->dual_mode = 1;
+#endif
+
return 0;
}
@@ -963,32 +952,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave;
}
-
-static const struct region_device_ops tegra_spi_ops = {
- .mmap = mmap_helper_rdev_mmap,
- .munmap = mmap_helper_rdev_munmap,
- .readat = tegra_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
- return &mdev.rdev;
-}
-
-void boot_device_init(void)
-{
- struct tegra_spi_channel *boot_chan;
-
- boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
- boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
-
-#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
- boot_chan->dual_mode = 1;
-#endif
- boot_slave = &boot_chan->slave;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
-}
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c
index 546018a..2e2aeec 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.c
@@ -19,7 +19,6 @@
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <console/console.h>
#include <soc/alternate_cbfs.h>
@@ -46,7 +45,7 @@
* rest of the firmware's lifetime and all subsequent stages (which will not
* have __PRE_RAM__ defined) can just directly reference it there.
*/
-static int usb_cbfs_open(void)
+static int usb_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
static int first_run = 1;
@@ -81,7 +80,7 @@ static int usb_cbfs_open(void)
* this seems like a safer approach. It also makes it easy to pass our image
* down to payloads.
*/
-static int sdmmc_cbfs_open(void)
+static int sdmmc_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
/*
@@ -112,109 +111,66 @@ static int sdmmc_cbfs_open(void)
return 0;
}
-static int exynos_cbfs_open(struct cbfs_media *media) {
- return 0;
-}
-
-static int exynos_cbfs_close(struct cbfs_media *media) {
- return 0;
-}
-
-static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ memcpy(dest, _cbfs_cache + offset, count);
return count;
}
-static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset,
- size_t count) {
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ return _cbfs_cache + offset;
}
-static void *exynos_cbfs_unmap(struct cbfs_media *media,
- const void *address) {
- const struct region_device *boot_dev;
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
- boot_dev = media->context;
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- rdev_munmap(boot_dev, (void *)address);
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
- return NULL;
+ return 0;
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
- return -1;
-
- media->open = exynos_cbfs_open;
- media->close = exynos_cbfs_close;
- media->read = exynos_cbfs_read;
- media->map = exynos_cbfs_map;
- media->unmap = exynos_cbfs_unmap;
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
return 0;
}
-static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0);
-
-const struct region_device *boot_device_ro(void)
+int init_default_cbfs_media(struct cbfs_media *media)
{
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
- return &alternate_rdev.rdev;
-
- switch (exynos_power->om_stat & OM_STAT_MASK) {
- case OM_STAT_SDMMC:
- return &alternate_rdev.rdev;
- case OM_STAT_SPI:
- return exynos_spi_boot_device();
- default:
- printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
- exynos_power->om_stat);
- return NULL;
- }
-}
-
-void boot_device_init(void)
-{
- mem_region_device_init(&alternate_rdev, _cbfs_cache, _cbfs_cache_size);
-
- if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- usb_cbfs_open();
- return;
- }
+ return initialize_exynos_usb_cbfs_media(media);
switch (exynos_power->om_stat & OM_STAT_MASK) {
case OM_STAT_SDMMC:
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- sdmmc_cbfs_open();
- break;
+ return initialize_exynos_sdmmc_cbfs_media(media);
case OM_STAT_SPI:
- exynos_init_spi_boot_device();
- break;
+ return initialize_exynos_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
default:
printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
exynos_power->om_stat);
+ return 1;
}
}
diff --git a/src/soc/samsung/exynos5250/include/soc/spi.h b/src/soc/samsung/exynos5250/include/soc/spi.h
index 298db1a..92236ae 100644
--- a/src/soc/samsung/exynos5250/include/soc/spi.h
+++ b/src/soc/samsung/exynos5250/include/soc/spi.h
@@ -20,7 +20,8 @@
#ifndef CPU_SAMSUNG_EXYNOS5250_SPI_H
#define CPU_SAMSUNG_EXYNOS5250_SPI_H
-#include <boot_device.h>
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
@@ -91,6 +92,8 @@ int exynos_spi_open(struct exynos_spi *regs);
int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off);
int exynos_spi_close(struct exynos_spi *regs);
-void exynos_init_spi_boot_device(void);
-const struct region_device *exynos_spi_boot_device(void);
+/* Serve as CBFS media source */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
#endif
diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c
index adf31e4..4f32487 100644
--- a/src/soc/samsung/exynos5250/spi.c
+++ b/src/soc/samsung/exynos5250/spi.c
@@ -20,13 +20,11 @@
#include <arch/io.h>
#include <assert.h>
-#include <boot_device.h>
#include <console/console.h>
#include <soc/clk.h>
#include <soc/gpio.h>
#include <soc/spi.h>
#include <stdlib.h>
-#include <symbols.h>
#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "EXYNOS_SPI: " x)
@@ -146,47 +144,70 @@ int exynos_spi_close(struct exynos_spi *regs)
return 0;
}
-static struct exynos_spi *boot_slave_regs;
+// SPI as CBFS media.
+struct exynos_spi_media {
+ struct exynos_spi *regs;
+ struct cbfs_simple_buffer buffer;
+};
-static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
-{
+static int exynos_spi_cbfs_open(struct cbfs_media *media) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_open\n");
+ return exynos_spi_open(spi->regs);
+}
+
+static int exynos_spi_cbfs_close(struct cbfs_media *media) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_close\n");
+ return exynos_spi_close(spi->regs);
+}
+
+static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
int bytes;
DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
- exynos_spi_open(boot_slave_regs);
- bytes = exynos_spi_read(boot_slave_regs, dest, count, offset);
- exynos_spi_close(boot_slave_regs);
+ bytes = exynos_spi_read(spi->regs, dest, count, offset);
+ // Flush and re-open the device.
+ exynos_spi_close(spi->regs);
+ exynos_spi_open(spi->regs);
return bytes;
}
-static void *exynos_spi_map(const struct region_device *rdev,
- size_t offset, size_t count)
-{
+static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
DEBUG_SPI("exynos_spi_cbfs_map\n");
- // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
- // requires buffer memory address to be aligned.
+ // See exynos_spi_rx_tx for I/O alignment limitation.
if (count % 4)
count += 4 - (count % 4);
- return mmap_helper_rdev_mmap(rdev, offset, count);
+ return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
}
-static const struct region_device_ops exynos_spi_ops = {
- .mmap = exynos_spi_map,
- .munmap = mmap_helper_rdev_munmap,
- .readat = exynos_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE);
-
-void exynos_init_spi_boot_device(void)
-{
- boot_slave_regs = (void *)EXYNOS5_SPI1_BASE;
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+static void *exynos_spi_cbfs_unmap(struct cbfs_media *media,
+ const void *address) {
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_unmap\n");
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-const struct region_device *exynos_spi_boot_device(void)
-{
- return &mdev.rdev;
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size) {
+ // TODO Replace static variable to support multiple streams.
+ static struct exynos_spi_media context;
+ DEBUG_SPI("initialize_exynos_spi_cbfs_media\n");
+
+ context.regs = (void*)EXYNOS5_SPI1_BASE;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
+ media->open = exynos_spi_cbfs_open;
+ media->close = exynos_spi_cbfs_close;
+ media->read = exynos_spi_cbfs_read;
+ media->map = exynos_spi_cbfs_map;
+ media->unmap = exynos_spi_cbfs_unmap;
+
+ return 0;
}
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c
index 9bba748..b30ed6b 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.c
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.c
@@ -20,7 +20,6 @@
#include <arch/cache.h>
#include <assert.h>
-#include <boot_device.h>
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <console/console.h>
#include <soc/alternate_cbfs.h>
@@ -47,7 +46,7 @@
* rest of the firmware's lifetime and all subsequent stages (which will not
* have __PRE_RAM__ defined) can just directly reference it there.
*/
-static int usb_cbfs_open(void)
+static int usb_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
static int first_run = 1;
@@ -85,7 +84,7 @@ static int usb_cbfs_open(void)
* this seems like a safer approach. It also makes it easy to pass our image
* down to payloads.
*/
-static int sdmmc_cbfs_open(void)
+static int sdmmc_cbfs_open(struct cbfs_media *media)
{
#ifdef __PRE_RAM__
/*
@@ -119,109 +118,66 @@ static int sdmmc_cbfs_open(void)
return 0;
}
-static int exynos_cbfs_open(struct cbfs_media *media) {
- return 0;
-}
-
-static int exynos_cbfs_close(struct cbfs_media *media) {
- return 0;
-}
-
-static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest,
- size_t offset, size_t count) {
- const struct region_device *boot_dev;
-
- boot_dev = media->context;
-
- if (rdev_readat(boot_dev, dest, offset, count) < 0)
- return 0;
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ memcpy(dest, _cbfs_cache + offset, count);
return count;
}
-static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset,
- size_t count) {
- const struct region_device *boot_dev;
- void *ptr;
-
- boot_dev = media->context;
-
- ptr = rdev_mmap(boot_dev, offset, count);
-
- if (ptr == NULL)
- return (void *)-1;
-
- return ptr;
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < _cbfs_cache_size);
+ return _cbfs_cache + offset;
}
-static void *exynos_cbfs_unmap(struct cbfs_media *media,
- const void *address) {
- const struct region_device *boot_dev;
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
- boot_dev = media->context;
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- rdev_munmap(boot_dev, (void *)address);
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
- return NULL;
+ return 0;
}
-int init_default_cbfs_media(struct cbfs_media *media)
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
- boot_device_init();
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- media->context = (void *)boot_device_ro();
-
- if (media->context == NULL)
- return -1;
-
- media->open = exynos_cbfs_open;
- media->close = exynos_cbfs_close;
- media->read = exynos_cbfs_read;
- media->map = exynos_cbfs_map;
- media->unmap = exynos_cbfs_unmap;
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
return 0;
}
-static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0);
-
-const struct region_device *boot_device_ro(void)
+int init_default_cbfs_media(struct cbfs_media *media)
{
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
- return &alternate_rdev.rdev;
-
- switch (exynos_power->om_stat & OM_STAT_MASK) {
- case OM_STAT_SDMMC:
- return &alternate_rdev.rdev;
- case OM_STAT_SPI:
- return exynos_spi_boot_device();
- default:
- printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
- exynos_power->om_stat);
- return NULL;
- }
-}
-
-void boot_device_init(void)
-{
- mem_region_device_init(&alternate_rdev, _cbfs_cache, _cbfs_cache_size);
-
- if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) {
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
- usb_cbfs_open();
- return;
- }
+ return initialize_exynos_usb_cbfs_media(media);
switch (exynos_power->om_stat & OM_STAT_MASK) {
case OM_STAT_SDMMC:
- printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
- sdmmc_cbfs_open();
- break;
+ return initialize_exynos_sdmmc_cbfs_media(media);
case OM_STAT_SPI:
- exynos_init_spi_boot_device();
- break;
+ return initialize_exynos_spi_cbfs_media(media,
+ _cbfs_cache, _cbfs_cache_size);
default:
printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
exynos_power->om_stat);
+ return 1;
}
}
diff --git a/src/soc/samsung/exynos5420/include/soc/spi.h b/src/soc/samsung/exynos5420/include/soc/spi.h
index 77d5ffc..cf77800 100644
--- a/src/soc/samsung/exynos5420/include/soc/spi.h
+++ b/src/soc/samsung/exynos5420/include/soc/spi.h
@@ -20,7 +20,8 @@
#ifndef CPU_SAMSUNG_EXYNOS5420_SPI_H
#define CPU_SAMSUNG_EXYNOS5420_SPI_H
-#include <boot_device.h>
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
@@ -90,6 +91,8 @@ check_member(exynos_spi, fb_clk, 0x2c);
#define SPI_RX_BYTE_SWAP (1 << 6)
#define SPI_RX_HWORD_SWAP (1 << 7)
-void exynos_init_spi_boot_device(void);
-const struct region_device *exynos_spi_boot_device(void);
+/* Serve as CBFS media source */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
#endif
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 2edc337..5f29803 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -26,7 +26,6 @@
#include <spi_flash.h>
#include <stdlib.h>
#include <string.h>
-#include <symbols.h>
#define EXYNOS_SPI_MAX_TRANSFER_BYTES (65535)
@@ -243,43 +242,76 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
return len;
}
-static struct exynos_spi_slave *boot_slave;
+// SPI as CBFS media.
+struct exynos_spi_media {
+ struct spi_slave *slave;
+ struct cbfs_simple_buffer buffer;
+};
+
+static int exynos_spi_cbfs_open(struct cbfs_media *media)
+{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_open\n");
+ return spi_claim_bus(spi->slave);
+}
+
+static int exynos_spi_cbfs_close(struct cbfs_media *media)
+{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_close\n");
+ spi_release_bus(spi->slave);
+ return 0;
+}
-static ssize_t exynos_spi_readat(const struct region_device *rdev, void *dest,
- size_t offset, size_t count)
+static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ int bytes;
DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
- return exynos_spi_read(&boot_slave->slave, dest, count, offset);
+ bytes = exynos_spi_read(spi->slave, dest, count, offset);
+ return bytes;
}
-static void *exynos_spi_map(const struct region_device *rdev,
- size_t offset, size_t count)
+static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
{
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
DEBUG_SPI("exynos_spi_cbfs_map\n");
// exynos: spi_rx_tx may work in 4 byte-width-transmission mode and
// requires buffer memory address to be aligned.
if (count % 4)
count += 4 - (count % 4);
- return mmap_helper_rdev_mmap(rdev, offset, count);
+ return cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
}
-static const struct region_device_ops exynos_spi_ops = {
- .mmap = exynos_spi_map,
- .munmap = mmap_helper_rdev_munmap,
- .readat = exynos_spi_readat,
-};
-
-static struct mmap_helper_region_device mdev =
- MMAP_HELPER_REGION_INIT(&exynos_spi_ops, 0, CONFIG_ROM_SIZE);
-
-void exynos_init_spi_boot_device(void)
+static void *exynos_spi_cbfs_unmap(struct cbfs_media *media,
+ const void *address)
{
- boot_slave = &exynos_spi_slaves[1];
-
- mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
+ struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context;
+ DEBUG_SPI("exynos_spi_cbfs_unmap\n");
+ return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
-const struct region_device *exynos_spi_boot_device(void)
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size)
{
- return &mdev.rdev;
+ // TODO Replace static variable to support multiple streams.
+ static struct exynos_spi_media context;
+ static struct exynos_spi_slave *eslave = &exynos_spi_slaves[1];
+ DEBUG_SPI("initialize_exynos_spi_cbfs_media\n");
+
+ context.slave = &eslave->slave;
+ context.buffer.allocated = context.buffer.last_allocate = 0;
+ context.buffer.buffer = buffer_address;
+ context.buffer.size = buffer_size;
+ media->context = (void*)&context;
+ media->open = exynos_spi_cbfs_open;
+ media->close = exynos_spi_cbfs_close;
+ media->read = exynos_spi_cbfs_read;
+ media->map = exynos_spi_cbfs_map;
+ media->unmap = exynos_spi_cbfs_unmap;
+
+ return 0;
}
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 0b0b862..0fc0d54 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -94,6 +94,15 @@ config CHROMEOS_RAMOOPS_RAM_SIZE
default 0x00100000
depends on CHROMEOS_RAMOOPS
+config FLASHMAP_OFFSET
+ hex "Flash Map Offset"
+ default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default CBFS_SIZE if !ARCH_X86
+ default 0
+ help
+ Offset of flash map in firmware image
+
config EC_SOFTWARE_SYNC
bool "Enable EC software sync"
default n
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index df24435..6e416ee 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -34,7 +34,11 @@ ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
+verstage-y += fmap.c
+romstage-y += fmap.c
+ramstage-y += fmap.c
ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
+smm-y += fmap.c
romstage-y += vpd_decode.c cros_vpd.c
ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c
ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),)
diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c
index fed1d82..c0e4830 100644
--- a/src/vendorcode/google/chromeos/cros_vpd.c
+++ b/src/vendorcode/google/chromeos/cros_vpd.c
@@ -6,11 +6,12 @@
#include <console/console.h>
-#include <fmap.h>
+#include <cbfs.h>
#include <stdlib.h>
#include <string.h>
#include "cros_vpd.h"
+#include "fmap.h"
#include "lib_vpd.h"
#include "vpd_tables.h"
@@ -34,7 +35,9 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size)
MAYBE_STATIC int result = -1;
struct google_vpd_info info;
int32_t base;
- struct region_device vpd;
+
+ const struct fmap_area *area;
+ struct cbfs_media media;
if (cached) {
*vpd_address = cached_address;
@@ -43,31 +46,32 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size)
}
cached = 1;
- if (fmap_locate_area_as_rdev("RO_VPD", &vpd)) {
+ area = find_fmap_area(fmap_find(), "RO_VPD");
+ if (!area) {
printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__);
return result;
}
-
- base = 0;
- cached_size = region_device_sz(&vpd);
-
- if ((cached_size < GOOGLE_VPD_2_0_OFFSET + sizeof(info)) ||
- rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
- cached_size - GOOGLE_VPD_2_0_OFFSET)) {
+ if (area->size <= GOOGLE_VPD_2_0_OFFSET + sizeof(info)) {
printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n",
- __func__, cached_size);
+ __func__, area->size);
return result;
}
+ base = area->offset + GOOGLE_VPD_2_0_OFFSET;
+ cached_size = area->size - GOOGLE_VPD_2_0_OFFSET;
+ init_default_cbfs_media(&media);
+ media.open(&media);
+
/* Try if we can find a google_vpd_info, otherwise read whole VPD. */
- if (rdev_readat(&vpd, &info, base, sizeof(info)) == sizeof(info) &&
+ if (media.read(&media, &info, base, sizeof(info)) == sizeof(info) &&
memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic))
== 0 && cached_size >= info.size + sizeof(info)) {
base += sizeof(info);
cached_size = info.size;
}
- cached_address = rdev_mmap(&vpd, base, cached_size);
+ cached_address = media.map(&media, base, cached_size);
+ media.close(&media);
if (cached_address) {
*vpd_address = cached_address;
*vpd_size = cached_size;
diff --git a/src/vendorcode/google/chromeos/fmap.h b/src/vendorcode/google/chromeos/fmap.h
new file mode 100644
index 0000000..05d3fb6
--- /dev/null
+++ b/src/vendorcode/google/chromeos/fmap.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_LIB_FMAP_H__
+#define FLASHMAP_LIB_FMAP_H__
+
+#include <stdint.h>
+
+#define FMAP_REVERSED_SIGNATURE "__PAMF__" /* avoid magic number in .rodata */
+#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
+#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
+#define FMAP_STRLEN 32 /* maximum length for strings, */
+ /* including null-terminator */
+
+enum fmap_flags {
+ FMAP_AREA_STATIC = 1 << 0,
+ FMAP_AREA_COMPRESSED = 1 << 1,
+ FMAP_AREA_RO = 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+ uint32_t offset; /* offset relative to base */
+ uint32_t size; /* size in bytes */
+ uint8_t name[FMAP_STRLEN]; /* descriptive name */
+ uint16_t flags; /* flags for this area */
+} __attribute__((packed));
+
+struct fmap {
+ uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
+ uint8_t ver_major; /* major version */
+ uint8_t ver_minor; /* minor version */
+ uint64_t base; /* address of the firmware binary */
+ uint32_t size; /* size of firmware binary in bytes */
+ uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
+ uint16_t nareas; /* number of areas described by
+ fmap_areas[] below */
+ struct fmap_area areas[];
+} __attribute__((packed));
+
+
+/* coreboot specific function prototypes */
+const struct fmap *fmap_find(void);
+const struct fmap_area *find_fmap_area(const struct fmap *fmap,
+ const char name[]);
+int find_fmap_entry(const char name[], void **pointer);
+#endif /* FLASHMAP_LIB_FMAP_H__*/
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index 955d72f..6b3d7dc 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -26,13 +26,13 @@
#include <cbmem.h>
#include <console/console.h>
#include <console/vtxprintf.h>
-#include <fmap.h>
#include <stdlib.h>
#include <timestamp.h>
#define NEED_VB20_INTERNALS /* TODO: remove me! */
#include <vb2_api.h>
#include <vboot_struct.h>
#include "../chromeos.h"
+#include "../fmap.h"
#include "../vboot_handoff.h"
#include "misc.h"
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