coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 849fac6 autoport: Update documentation to mention runtime prerequisites
by Vladimir Serbinenko 29 May '15

29 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10369 -gerrit commit 849fac6d4ccb635c86a48e0cf74da6e93a2c0db7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 29 20:40:55 2015 +0200 autoport: Update documentation to mention runtime prerequisites Change-Id: I3b5fe953fa0e00fb827b66963d69f32d63a07b16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/readme.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index e5ea77d..2f525a9 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -15,7 +15,12 @@ likely to miss EC support * Go into BIOS setup on target machine and enable all the devices. This will allow autoport to detect as much as possible * Boot into target machine under GNU/Linux -* Make sure you have GCC and golang installed +* Make sure that following components are installed: + * GCC + * golang + * lspci + * dmidecode + * acpidump * Grab coreboot tree * Execute following commands starting from coreboot tree

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Patch merged into coreboot/master: 2befcbb UEFI: Conditionally define the ASSERT macro
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 2befcbb85dc63da2c972c656656f390d976802e6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed May 27 16:16:19 2015 -0700 UEFI: Conditionally define the ASSERT macro Only define the ASSERT macro when it is not already defined. This change allows the UEFI/FSP definitions to be included with most other coreboot includes. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: Iccfeb83eb1e52623ae0a0fe2a96b587ce61f82d7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10334 for details. -gerrit

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Patch merged into coreboot/master: f4d6587 tpm: Add Infineon TPM 1.2 support
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit f4d65872d789307a25a80479fcfc1a66c53d42ae Author: Subrata <subrata.banik(a)intel.com> Date: Thu May 14 14:38:07 2015 +0530 tpm: Add Infineon TPM 1.2 support This patch provides support for TPM Infineon TT1.2 devices by enumerating the TT1.2 ID in the Infineon device list. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271256 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/10302 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> See http://review.coreboot.org/10302 for details. -gerrit

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Patch merged into coreboot/master: 41b08d9 tpm: Fix multiple device support
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 41b08d99441fb8cf9e5f69eec0209c3495a40ec9 Author: Subrata <subrata.banik(a)intel.com> Date: Thu May 14 14:38:07 2015 +0530 tpm: Fix multiple device support Current TPM driver does not support multiple devices for a given vendor. As the device object never takes the 2nd ID in the list. This patch fixes the same. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271727 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar(a)intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar(a)intel.com> Reviewed-on: http://review.coreboot.org/10303 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> See http://review.coreboot.org/10303 for details. -gerrit

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Patch merged into coreboot/master: 1ec23c9 intel/broadwell: Hide use of acpi_slp_type
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 1ec23c9b52ed95bfcc71ed0637cca1c302e7a815 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:18:18 2015 +0300 intel/broadwell: Hide use of acpi_slp_type Change-Id: I106779571df5168ec358ad1cc4dc4195639a7a7d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10359 for details. -gerrit

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Patch merged into coreboot/master: 315a7b8 binaryPI: Hide use of acpi_slp_type
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 315a7b83836954917e993f5ce59b29cfe7c99470 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:18:08 2015 +0300 binaryPI: Hide use of acpi_slp_type Change-Id: I867932db4388eb078b69b6f42c82967777d45d79 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10358 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10358 for details. -gerrit

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Patch merged into coreboot/master: 59d262c x86 SMM: Merge recipes
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 59d262ce6f76b7ea23cb2890ab9777aba5b25d06 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 10:55:59 2015 +0300 x86 SMM: Merge recipes Change-Id: I35244ebd56e1653109f7cf68ed26a42035c17cc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10367 for details. -gerrit

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Patch merged into coreboot/master: e4e0f94 x86 SMM: We have single SMM linker script now
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit e4e0f9477f97e88e8ecaa7c4ffd31083ed1d327d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 10:55:02 2015 +0300 x86 SMM: We have single SMM linker script now Change-Id: I0c20b674b536a2964962f84228f681b53dc114dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10366 Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10366 for details. -gerrit

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Patch set updated for coreboot: 7ccf6e7 HyperTransport: Use subordinate property to track chain enumeration
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8688 -gerrit commit 7ccf6e750761ab65febf21f23102f73808f659bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 05:56:22 2015 +0200 HyperTransport: Use subordinate property to track chain enumeration For amdfam10, (ht_c_index > 3) never evaluates true as the code already has a return for this case above. Change-Id: Ie90941671e1b2b4f42e2b1b0641ca59334fcf0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 4 +-- src/northbridge/amd/agesa/family10/northbridge.c | 11 ++++++-- src/northbridge/amd/agesa/family15/northbridge.c | 14 +++++++--- src/northbridge/amd/amdfam10/northbridge.c | 35 ++++++++++++------------ src/northbridge/amd/amdk8/northbridge.c | 26 ++++++++++++------ 5 files changed, 55 insertions(+), 35 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 1a2e7ff..84b1aa7 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -501,8 +501,8 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, ht_unitid_base, offset_unitid); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max); - return max; + bus->subordinate = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, bus->secondary); + return bus->subordinate; } unsigned int ht_scan_bridge(struct device *dev, unsigned int max) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6d0b1b7..9f2555f 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -554,13 +554,14 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; device_t io_hub = NULL; u32 next_unitid = 0xff; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { @@ -576,7 +577,9 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } } - return max; + dev->bus->subordinate = max; + + return unused; } static struct device_operations northbridge_operations = { @@ -913,7 +916,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for (link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b2d8abd..a4f78f1 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -459,12 +459,14 @@ static void nb_set_resources(device_t dev) } } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; device_t io_hub = NULL; u32 next_unitid = 0x18; + unsigned int max = dev->bus->subordinate; + nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { for (link = dev->link_list; link; link = link->next) { @@ -479,7 +481,10 @@ static unsigned scan_chains(device_t dev, unsigned max) } } } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -948,8 +953,9 @@ static void domain_set_resources(device_t dev) /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + return link->subordinate; } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a2124f0..121cdf2 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -227,7 +227,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool max_bus = 0xfc; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = link->secondary; /* Read the existing primary/secondary/subordinate bus * number configuration. @@ -245,7 +245,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* set the config map space */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, max_bus, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -263,16 +263,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); + link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); - } - - link->subordinate = max; set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); sysconf.ht_c_num++; @@ -286,15 +281,16 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool sysconf.hcdn_reg[ht_c_index] = temp; } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); + return link->subordinate; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); @@ -312,7 +308,10 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -913,7 +912,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -924,7 +923,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for(link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. @@ -948,7 +949,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) @@ -1213,7 +1214,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1382,7 +1383,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 29cc5ed..51e1e2d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -171,7 +171,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ max_bus = 0xff; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = link->secondary; /* Read the existing primary/secondary/subordinate bus * number configuration. @@ -186,7 +186,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ busses &= 0xff000000; busses |= (((unsigned int)(dev->bus->secondary) << 0) | ((unsigned int)(link->secondary) << 8) | - ((unsigned int)(link->subordinate) << 16)); + (max_bus << 16)); pci_write_config32(dev, link->cap + 0x14, busses); config_busses &= 0x000fc88; @@ -195,7 +195,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (( nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | - ((link->subordinate) << 24); + (max_bus << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -213,12 +213,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); + link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; busses = (busses & 0xff00ffff) | ((unsigned int) (link->subordinate) << 16); pci_write_config32(dev, link->cap + 0x14, busses); @@ -239,14 +238,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ sysconf.hcdn_reg[index] = temp; } - return max; + return link->subordinate; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = 0; + unsigned int max = dev->bus->subordinate; nodeid = amdk8_nodeid(dev); if (nodeid == 0) @@ -266,7 +266,10 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -1096,11 +1099,16 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) { u32 reg; int i; + struct bus *link = dev->link_list; + /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); + + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe.

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Patch set updated for coreboot: c1aca90 PCI subsystem: Drop parameter max from scan_bus
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8539 -gerrit commit c1aca90f9cd823846224cefc7934b1502b7ce67d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 18 13:09:47 2015 +0200 PCI subsystem: Drop parameter max from scan_bus Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 9 +++------ src/device/pci_device.c | 24 ++++++++++-------------- src/device/pciexp_device.c | 7 +++---- src/include/device/pci.h | 9 ++++++--- src/include/device/pciexp.h | 5 +++-- src/include/device/pcix.h | 2 -- src/northbridge/amd/agesa/family10/northbridge.c | 6 ++++-- src/northbridge/amd/agesa/family15/northbridge.c | 6 ++++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- src/southbridge/amd/amd8131/bridge.c | 12 +++++------- src/southbridge/amd/amd8132/bridge.c | 13 +++++-------- 12 files changed, 47 insertions(+), 54 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 84b1aa7..799038c 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -488,11 +488,9 @@ end_of_chain: * @param bus TODO * @param min_devfn TODO * @param max_devfn TODO - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -static unsigned int hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn, unsigned int max) +static void hypertransport_scan_chain_x(struct bus *bus, + unsigned int min_devfn, unsigned int max_devfn) { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; @@ -501,8 +499,7 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, ht_unitid_base, offset_unitid); /* Now that nothing is overlapping it is safe to scan the children. */ - bus->subordinate = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, bus->secondary); - return bus->subordinate; + pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } unsigned int ht_scan_bridge(struct device *dev, unsigned int max) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index fe03d61..188f101 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1074,17 +1074,12 @@ unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) * Determine the existence of devices and bridges on a PCI bus. If there are * bridges on the bus, recursively scan the buses behind the bridges. * - * This function is the default scan_bus() method for the root device - * 'dev_root'. - * * @param bus Pointer to the bus structure. * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max) +void pci_scan_bus(struct bus *bus, unsigned min_devfn, + unsigned max_devfn) { unsigned int devfn; struct device *old_devices; @@ -1149,17 +1144,19 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ + unsigned int max = bus->secondary; + for (child = bus->children; child; child = child->sibling) max = scan_bus(child, max); + bus->subordinate = max; + /* * We've scanned the bus and so we know all about what's on the other * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max); post_code(0x55); - return max; } typedef enum { @@ -1228,10 +1225,9 @@ static void pci_bridge_route(struct bus *link, scan_state state) * @return The maximum bus number found, after scanning all subordinate buses. */ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, - unsigned int (*do_scan_bus) (struct bus * bus, + void (*do_scan_bus) (struct bus * bus, unsigned min_devfn, - unsigned max_devfn, - unsigned int max)) + unsigned max_devfn)) { struct bus *bus; @@ -1251,7 +1247,7 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, pci_bridge_route(bus, PCI_ROUTE_SCAN); - bus->subordinate = do_scan_bus(bus, 0x00, 0xff, bus->secondary); + do_scan_bus(bus, 0x00, 0xff); pci_bridge_route(bus, PCI_ROUTE_FINAL); @@ -1287,7 +1283,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); return unused; } diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f6127b2..5311397 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -416,12 +416,12 @@ static void pciexp_tune_dev(device_t dev) #endif } -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max) +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn) { device_t child; - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { if ((child->path.pci.devfn < min_devfn) || @@ -430,7 +430,6 @@ unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, } pciexp_tune_dev(child); } - return max; } unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 141d2e8..f1dcd03 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -70,11 +70,14 @@ void pci_dev_enable_resources(device_t dev); void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); + unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max)); + void (*do_scan_bus)(struct bus *bus, + unsigned min_devfn, unsigned max_devfn)); unsigned int pci_scan_bridge(device_t bus, unsigned int max); -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); + +void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn); + uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 1146557..b600228 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -9,8 +9,9 @@ enum aspm_type { PCIE_ASPM_BOTH = 3, }; -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn); + unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..75be7aa 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,8 +2,6 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); unsigned int pcix_scan_bridge(device_t dev, unsigned int max); const char *pcix_speed(u16 sstatus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index bb2f1d8..6ba6770 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -565,6 +565,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ io_hub = link->children; @@ -572,9 +573,10 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } dev->bus->subordinate = max; @@ -917,7 +919,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) for (link = dev->link_list; link; link = link->next) { link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); dev->bus->subordinate = link->subordinate; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 093d0c0..e480eba 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -469,6 +469,7 @@ static unsigned scan_chains(device_t dev, unsigned unused) nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ @@ -477,9 +478,10 @@ static unsigned scan_chains(device_t dev, unsigned unused) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } dev->bus->subordinate = max; @@ -954,7 +956,7 @@ static void domain_set_resources(device_t dev) static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); return unused; } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 121cdf2..ff36bf5 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -263,7 +263,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -924,7 +924,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) for(link = dev->link_list; link; link = link->next) { link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); dev->bus->subordinate = link->subordinate; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 22bc51c..63a25ab 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -213,7 +213,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -1107,7 +1107,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) } link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); dev->bus->subordinate = link->subordinate; /* Tune the hypertransport transaction for best performance. diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index e638fae..cb76980 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -192,16 +192,15 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) pci_write_config16(dev, cap + PCI_X_CMD, cmd); } } -static unsigned int amd8131_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8131_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8131_bus_info info; struct bus *pbus; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8131 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -243,13 +242,13 @@ static unsigned int amd8131_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } @@ -264,7 +263,6 @@ static unsigned int amd8131_scan_bus(struct bus *bus, bus_path(pbus)); pbus->disable_relaxed_ordering = 1; } - return max; } static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max) diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 2684e7c..48d7c51 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -138,15 +138,14 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) } -static unsigned int amd8132_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8132_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8132_bus_info info; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8132 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -181,20 +180,18 @@ static unsigned int amd8132_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } #endif /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } /* Tune the devices on the bus */ amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); - - return max; } static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)

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coreboot-gerrit May 2015