coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

1 participants
1299 discussions

Patch set updated for coreboot: c60f150 PCI subsystem: Refactor PCI bridge register control
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8536 -gerrit commit c60f150c9b42f8694fbc644e1974d90f846d0511 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 06:58:26 2015 +0200 PCI subsystem: Refactor PCI bridge register control Change-Id: I1766c92abe7a74326c49df74ba38930a502fcb5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 76 +++++++++++++++++++++++++++++---------------- src/include/device/device.h | 1 + 2 files changed, 51 insertions(+), 26 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e43d4e5..7ac560b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1162,6 +1162,53 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, return max; } +typedef enum { + PCI_ROUTE_CLOSE, + PCI_ROUTE_SCAN, + PCI_ROUTE_FINAL, +} scan_state; + +static void pci_bridge_route(struct bus *link, scan_state state) +{ + struct device *dev = link->dev; + struct bus *parent = dev->bus; + u32 reg, buses = 0; + + if (state == PCI_ROUTE_CLOSE) { + buses |= 0xfeff << 8; + } else if (state == PCI_ROUTE_SCAN) { + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= ((u32) link->subordinate & 0xff) << 16; + } else if (state == PCI_ROUTE_FINAL) { + buses |= parent->secondary & 0xff; + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= ((u32) link->subordinate & 0xff) << 16; + } + + if (state == PCI_ROUTE_SCAN) { + /* Clear all status bits and turn off memory, I/O and master enables. */ + link->bridge_cmd = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, 0x0000); + pci_write_config16(dev, PCI_STATUS, 0xffff); + } + + /* + * Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is not + * correctly configured. + */ + + reg = pci_read_config32(dev, PCI_PRIMARY_BUS); + reg &= 0xff000000; + reg |= buses; + pci_write_config32(dev, PCI_PRIMARY_BUS, reg); + + if (state == PCI_ROUTE_FINAL) { + pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); + } +} + + /** * Scan a PCI bridge and the buses behind the bridge. * @@ -1182,8 +1229,6 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, unsigned int max)) { struct bus *bus; - u32 buses; - u16 cr; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); @@ -1207,27 +1252,7 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, bus->secondary = ++max; bus->subordinate = 0xff; - /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, 0x0000); - pci_write_config16(dev, PCI_STATUS, 0xffff); - - /* - * Read the existing primary/secondary/subordinate bus - * number configuration. - */ - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - - /* - * Configure the bus numbers for this bridge: the configuration - * transactions will not be propagated by the bridge if it is not - * correctly configured. - */ - buses &= 0xff000000; - buses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(bus->secondary) << 8) | - ((unsigned int)(bus->subordinate) << 16)); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); + pci_bridge_route(bus, PCI_ROUTE_SCAN); /* Now we can scan all subordinate buses (those behind the bridge). */ max = do_scan_bus(bus, 0x00, 0xff, max); @@ -1237,9 +1262,8 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, * bus number to its real value. */ bus->subordinate = max; - buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - pci_write_config16(dev, PCI_COMMAND, cr); + + pci_bridge_route(bus, PCI_ROUTE_FINAL); printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); return max; diff --git a/src/include/device/device.h b/src/include/device/device.h index d9fc663..aec1af5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -81,6 +81,7 @@ struct bus { ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ + uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */

1 0

Patch set updated for coreboot: 8fddac5 PCI subsystem: Use subordinate property to track bus enumeration
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8537 -gerrit commit 8fddac599cc1370d5bfb059cf646c970c72c8dd9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 06:58:26 2015 +0200 PCI subsystem: Use subordinate property to track bus enumeration Parameter max is the cumulative number of PCI buses scanned on the system so far. Use the property subordinate from the parent PCI bridge device to keep track of the first available bus number instead of passing that on the stack. Change-Id: I1a884c98d50fa4f1eb2752e10b778aea8a7b090a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ac560b..fe03d61 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1174,11 +1174,16 @@ static void pci_bridge_route(struct bus *link, scan_state state) struct bus *parent = dev->bus; u32 reg, buses = 0; + if (state == PCI_ROUTE_SCAN) { + link->secondary = parent->subordinate + 1; + link->subordinate = link->secondary; + } + if (state == PCI_ROUTE_CLOSE) { buses |= 0xfeff << 8; } else if (state == PCI_ROUTE_SCAN) { buses |= ((u32) link->secondary & 0xff) << 8; - buses |= ((u32) link->subordinate & 0xff) << 16; + buses |= 0xff << 16; /* MAX PCI_BUS number here */ } else if (state == PCI_ROUTE_FINAL) { buses |= parent->secondary & 0xff; buses |= ((u32) link->secondary & 0xff) << 8; @@ -1205,10 +1210,10 @@ static void pci_bridge_route(struct bus *link, scan_state state) if (state == PCI_ROUTE_FINAL) { pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); + parent->subordinate = link->subordinate; } } - /** * Scan a PCI bridge and the buses behind the bridge. * @@ -1244,29 +1249,13 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, bus = dev->link_list; - /* - * Set up the primary, secondary and subordinate bus numbers. We have - * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. - */ - bus->secondary = ++max; - bus->subordinate = 0xff; - pci_bridge_route(bus, PCI_ROUTE_SCAN); - /* Now we can scan all subordinate buses (those behind the bridge). */ - max = do_scan_bus(bus, 0x00, 0xff, max); - - /* - * We know the number of buses behind this bridge. Set the subordinate - * bus number to its real value. - */ - bus->subordinate = max; + bus->subordinate = do_scan_bus(bus, 0x00, 0xff, bus->secondary); pci_bridge_route(bus, PCI_ROUTE_FINAL); - printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); - return max; + return bus->subordinate; } /**

1 0

Patch set updated for coreboot: 9c43564 devicetree: Rename unused parameter max in domain_scan_bus()
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8855 -gerrit commit 9c435645099864dd570649801163c1c234fc1be7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 15:26:52 2015 +0200 devicetree: Rename unused parameter max in domain_scan_bus() For the PCI root node, input parameter max==0 and output value max is not relevant for operation. Change-Id: I23adab24aa957c4d51d703098a9a40ed660b4e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 7 ++++--- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4651258..e43d4e5 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1271,10 +1271,11 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * @param max The highest bus number assigned up to now. * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff, link->secondary); + return unused; } /** diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index c9e4200..bb2f1d8 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -905,7 +905,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -942,7 +942,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5a08f23..093d0c0 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -951,11 +951,11 @@ static void domain_set_resources(device_t dev) } /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); - return link->subordinate; + return unused; } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c0174de..22bc51c 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1095,7 +1095,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -1131,7 +1131,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } static struct device_operations pci_domain_ops = {

1 0

Patch set updated for coreboot: 8373851 devicetree: Single scan_bridges()
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8540 -gerrit commit 8373851436ced90a3ac2c587d7335f868318010e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 20 21:28:31 2015 +0200 devicetree: Single scan_bridges() Change-Id: Ifd277992a69a4182e2fac92aaf746abe4fec2a1b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 21 +++++++++++++++++---- src/device/pci_device.c | 7 +------ src/device/root_device.c | 12 ++---------- src/include/device/device.h | 2 +- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 35bb6e2..a8900a6 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -916,15 +916,15 @@ int reset_bus(struct bus *bus) * @param max Current bus number. * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int scan_bus(struct device *busdev, unsigned int max) +static unsigned int scan_bus(struct device *busdev, unsigned int max) { unsigned int new_max; int do_scan_bus; - if (!busdev || !busdev->enabled || !busdev->ops || - !busdev->ops->scan_bus) { + if (!busdev->enabled) return max; - } + + printk(BIOS_SPEW, "%s scanning...\n", dev_path(busdev)); post_log_path(busdev); @@ -945,6 +945,19 @@ unsigned int scan_bus(struct device *busdev, unsigned int max) return new_max; } +void scan_bridges(struct bus *bus) +{ + struct device *child; + unsigned int max = bus->secondary; + + for (child = bus->children; child; child = child->sibling) { + if (!child->ops || !child->ops->scan_bus) + continue; + max = scan_bus(child, max); + } + bus->subordinate = max; +} + /** * Determine the existence of devices and extend the device tree. * diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 188f101..07b1993 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1083,7 +1083,6 @@ void pci_scan_bus(struct bus *bus, unsigned min_devfn, { unsigned int devfn; struct device *old_devices; - struct device *child; printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); @@ -1144,12 +1143,8 @@ void pci_scan_bus(struct bus *bus, unsigned min_devfn, * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ - unsigned int max = bus->secondary; - for (child = bus->children; child; child = child->sibling) - max = scan_bus(child, max); - - bus->subordinate = max; + scan_bridges(bus); /* * We've scanned the bus and so we know all about what's on the other diff --git a/src/device/root_device.c b/src/device/root_device.c index d4ad034..4eae12a 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -126,22 +126,14 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) */ static unsigned int root_dev_scan_bus(device_t bus, unsigned int passthru) { - device_t child; struct bus *link; - unsigned int max = 0; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); scan_static_bus(bus, 0); - for (link = bus->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (!child->ops || !child->ops->scan_bus) - continue; - printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); - max = scan_bus(child, max); - } - } + for (link = bus->link_list; link; link = link->next) + scan_bridges(link); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); diff --git a/src/include/device/device.h b/src/include/device/device.h index aec1af5..84a17d0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -172,7 +172,7 @@ void dev_finalize_chips(void); /* Generic device helper functions */ int reset_bus(struct bus *bus); -unsigned int scan_bus(struct device *bus, unsigned int _max); +void scan_bridges(struct bus *bus); void assign_resources(struct bus *bus); const char *dev_name(device_t dev); const char *dev_path(device_t dev);

1 0

Patch set updated for coreboot: 17ef2f3 devicetree: Change scan_bus() prototype in device ops
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8541 -gerrit commit 17ef2f370afd8d188ca72a9f56748bb0e612b83d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 21:04:23 2015 +0200 devicetree: Change scan_bus() prototype in device ops The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 16 +++++---------- src/device/hypertransport.c | 4 ++-- src/device/pci_device.c | 17 ++++----------- src/device/pciexp_device.c | 4 ++-- src/device/pcix_device.c | 6 ++---- src/device/root_device.c | 24 ++++++---------------- src/include/device/device.h | 8 ++++---- src/include/device/hypertransport.h | 3 ++- src/include/device/pci.h | 4 ++-- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 3 ++- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 ++--- src/northbridge/amd/agesa/family10/northbridge.c | 10 +++------ src/northbridge/amd/agesa/family14/northbridge.c | 3 +-- src/northbridge/amd/agesa/family15/northbridge.c | 10 +++------ src/northbridge/amd/agesa/family15rl/northbridge.c | 3 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 +-- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 +-- src/northbridge/amd/amdfam10/northbridge.c | 10 +++------ src/northbridge/amd/amdk8/northbridge.c | 10 +++------ src/northbridge/amd/pi/00630F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +-- src/northbridge/intel/i3100/pciexp_porta.c | 5 +++-- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 5 +++-- src/soc/intel/baytrail/pcie.c | 4 ++-- src/southbridge/amd/amd8131/bridge.c | 4 ++-- src/southbridge/amd/amd8132/bridge.c | 4 ++-- src/southbridge/amd/cs5536/cs5536.c | 4 ++-- src/southbridge/intel/bd82x6x/pcie.c | 7 ++----- src/southbridge/intel/i3100/pciexp_portb.c | 5 +++-- src/southbridge/intel/i82801ix/pcie.c | 7 ++----- 31 files changed, 73 insertions(+), 126 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index a8900a6..6bdeae1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -913,16 +913,13 @@ int reset_bus(struct bus *bus) * required, reset the bus and scan it again. * * @param busdev Pointer to the bus device. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate buses. */ -static unsigned int scan_bus(struct device *busdev, unsigned int max) +static void scan_bus(struct device *busdev) { - unsigned int new_max; int do_scan_bus; if (!busdev->enabled) - return max; + return; printk(BIOS_SPEW, "%s scanning...\n", dev_path(busdev)); @@ -931,7 +928,7 @@ static unsigned int scan_bus(struct device *busdev, unsigned int max) do_scan_bus = 1; while (do_scan_bus) { struct bus *link; - new_max = busdev->ops->scan_bus(busdev, max); + busdev->ops->scan_bus(busdev); do_scan_bus = 0; for (link = busdev->link_list; link; link = link->next) { if (link->reset_needed) { @@ -942,20 +939,17 @@ static unsigned int scan_bus(struct device *busdev, unsigned int max) } } } - return new_max; } void scan_bridges(struct bus *bus) { struct device *child; - unsigned int max = bus->secondary; for (child = bus->children; child; child = child->sibling) { if (!child->ops || !child->ops->scan_bus) continue; - max = scan_bus(child, max); + scan_bus(child); } - bus->subordinate = max; } /** @@ -999,7 +993,7 @@ void dev_enumerate(void) printk(BIOS_ERR, "dev_root missing scan_bus operation"); return; } - scan_bus(root, 0); + scan_bus(root); post_log_clear(); printk(BIOS_INFO, "done\n"); } diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 799038c..584ac78 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -502,9 +502,9 @@ static void hypertransport_scan_chain_x(struct bus *bus, pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } -unsigned int ht_scan_bridge(struct device *dev, unsigned int max) +void ht_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); + do_pci_scan_bridge(dev, hypertransport_scan_chain_x); } /** Default device operations for hypertransport bridges */ diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 07b1993..6332209 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1215,11 +1215,9 @@ static void pci_bridge_route(struct bus *link, scan_state state) * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. * @param do_scan_bus TODO - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, +void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus) (struct bus * bus, unsigned min_devfn, unsigned max_devfn)) @@ -1245,8 +1243,6 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, do_scan_bus(bus, 0x00, 0xff); pci_bridge_route(bus, PCI_ROUTE_FINAL); - - return bus->subordinate; } /** @@ -1258,12 +1254,10 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int pci_scan_bridge(struct device *dev, unsigned int max) +void pci_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); } /** @@ -1272,14 +1266,11 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * This function is the default scan_bus() method for PCI domains. * * @param dev Pointer to the domain. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) +void pci_domain_scan_bus(device_t dev) { struct bus *link = dev->link_list; pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - return unused; } /** diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 5311397..ee24456 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -432,9 +432,9 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, } } -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) +void pciexp_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); + do_pci_scan_bridge(dev, pciexp_scan_bus); } /** Default device operations for PCI Express bridges */ diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index cfa2f91..7ed64df 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -112,12 +112,12 @@ const char *pcix_speed(u16 sstatus) return result; } -unsigned int pcix_scan_bridge(device_t dev, unsigned int max) +void pcix_scan_bridge(device_t dev) { unsigned int pos; u16 sstatus; - max = do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); /* Find the PCI-X capability. */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); @@ -129,8 +129,6 @@ unsigned int pcix_scan_bridge(device_t dev, unsigned int max) /* Print the PCI-X bus speed. */ printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, pcix_speed(sstatus)); - - return max; } /** Default device operations for PCI-X bridges */ diff --git a/src/device/root_device.c b/src/device/root_device.c index 4eae12a..0185275 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -45,11 +45,9 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * file under some static bus in order to be enumerated at run time. * * @param bus Pointer to the device to which the static buses are attached to. - * @param max Maximum bus number currently used before scanning. - * @return The largest bus number used. */ -static unsigned int scan_static_bus(device_t bus, unsigned int passthru) +static void scan_static_bus(device_t bus) { device_t child; struct bus *link; @@ -67,22 +65,18 @@ static unsigned int scan_static_bus(device_t bus, unsigned int passthru) child->enabled ? "enabled" : "disabled"); } } - - return passthru; } -unsigned int scan_lpc_bus(device_t bus, unsigned int passthru) +void scan_lpc_bus(device_t bus) { printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus, 0); + scan_static_bus(bus); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } -unsigned int scan_smbus(device_t bus, unsigned int passthru) +void scan_smbus(device_t bus) { device_t child; struct bus *link; @@ -111,8 +105,6 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) } printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } /** @@ -121,23 +113,19 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) * This function is the default scan_bus() method of the root device. * * @param root The root device structure. - * @param max The current bus number scanned so far, usually 0x00. - * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t bus, unsigned int passthru) +static void root_dev_scan_bus(device_t bus) { struct bus *link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus, 0); + scan_static_bus(bus); for (link = bus->link_list; link; link = link->next) scan_bridges(link); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } static void root_dev_reset(struct bus *bus) diff --git a/src/include/device/device.h b/src/include/device/device.h index 84a17d0..9c53f95 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -46,7 +46,7 @@ struct device_operations { void (*enable_resources)(device_t dev); void (*init)(device_t dev); void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); + void (*scan_bus)(device_t bus); void (*enable)(device_t dev); void (*disable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); @@ -224,13 +224,13 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); -unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); +void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); -unsigned int scan_smbus(device_t bus, unsigned int _max); -unsigned int scan_lpc_bus(device_t bus, unsigned int _max); +void scan_smbus(device_t bus); +void scan_lpc_bus(device_t bus); /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 03e327d..22e0ac4 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -5,7 +5,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unit_base, unsigned offset_unitid); -unsigned int ht_scan_bridge(struct device *dev, unsigned int max); +void ht_scan_bridge(struct device *dev); + extern struct device_operations default_ht_ops_bus; #define HT_IO_HOST_ALIGN 4096 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1dcd03..2a76ba9 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -71,11 +71,11 @@ void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +void do_pci_scan_bridge(device_t bus, void (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +void pci_scan_bridge(device_t bus); void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn); uint8_t pci_moving_config8(struct device *dev, unsigned reg); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index b600228..f3df1a5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -12,7 +12,7 @@ enum aspm_type { void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +void pciexp_scan_bridge(device_t dev); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 75be7aa..024c548 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,7 +2,8 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +void pcix_scan_bridge(device_t dev); + const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 1967c8b..26cbda5 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -241,14 +241,14 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int passthru) +static void cpu_bus_scan(device_t bus) { int max_cpus = fw_cfg_max_cpus(); device_t cpu; int i; if (max_cpus < 0) - return 0; + return; /* * TODO: This only handles the simple "qemu -smp $nr" case @@ -261,7 +261,6 @@ static unsigned int cpu_bus_scan(device_t bus, unsigned int passthru) if (cpu) set_cpu_topology(cpu, 1, 0, i, 0); } - return max_cpus; } static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6ba6770..0fe1910 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -554,7 +554,7 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -580,8 +580,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } static struct device_operations northbridge_operations = { @@ -907,7 +905,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -944,7 +942,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } @@ -1012,7 +1009,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1188,7 +1185,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 426ec74..32b74f6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -765,7 +765,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static u32 cpu_bus_scan(struct device *dev, u32 passthru) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus = dev->link_list; device_t cpu; @@ -784,7 +784,6 @@ static u32 cpu_bus_scan(struct device *dev, u32 passthru) if (cpu) amd_cpu_topology(cpu, 0, apic_id); } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index e480eba..94e16ac 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -459,7 +459,7 @@ static void nb_set_resources(device_t dev) } } -static unsigned scan_chains(device_t dev, unsigned unused) +static void scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -485,8 +485,6 @@ static unsigned scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -953,11 +951,10 @@ static void domain_set_resources(device_t dev) } /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) +static void f15_pci_domain_scan_bus(device_t dev) { struct bus *link = dev->link_list; pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); - return unused; } static struct device_operations pci_domain_ops = { @@ -1011,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1184,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d322fdc..0a1e7d3 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -992,7 +992,7 @@ static void add_more_links(struct device *dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1166,7 +1166,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 08287dc..37b6a8e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -991,7 +991,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1165,7 +1165,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 7c603c0..9bbc279 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1008,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1182,7 +1182,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index ff36bf5..4734522 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -285,7 +285,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool return link->subordinate; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -310,8 +310,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -912,7 +910,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -949,7 +947,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) @@ -1214,7 +1211,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1383,7 +1380,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 63a25ab..45cff9e 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -241,7 +241,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ return link->subordinate; } -static unsigned amdk8_scan_chains(device_t dev, unsigned unused) +static void amdk8_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -268,8 +268,6 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -1095,7 +1093,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) +static void amdk8_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -1131,7 +1129,6 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } static struct device_operations pci_domain_ops = { @@ -1180,7 +1177,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1319,7 +1316,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index e0fc11e..60a1d49 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -985,7 +985,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1176,7 +1176,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 71099d9..8e340ce 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1001,7 +1001,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1187,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index b37e3cf..a4be7a6 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -45,7 +45,7 @@ static void pcie_init(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -62,7 +62,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 31cd29f..f7e3a6a 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -67,7 +67,7 @@ static void pcie_bus_enable_resources(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -84,7 +84,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index e4c0654..4a050fa 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -230,7 +230,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) +static void byt_pciexp_scan_bridge(device_t dev) { static const struct reg_script wait_for_link_active[] = { REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), @@ -240,7 +240,7 @@ static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) /* wait for Link Active with 50ms timeout */ reg_script_run_on_dev(dev, wait_for_link_active); - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); + do_pci_scan_bridge(dev, pciexp_scan_bus); } static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index cb76980..1587268 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -265,9 +265,9 @@ static void amd8131_scan_bus(struct bus *bus, } } -static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max) +static void amd8131_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8131_scan_bus); + do_pci_scan_bridge(dev, amd8131_scan_bus); } diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 48d7c51..027a085 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -194,9 +194,9 @@ static void amd8132_scan_bus(struct bus *bus, amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); } -static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max) +static void amd8132_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8132_scan_bus); + do_pci_scan_bridge(dev, amd8132_scan_bus); } diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index cece16d..67eabb0 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -688,10 +688,10 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; -static unsigned int scan_lpc_smbus(device_t dev, unsigned int max) +static void scan_lpc_smbus(device_t dev) { /* FIXME. Do we have mixed LPC/SMBus device node here. */ - return scan_smbus(dev, max); + scan_smbus(dev); } static struct device_operations southbridge_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 42a8578..1b8ac76 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -273,13 +273,12 @@ static void pch_pcie_enable(device_t dev) pch_pcie_pm_early(dev); } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); @@ -287,8 +286,6 @@ static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); - - return ret; } static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c index 815c081..41e921c 100644 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ b/src/southbridge/intel/i3100/pciexp_portb.c @@ -39,7 +39,7 @@ static void pcie_init(struct device *dev) { } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -56,7 +56,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 58c0e19..5858176 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -110,19 +110,16 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_i82801ix_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } - - return ret; } static struct pci_operations pci_ops = {

1 0

Patch set updated for coreboot: fa85811 devicetree: Discriminate device ops scan_bus()
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8534 -gerrit commit fa8581159e9ad3baf87fcb8422d70ba1994dbf13 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 26 20:47:47 2015 +0200 devicetree: Discriminate device ops scan_bus() Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/root_device.c | 84 ++++++++++++++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 7 +-- src/drivers/i2c/i2cmux2/i2cmux2.c | 7 +-- src/include/device/device.h | 3 +- src/mainboard/lippert/frontrunner/devicetree.cb | 6 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/traf_ctrl.c | 5 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/smbus.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/agesa/hudson/sm.c | 2 +- src/southbridge/amd/amd8111/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/amd8111/smbus.c | 2 +- src/southbridge/amd/amd8111/usb.c | 2 - src/southbridge/amd/cimx/sb700/late.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 2 +- src/southbridge/amd/cs5535/cs5535.c | 1 - src/southbridge/amd/cs5536/cs5536.c | 9 ++- src/southbridge/amd/pi/hudson/lpc.c | 2 +- src/southbridge/amd/pi/hudson/sm.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb600/sm.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sm.c | 2 +- src/southbridge/broadcom/bcm5785/lpc.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 1 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 2 +- src/southbridge/intel/esb6300/smbus.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 1 - src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 1 - src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/fsp_rangeley/smbus.c | 2 +- src/southbridge/intel/i3100/lpc.c | 2 +- src/southbridge/intel/i3100/smbus.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 2 +- src/southbridge/intel/i82801ax/smbus.c | 2 +- src/southbridge/intel/i82801bx/lpc.c | 2 +- src/southbridge/intel/i82801bx/smbus.c | 2 +- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801ex/lpc.c | 2 +- src/southbridge/intel/i82801ex/smbus.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smbus.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/smbus.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 1 - src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/southbridge/intel/sch/lpc.c | 2 +- src/southbridge/intel/sch/smbus.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/ck804/smbus.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 2 +- src/southbridge/rdc/r8610/r8610.c | 1 - src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 6 +- src/superio/smsc/lpc47b397/superio.c | 1 - 77 files changed, 140 insertions(+), 117 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 1ec6f7f..0575b56 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -44,51 +44,69 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * debug device. Those virtual devices have to be listed in the config * file under some static bus in order to be enumerated at run time. * - * This function is the default scan_bus() method for the root device and - * LPC bridges. - * * @param bus Pointer to the device to which the static buses are attached to. * @param max Maximum bus number currently used before scanning. * @return The largest bus number used. */ -static int smbus_max = 0; -unsigned int scan_static_bus(device_t bus, unsigned int max) + +static unsigned int scan_static_bus(device_t bus, unsigned int max) { device_t child; struct bus *link; - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for (link = bus->link_list; link; link = link->next) { - /* For SMBus bus enumerate. */ - child = link->children; - - if (child && child->path.type == DEVICE_PATH_I2C) - link->secondary = ++smbus_max; - for (child = link->children; child; child = child->sibling) { + if (child->chip_ops && child->chip_ops->enable_dev) child->chip_ops->enable_dev(child); if (child->ops && child->ops->enable) child->ops->enable(child); - if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), - child->bus->link_num); - } printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled ? "enabled" : "disabled"); } } + return max; +} + +unsigned int scan_lpc_bus(device_t bus, unsigned int max) +{ + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + max = scan_static_bus(bus, max); + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); + + return max; +} + +unsigned int scan_smbus(device_t bus, unsigned int max) +{ + device_t child; + struct bus *link; + static int smbus_max = 0; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + for (link = bus->link_list; link; link = link->next) { + + link->secondary = ++smbus_max; + for (child = link->children; child; child = child->sibling) { - if (!child->ops || !child->ops->scan_bus) - continue; - printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); - max = scan_bus(child, max); + + if (child->chip_ops && child->chip_ops->enable_dev) + child->chip_ops->enable_dev(child); + + if (child->ops && child->ops->enable) + child->ops->enable(child); + + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev), + child->bus->link_num); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(child), + child->enabled ? "enabled" : "disabled"); } } @@ -106,9 +124,27 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) * @param max The current bus number scanned so far, usually 0x00. * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t root, unsigned int max) +static unsigned int root_dev_scan_bus(device_t bus, unsigned int max) { - return scan_static_bus(root, max); + device_t child; + struct bus *link; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + max = scan_static_bus(bus, max); + + for (link = bus->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (!child->ops || !child->ops->scan_bus) + continue; + printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); + max = scan_bus(child, max); + } + } + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); + + return max; } static void root_dev_reset(struct bus *bus) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 1091653..ef5ab3a 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux_set_link(struct device *dev, unsigned int link) { @@ -21,7 +16,7 @@ static struct device_operations i2cmux_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux_set_link, }; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index fe48e76..4d1241a 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux2_set_link(struct device *dev, unsigned int link) { @@ -20,7 +15,7 @@ static struct device_operations i2cmux2_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux2_set_link, }; diff --git a/src/include/device/device.h b/src/include/device/device.h index 0acebb8..d9fc663 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -224,11 +224,12 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); +unsigned int scan_smbus(device_t bus, unsigned int _max); +unsigned int scan_lpc_bus(device_t bus, unsigned int _max); /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 78d099a..239f1f9 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -6,10 +6,10 @@ chip northbridge/amd/gx2 end device domain 0 on - device pci 0.0 on end + device pci 0.0 on chip southbridge/amd/cs5535 - register "setupflash" = "0" - device pci 12.0 on + register "setupflash" = "0" + device pci 12.0 on end device pci 12.1 off end # SMI device pci 12.2 on end # IDE device pci 12.3 off end # Audio diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 91a9930..483f19e 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -297,7 +297,7 @@ static struct device_operations cx700_lpc_ops = { .set_resources = cx700_set_resources, .enable_resources = cx700_enable_resources, .init = cx700_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 00955b0..be39acd 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -362,7 +362,7 @@ static struct device_operations vx800_lpc_ops = { .set_resources = vx800_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 61a8a7b..f6c4c6a 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -192,7 +192,7 @@ static struct device_operations vx900_lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index fb15193..011bb41 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -134,8 +134,9 @@ static struct device_operations traf_ctrl_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_traf_ctr_init, - /* Need this here, or the IOAPIC driver won't be called */ - .scan_bus = scan_static_bus, + /* Need this here, or the IOAPIC driver won't be called. + * FIXME: Technically not a LPC bus. */ + .scan_bus = scan_lpc_bus, }; static const struct pci_driver traf_ctrl_driver __pci_driver = { diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 365ac3d..26e0156 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -546,7 +546,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 0acfe78..13c975f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -643,7 +643,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = &lpc_init, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_lpc_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index e0f9b8a..5660a41 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -94,7 +94,7 @@ static struct device_operations smbus_ops = { .read_resources = &smbus_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_smbus, .init = &pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &broadwell_pci_ops, diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 44127ee..ac80478 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -607,7 +607,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index f3a525c..65cb955 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -333,7 +333,7 @@ static struct device_operations lpc_ops = { #endif .enable_resources = hudson_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 6d0ce26..396b7c4 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -226,7 +226,7 @@ static struct device_operations acpi_ops = { .set_resources = pci_dev_set_resources, .enable_resources = acpi_enable_resources, .init = acpi_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* We don't need amd8111_enable, chip ops takes care of it. * It could be useful if these devices were not * enabled by default. diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 2ded0cb..47b9ae7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -151,7 +151,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c index 0a0c58d..def1377 100644 --- a/src/southbridge/amd/amd8111/smbus.c +++ b/src/southbridge/amd/amd8111/smbus.c @@ -28,7 +28,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c index 13dccf4..feb7793 100644 --- a/src/southbridge/amd/amd8111/usb.c +++ b/src/southbridge/amd/amd8111/usb.c @@ -25,8 +25,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, -// .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4254a5c..cd36fac 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -111,7 +111,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 79c2203..0ada673 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -161,7 +161,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 7249ec5..fbff7df 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -132,7 +132,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index e66a1e2..70b8386 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -94,7 +94,6 @@ static struct device_operations southbridge_ops = { .enable_resources = pci_dev_enable_resources, .init = southbridge_init, .enable = southbridge_enable, - .scan_bus = scan_static_bus, }; static const struct pci_driver cs5535_pci_driver __pci_driver = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 0db8195..cece16d 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -688,13 +688,18 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; +static unsigned int scan_lpc_smbus(device_t dev, unsigned int max) +{ + /* FIXME. Do we have mixed LPC/SMBus device node here. */ + return scan_smbus(dev, max); +} + static struct device_operations southbridge_ops = { .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, -// .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_smbus, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 840ff7a..b813d12 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -340,7 +340,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 62c88de..2fb9e22 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -242,7 +242,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 0254f83..40fde47 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -361,7 +361,7 @@ static struct device_operations smbus_ops = { .set_resources = sb600_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be3c4d6..94d8dcb 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -287,7 +287,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2a88a80..f544c88 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -452,7 +452,7 @@ static struct device_operations smbus_ops = { .set_resources = sb700_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 5a40a8d..0cd5b32 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -254,7 +254,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index b34cfbd..1523c60 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -343,7 +343,7 @@ static struct device_operations smbus_ops = { .set_resources = sb800_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 28e8a8f..ef70df6 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -135,7 +135,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index bddb090..3390b0d 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -154,7 +154,7 @@ static struct device_operations sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sb_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 19b4757..192de74 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -619,7 +619,7 @@ static struct device_operations vortex_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c1bc45f..fec0d5c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -827,7 +827,7 @@ static struct device_operations device_ops = { .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ed25e44..ab3d475 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -760,7 +760,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 75e517f..6bd26c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -763,7 +763,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 94546a7..0198841 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -151,7 +151,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index 22bb150..e1718bb 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -362,7 +362,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = esb6300_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = esb6300_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c index 92cb288..2c026b8 100644 --- a/src/southbridge/intel/esb6300/smbus.c +++ b/src/southbridge/intel/esb6300/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = esb6300_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 1d92532..b410332 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -761,7 +761,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index ab6ae09..8f65da3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -759,7 +759,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 5e7b661..292dbba 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -762,7 +762,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3aee7ed..22de62d 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -463,7 +463,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 8368afe..7864b1e 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -87,7 +87,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index b29180c..aef855f 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -457,7 +457,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i3100_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c index 445b668..2feb00f 100644 --- a/src/southbridge/intel/i3100/smbus.c +++ b/src/southbridge/intel/i3100/smbus.c @@ -74,7 +74,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i3100_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1945fae..024604b 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -145,7 +145,7 @@ static const struct device_operations isa_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, - .scan_bus = scan_static_bus, /* TODO: Needed? */ + .scan_bus = scan_lpc_bus, /* TODO: Needed? */ .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 82647e1..3817357 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -121,7 +121,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = pwrmgt_enable, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 4bd69d6..e960551 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -286,7 +286,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ax_enable, }; diff --git a/src/southbridge/intel/i82801ax/smbus.c b/src/southbridge/intel/i82801ax/smbus.c index cbe9e4a..76a78d1 100644 --- a/src/southbridge/intel/i82801ax/smbus.c +++ b/src/southbridge/intel/i82801ax/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ax_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index edadf40..7247cdc 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -304,7 +304,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801bx_enable, }; diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c index 8feb75b..836c256 100644 --- a/src/southbridge/intel/i82801bx/smbus.c +++ b/src/southbridge/intel/i82801bx/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801bx_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 22671c3..a348c95 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -230,7 +230,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, }; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 9f2a23f..29a457a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -336,7 +336,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 0a2f6e3..630484a 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -369,7 +369,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = i82801ex_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index fe49e11..75ea119 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ex_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index bf61855..5ff8c24 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -667,7 +667,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 585d16c..e556d72 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -258,7 +258,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 3cc053b..8713e55 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -582,7 +582,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 635cb19..9ae267d 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -101,7 +101,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f066b35..e46bea6 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -805,7 +805,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e68bb01..96e16e3 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -634,7 +634,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 085aec0..2bb4cbf 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -108,7 +108,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c055da5..4b7de54 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -834,7 +834,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index ae16a92..b7c8503 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -155,7 +155,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index e40b051..e961e4f 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -222,7 +222,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c index d208fcc..c3bff67 100644 --- a/src/southbridge/intel/sch/smbus.c +++ b/src/southbridge/intel/sch/smbus.c @@ -65,7 +65,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c6f8c24..406b4f2 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -329,7 +329,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &ck804_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index f5fa1d5..2803df0 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -96,7 +96,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &ck804_pci_ops, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d9c6211..d3399f3 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -261,7 +261,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 91d5830..2a56069 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -127,7 +127,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = mcp55_sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c index 338a133..328f3be 100644 --- a/src/southbridge/rdc/r8610/r8610.c +++ b/src/southbridge/rdc/r8610/r8610.c @@ -105,7 +105,6 @@ static struct device_operations r8610_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 9194420..e5eaa06 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -259,7 +259,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = sis966_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = sis966_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ebaaa04..f7f2dbe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -657,7 +657,7 @@ static const struct device_operations vt8237r_lpc_ops_s = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237s_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -666,7 +666,7 @@ static const struct device_operations vt8237r_lpc_ops_r = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237r_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -675,7 +675,7 @@ static const struct device_operations vt8237r_lpc_ops_a = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237a_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 8c7d70f..a9a8092 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -134,7 +134,6 @@ static struct device_operations ops_hwm = { .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, .ops_pnp_mode = &pnp_conf_mode_55_aa, };

1 0

Patch set updated for coreboot: 2bbed0a devicetree: Rename unused parameter to passthru
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8535 -gerrit commit 2bbed0aee0969ee75c8a5e120d3b0e930e1cdd8a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 25 07:38:01 2015 +0200 devicetree: Rename unused parameter to passthru The actual use of the parameter max is to keep track of PCI bus number while recursively scanning PCI bridges or PCI-e rootports. Neither CPU, SMBus, LPC or other static buses are involved in this enumeration, but the way bridge operations were originally designed forced to pass this argument thru unrelated functions. Follow-up removes these once the function prototype gets fixed. Change-Id: Idbc9c515a362c571a1798bb36972058b309c2774 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/root_device.c | 21 +++++++++++---------- src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ++-- 11 files changed, 30 insertions(+), 29 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 0575b56..d4ad034 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -49,7 +49,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * @return The largest bus number used. */ -static unsigned int scan_static_bus(device_t bus, unsigned int max) +static unsigned int scan_static_bus(device_t bus, unsigned int passthru) { device_t child; struct bus *link; @@ -68,21 +68,21 @@ static unsigned int scan_static_bus(device_t bus, unsigned int max) } } - return max; + return passthru; } -unsigned int scan_lpc_bus(device_t bus, unsigned int max) +unsigned int scan_lpc_bus(device_t bus, unsigned int passthru) { printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - max = scan_static_bus(bus, max); + scan_static_bus(bus, 0); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - return max; + return passthru; } -unsigned int scan_smbus(device_t bus, unsigned int max) +unsigned int scan_smbus(device_t bus, unsigned int passthru) { device_t child; struct bus *link; @@ -112,7 +112,7 @@ unsigned int scan_smbus(device_t bus, unsigned int max) printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - return max; + return passthru; } /** @@ -124,14 +124,15 @@ unsigned int scan_smbus(device_t bus, unsigned int max) * @param max The current bus number scanned so far, usually 0x00. * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t bus, unsigned int max) +static unsigned int root_dev_scan_bus(device_t bus, unsigned int passthru) { device_t child; struct bus *link; + unsigned int max = 0; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - max = scan_static_bus(bus, max); + scan_static_bus(bus, 0); for (link = bus->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { @@ -144,7 +145,7 @@ static unsigned int root_dev_scan_bus(device_t bus, unsigned int max) printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - return max; + return passthru; } static void root_dev_reset(struct bus *bus) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f12a272..1967c8b 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -241,7 +241,7 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(device_t bus, unsigned int passthru) { int max_cpus = fw_cfg_max_cpus(); device_t cpu; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 9f2555f..c9e4200 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1010,7 +1010,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1186,7 +1186,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 355a458..426ec74 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -765,7 +765,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static u32 cpu_bus_scan(struct device *dev, u32 max) +static u32 cpu_bus_scan(struct device *dev, u32 passthru) { struct bus *cpu_bus = dev->link_list; device_t cpu; @@ -784,7 +784,7 @@ static u32 cpu_bus_scan(struct device *dev, u32 max) if (cpu) amd_cpu_topology(cpu, 0, apic_id); } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a4f78f1..5a08f23 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1009,7 +1009,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1185,7 +1185,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 1f11f1d..d322fdc 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -992,7 +992,7 @@ static void add_more_links(struct device *dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1166,7 +1166,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c39ebd1..08287dc 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -991,7 +991,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1165,7 +1165,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d1b06ec..7c603c0 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1008,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1182,7 +1182,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 51e1e2d..c0174de 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1180,7 +1180,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1319,7 +1319,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 15892c6..e0fc11e 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -985,7 +985,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1176,7 +1176,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c44c189..71099d9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1001,7 +1001,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(device_t dev, u32 passthru) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1187,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; + return passthru; } static void cpu_bus_init(device_t dev)

1 0

Patch set updated for coreboot: ac11737 HyperTransport: Move pci_scan_bus() call
by Kyösti Mälkki 29 May '15

29 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8687 -gerrit commit ac11737d64bf1c53c349c2f1d288567ccb6c82a2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 16:16:59 2015 +0200 HyperTransport: Move pci_scan_bus() call Allows to remove parameter max from the call, it is not involved with the unitid assignment. Change-Id: I087622f4ff69474f0b27cfd8709106ab8ac4ca98 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 13 ++++++++----- src/include/device/hypertransport.h | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 6 +++++- src/northbridge/amd/amdk8/northbridge.c | 6 +++++- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index a15a021..1a2e7ff 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -249,7 +249,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, } unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max, + unsigned max_devfn, unsigned *ht_unitid_base, unsigned offset_unitid) { @@ -474,9 +474,7 @@ end_of_chain: last_func->sibling = old_devices; } - /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max); - return max; + return next_unitid; } /** @@ -498,8 +496,13 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; - return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, + + unsigned int next_unitid = hypertransport_scan_chain(bus, min_devfn, max_devfn, ht_unitid_base, offset_unitid); + + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max); + return max; } unsigned int ht_scan_bridge(struct device *dev, unsigned int max) diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index e927d61..03e327d 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -4,7 +4,7 @@ #include <device/hypertransport_def.h> unsigned int hypertransport_scan_chain(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); + unsigned min_devfn, unsigned max_devfn, unsigned *ht_unit_base, unsigned offset_unitid); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_ht_ops_bus; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3fb0beb..a2124f0 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -165,6 +165,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; + unsigned int next_unitid; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; @@ -259,7 +260,10 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f2e0e4c..29cc5ed 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -105,6 +105,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 max) { int i; + unsigned int next_unitid; u32 busses, config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain @@ -209,7 +210,10 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value

1 0

New patch to review for coreboot: 6cf2548 autoport: Minor style fixes in readme.
by Vladimir Serbinenko 29 May '15

29 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10368 -gerrit commit 6cf2548630a8c7656cba580f034d1c2b3dd4750f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 29 12:12:28 2015 +0200 autoport: Minor style fixes in readme. Change-Id: I089ec3d68e734820d13bb68a7122dfdb89c3f6a3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/readme.md | 129 ++++++++++++++++++++++++------------------------ 1 file changed, 65 insertions(+), 64 deletions(-) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 4f535fd..e5ea77d 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -2,16 +2,17 @@ ## Supported platforms -### Chipset. +### Chipset For any sandybridge or ivybridge platform generated result should be bootable, possibly with minor fixes. ### EC -EC support is likely to work on intel-based thinkpads. Other laptops are likely to miss EC support +EC support is likely to work on intel-based thinkpads. Other laptops are +likely to miss EC support ## How to use -* Go into BIOS setup on target machine and enable all the device. +* Go into BIOS setup on target machine and enable all the devices. This will allow autoport to detect as much as possible * Boot into target machine under GNU/Linux * Make sure you have GCC and golang installed @@ -91,14 +92,14 @@ up in SPD. Under Linux you can see present SPD addresses with following commands I will probe address range 0x03-0x77. Continue? [Y/n] y 0 1 2 3 4 5 6 7 8 9 a b c d e f - 00: -- -- -- -- -- 08 -- -- -- -- -- -- -- - 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 20: -- -- -- -- 24 -- -- -- -- -- -- -- -- -- -- -- - 30: 30 31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 50: 50 -- -- -- 54 55 56 57 -- -- -- -- 5c 5d 5e 5f - 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 70: -- -- -- -- -- -- -- -- + 00: -- -- -- -- -- 08 -- -- -- -- -- -- -- + 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 20: -- -- -- -- 24 -- -- -- -- -- -- -- -- -- -- -- + 30: 30 31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 50: 50 -- -- -- 54 55 56 57 -- -- -- -- 5c 5d 5e 5f + 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 70: -- -- -- -- -- -- -- -- Make sure to replace `9` with whatever bus is marked as smbus. Here in an example you see SPD at address `0x50`. Since we've booted with just the module in C0S0, so @@ -116,7 +117,7 @@ You can and should omit lines which correspond to slots not present on your machine. This way works well if your RAM is socketed. For soldered RAM if you see -its SPD, you're in a luck and can proceed the same way although you may have to +its SPD, you're in luck and can proceed the same way although you may have to guess some entries due to RAM not being removable. Most cases of soldered RAM don't have EEPROM chip. In this case you'd have to create @@ -124,39 +125,39 @@ fake SPD. Look in `inteltool.log`. You'll see something like: /* SPD matching current mode: */ /* CH0S0 */ - 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 - 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 - 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 - 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 - 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 + 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 + 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 + 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 + 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 /* CH1S0 */ - 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 - 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 - 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 - 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 - 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 + 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 + 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 + 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 + 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 This is not completely exact represantation of RAM capablities as it lists only the mode currently used @@ -164,22 +165,22 @@ and lacks minor info like serial number. Using `xxd` you can create binary represantation of this SPD: cat | xxd -r > spd.bin <<EOF - 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 - 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 - 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 - 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 - 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 + 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 + 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 + 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 + 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EOF Then you can place this file into mainboard directory @@ -295,11 +296,11 @@ your device has very special power saving requirements. ## `install_intel_vga_int15_handler` -This is used to configure int15 hook used by vga bios. Parameters 2 and 3 usually -shouldn't be modified as vgabios is quite ok to figure panel fit and active output -by itself. Last number is the numerical ID of display type. If you don't get any output -with VGABIOS you should try different values for 4th parameter. If it doesn't help -try different values for first parameter as well +This is used to configure int15 hook used by vgabios. Parameters 2 and 3 usually +shouldn't be modified as vgabios is quite ok to figure panel fit and active +output by itself. Last number is the numerical ID of display type. If you +don't get any output with vgabios you should try different values for 4th +parameter. If it doesn't help try different values for first parameter as well ## CMOS options

1 0

Patch merged into coreboot/master: 3129f79 autoport: Write autoport together with porting guide for sandy/ivybridge.
by gerrit＠coreboot.org 29 May '15

29 May '15

the following patch was just integrated into master: commit 3129f792f77e310ea246503f8b68b76fc269cfd2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Write autoport together with porting guide for sandy/ivybridge. This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/7131 for details. -gerrit

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
130
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2015