the following patch was just integrated into master:
commit 9eebbd4151a692fddce93d3ff6986d37f7a44b56
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Mar 26 14:55:34 2015 -0500
x86: set smbios rom size based on CONFIG_ROM_SIZE
Instead of relying on the CBFS header's romsize field use
the CONFIG_ROM_SIZE Kconfig variable. That value is what is
used to create the rom file as it is. Therefore, just remove
the dependency.
Change-Id: If855d7378df20080061e27e4988e96aee233d1e0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9130
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/9130 for details.
-gerrit
the following patch was just integrated into master:
commit 22564088c7ac48cfe03a61451d8f9d4b08dbe8b4
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Fri Mar 27 22:49:18 2015 -0500
mainboards/amdfam10: Copy DIMM information to cbmem after romstage
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info()
function.
Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9138
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)gmail.com>
See http://review.coreboot.org/9138 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9217
-gerrit
commit c2ccc1ca2ac904ae31b79f73b303886fc98aae09
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sat Sep 27 20:04:49 2014 -0700
chromeec: Add wakeup delay after SPI /CS assertion
Some ECs may require a few microseconds to ramp up their clock after
being awaken by /CS assertion. This adds a Kconfig variable that can
be overridden at the mainboard-level which will force a delay between
asserting /CS and beginning a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer
Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585
Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220242
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 7 +++++++
src/ec/google/chromeec/ec_spi.c | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index bec12fb..32a4213 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -43,6 +43,13 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
depends on EC_GOOGLE_CHROMEEC_SPI
hex "SPI bus for Google's Chrome EC"
+config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
+ depends on EC_GOOGLE_CHROMEEC_SPI
+ int
+ default 0
+ help
+ Force delay after asserting /CS to allow EC to wakeup.
+
config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI
hex
diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c
index 4b3e587..d11348c 100644
--- a/src/ec/google/chromeec/ec_spi.c
+++ b/src/ec/google/chromeec/ec_spi.c
@@ -18,6 +18,7 @@
*/
#include <console/console.h>
+#include <delay.h>
#include "ec.h"
#include "ec_commands.h"
#include <spi-generic.h>
@@ -50,6 +51,10 @@ static int crosec_spi_io(size_t req_size, size_t resp_size, void *context)
spi_claim_bus(slave);
+ /* Allow EC to ramp up clock after being awaken.
+ * See chrome-os-partner:32223 for more details. */
+ udelay(CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US);
+
if (spi_xfer(slave, req_buf, req_size, NULL, 0)) {
printk(BIOS_ERR, "%s: Failed to send request.\n", __func__);
spi_release_bus(slave);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9215
-gerrit
commit 227a231c73da9fcabb089cf280051732dec116f0
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 29 13:04:06 2014 -0700
chromeec: Fix logging of EC wake events
The EC behavior for reading events from the ACPI interface was broken
with this commit:
d899fda lpc: ACPI query-next-event drops masked events
https://chromium-review.googlesource.com/194935
This is causing no EC wake events to be logged. To make sure they are
logged once again set the wake mask before querying for events.
Also remove the check for port80 event logging since this is no longer
used as we now store the port80 code in CMOS and this is unnecessary
commands to do for the resume path.
BUG=chrome-os-partner:32462
BRANCH=samus,auron
TEST=build and boot on samus, check for EC wake events for keyboard
and lid in the event log.
Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7
Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220373
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/ec/google/chromeec/ec.c | 33 ++++++---------------------------
1 file changed, 6 insertions(+), 27 deletions(-)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index a329b5d..83c22d3 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -379,43 +379,22 @@ u32 google_chromeec_get_wake_mask(void)
EC_CMD_HOST_EVENT_GET_WAKE_MASK);
}
-#if CONFIG_ELOG
-/* Find the last port80 code from the previous boot */
-static u16 google_chromeec_get_port80_last_boot(void)
-{
- struct ec_response_port80_last_boot rsp;
- struct chromeec_command cmd = {
- .cmd_code = EC_CMD_PORT80_LAST_BOOT,
- .cmd_data_out = &rsp,
- .cmd_size_out = sizeof(rsp),
- };
-
- /* Get last port80 code */
- if (google_chromeec_command(&cmd) == 0)
- return rsp.code;
-
- return 0;
-}
-#endif
-
void google_chromeec_log_events(u32 mask)
{
#if CONFIG_ELOG
u8 event;
- u16 code;
-
- /* Find the last port80 code */
- code = google_chromeec_get_port80_last_boot();
+ u32 wake_mask;
- /* Log the last post code only if it is abornmal */
- if (code > 0 && code != POST_OS_BOOT && code != POST_OS_RESUME)
- printk(BIOS_DEBUG, "Chrome EC: Last POST code was 0x%02x\n",
- code);
+ /* Set wake mask so events will be read from ACPI interface */
+ wake_mask = google_chromeec_get_wake_mask();
+ google_chromeec_set_wake_mask(mask);
while ((event = google_chromeec_get_event()) != 0) {
if (EC_HOST_EVENT_MASK(event) & mask)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
}
+
+ google_chromeec_set_wake_mask(wake_mask);
#endif
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9213
-gerrit
commit be191b9d78820eaa91c11f1abc441e99213d8c21
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 29 08:38:04 2014 -0700
broadwell: Add event log entry for GPIO27
Add event log entry if GPIO27 is used to wake the system.
This GPIO is treated separately from other GPE and it is
one of the only events that can wake from Deep Sx.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=samus: suspend/resume and wake from keypress, check for
GPIO27 event in event log.
Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95
Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220323
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/elog.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c
index bb7e7ba..30f64e0 100644
--- a/src/soc/intel/broadwell/elog.c
+++ b/src/soc/intel/broadwell/elog.c
@@ -63,6 +63,10 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
+ /* GPIO27 */
+ if (ps->gpe0_sts[GPE_STD] & GP27_STS)
+ elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27);
+
/* Log GPIO events in set 1-3 */
pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);