Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9229
-gerrit
commit 5d20769e7b10a15085cd84189ddf6fc480e31af6
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Oct 29 11:18:11 2014 -0700
vboot: add vbnv flash driver
this adds a driver for vboot to read and write nvdata in spi flash.
it's assumed that flash contents are erased to 1-bits and write
operations can only change 1-bits to 0-bits.
when all nvram space is used, the driver will erase the whole block
and start the next write from the beginning.
BUG=chrome-os-partner:32774
BRANCH=ToT
TEST=Built for cosmos.
Change-Id: I40858f847151aa0770e1101e905476d270550f60
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 09713828b7b0cabd13a08de3f34e32bc4dbef4a4
Original-Change-Id: Ia9049f342b21fa4c289cb7b9254ab89ec1ef1699
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226525
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/vbnv_flash.c | 161 ++++++++++++++++++++++++++++
1 file changed, 161 insertions(+)
diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c
index 1271777..cf7c002 100644
--- a/src/vendorcode/google/chromeos/vbnv_flash.c
+++ b/src/vendorcode/google/chromeos/vbnv_flash.c
@@ -17,12 +17,173 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <2api.h>
+#include <cbfs.h>
+#include <cbfs_core.h>
+#include <console/console.h>
+#include <spi_flash.h>
+#include <string.h>
+#include <vboot_nvstorage.h>
#include "chromeos.h"
+#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
+#define BLOB_SIZE VBNV_BLOCK_SIZE
+#elif IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#define BLOB_SIZE VB2_NVDATA_SIZE
+#else
+#error unable to determine BLOB_SIZE
+#endif
+
+/* FMAP descriptor of the NVRAM area */
+static struct vboot_region nvram_region;
+
+/* offset of the current nvdata in nvram */
+static int blob_offset = -1;
+
+/* cache of the current nvdata */
+static uint8_t cache[BLOB_SIZE];
+
+/* spi_flash struct used when saving data */
+static struct spi_flash *spi_flash = NULL;
+
+/*
+ * This code assumes that flash is erased to 1-bits, and write operations can
+ * only change 1-bits to 0-bits. So if the new contents only change 1-bits to
+ * 0-bits, we can reuse the current blob.
+ */
+static inline uint8_t erase_value(void)
+{
+ return 0xff;
+}
+
+static inline int can_overwrite(uint8_t current, uint8_t new)
+{
+ return (current & new) == new;
+}
+
+static inline int is_initialized(void)
+{
+ return blob_offset >= 0;
+}
+
+static int init_vbnv(void)
+{
+ uint8_t buf[BLOB_SIZE];
+ uint8_t empty_blob[BLOB_SIZE];
+ int offset;
+ int i;
+
+ vboot_locate_region("RW_NVRAM", &nvram_region);
+ if (nvram_region.size < BLOB_SIZE) {
+ printk(BIOS_ERR, "%s: failed to locate NVRAM\n", __func__);
+ return 1;
+ }
+
+ /* Prepare an empty blob to compare against. */
+ for (i = 0; i < BLOB_SIZE; i++)
+ empty_blob[i] = erase_value();
+
+ /*
+ * after the loop, offset is supposed to point the blob right before the
+ * first empty blob, the last blob in the nvram if there is no empty
+ * blob, or 0 if the nvram has never been used.
+ */
+ for (i = 0, offset = 0; i <= nvram_region.size - BLOB_SIZE;
+ i += BLOB_SIZE) {
+ if (vboot_get_region(i, BLOB_SIZE, buf) == NULL) {
+ printk(BIOS_ERR, "failed to read nvdata\n");
+ return 1;
+ }
+ if (!memcmp(buf, empty_blob, BLOB_SIZE))
+ break;
+ offset = i;
+ }
+
+ /* reread the nvdata and write it to the cache */
+ if (vboot_get_region(offset, BLOB_SIZE, cache) == NULL) {
+ printk(BIOS_ERR, "failed to read nvdata\n");
+ return 1;
+ }
+
+ blob_offset = offset;
+
+ return 0;
+}
+
+static int vbnv_flash_probe(void)
+{
+ if (!spi_flash) {
+ spi_flash = spi_flash_probe(CONFIG_BOOT_MEDIA_SPI_BUS, 0);
+ if (!spi_flash) {
+ printk(BIOS_ERR, "failed to probe spi flash\n");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int erase_nvram(void)
+{
+ if (vbnv_flash_probe())
+ return 1;
+
+ if (spi_flash->erase(spi_flash, nvram_region.offset_addr,
+ nvram_region.size)) {
+ printk(BIOS_ERR, "failed to erase nvram\n");
+ return 1;
+ }
+
+ printk(BIOS_INFO, "nvram is cleared\n");
+ return 0;
+}
+
void read_vbnv(uint8_t *vbnv_copy)
{
+ if (!is_initialized())
+ if (init_vbnv())
+ return; /* error */
+ memcpy(vbnv_copy, cache, BLOB_SIZE);
}
void save_vbnv(const uint8_t *vbnv_copy)
{
+ int new_offset = blob_offset;
+ int i;
+
+ if (!is_initialized())
+ if (init_vbnv())
+ return; /* error */
+
+ /* Bail out if there have been no changes. */
+ if (!memcmp(vbnv_copy, cache, BLOB_SIZE))
+ return;
+
+ /* See if we can overwrite the current blob with the new one */
+ for (i = 0; i < BLOB_SIZE; i++) {
+ if (!can_overwrite(cache[i], vbnv_copy[i])) {
+ /* unable to overwrite. need to use the next blob */
+ new_offset += BLOB_SIZE;
+ if (new_offset > nvram_region.size - BLOB_SIZE) {
+ if (erase_nvram())
+ return; /* error */
+ new_offset = 0;
+ }
+ break;
+ }
+ }
+
+ if (vbnv_flash_probe())
+ return; /* error */
+
+ if (spi_flash->write(spi_flash, new_offset,
+ BLOB_SIZE, vbnv_copy) != BLOB_SIZE) {
+ printk(BIOS_ERR, "failed to write nvdata\n");
+ return; /* error */
+ }
+
+ /* write was successful. safely move pointer forward */
+ blob_offset = new_offset;
+ memcpy(cache, vbnv_copy, BLOB_SIZE);
+
+ return;
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9227
-gerrit
commit 3a7162a60e609755afbe23ff4389227b54a2cbd2
Author: Ryan Lin <ryan.lin(a)intel.com>
Date: Mon Oct 13 14:22:38 2014 -0700
coreboot: force 4-byte alignment for init structure with GCC 4.9
Force 4-byte alignment for .bs_init section to ensure that no padding
data is added to init structures.
BUG=chromium:416651
BRANCH=none
TEST=build firmware with GCC 4.9 and test on Auron and Rambi.
Change-Id: Ib81ffa5d71256007106f6e5c773da377f151f174
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: c3fc03bc2e3c7745f261f3b3fbffef6d49617f9c
Original-Change-Id: I3f94cd419b5951fdc6e5749576c4df2cc44f8a24
Original-Signed-off-by: Ryan Lin <ryan.lin(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223116
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/include/bootstate.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 8b5e4be..490acd8 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -185,7 +185,8 @@ struct boot_state_init_entry {
struct boot_state_callback bscb;
};
-#define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init")))
+#define BOOT_STATE_INIT_ATTR \
+ __attribute__ ((used, aligned(4), section(".bs_init")))
#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \
static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9222
-gerrit
commit bd7604841b4f7eedd733ede19d5358dbc03e6095
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Sep 23 20:53:20 2014 -0700
arm: Prevent compilation of old, experimental SMP support
The ARM SMP feature was added a long time ago and has never really been
used by anyone since. We are still always compiling cpu_info() even
though we don't use it, and it makes some dangerous assumptions about
stack alignment that are not guaranteed anywhere.
I'm planning to change the way the stack boundaries are defined. Rather
than trying to work that into this unsafe, unused and hard to test
feature, I think we should just seal it off with police tape and make
sure that if anyone ever tries to use it again (which currently seems
unlikely), they get forced to do their due diligence on making sure it
works as intended.
BUG=None
TEST=Compiled Veyron_Pinky.
Change-Id: Id25545cab88f29200c7672ef02c7804f0ac26399
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 5b517fc46b030a6e50ef2f5e4d4a449b98ce16c6
Original-Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219680
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/arch/arm/Makefile.inc | 2 +-
src/arch/arm/cpu.c | 5 +++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 25f764c..e739d0b 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -117,7 +117,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y)
ramstage-y += stages.c
ramstage-y += div0.c
-ramstage-y += cpu.c
+ramstage-$(CONFIG_COOP_MULTITASKING) += cpu.c
ramstage-y += eabi_compat.c
ramstage-y += boot.c
ramstage-y += tables.c
diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c
index f90c759..e02fed3 100644
--- a/src/arch/arm/cpu.c
+++ b/src/arch/arm/cpu.c
@@ -34,6 +34,11 @@
*/
struct cpu_info *cpu_info(void)
{
+#error "This is BROKEN! ARM stacks are currently not guaranteed to be " \
+ "STACK_SIZE-aligned in any way. If you ever plan to revive this " \
+ "feature, make sure you add the proper assertions " \
+ "(and maybe consider revising the whole thing to work closer to what " \
+ "arm64 is doing now)."
uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),
CONFIG_STACK_SIZE);
addr -= sizeof(struct cpu_info);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9221
-gerrit
commit bd4ed971baf35e87c326968967279e1788b8bb1f
Author: Ryan Lin <ryan.lin(a)intel.com>
Date: Wed Oct 1 15:53:39 2014 -0700
Broadwell: Reg_Script: add END tag to array "smbus_init_script"
Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script.
BUG=chromium:416651
TEST=test on Auron.
Change-Id: Ieeaf6c705aa673acc9bb2635e103c4148bc8742f
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 172c5fc259a2f6d09daccb1fe53fe0aa7c5601e1
Original-Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e
Original-Signed-off-by: Ryan Lin <ryan.lin(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220934
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
---
src/soc/intel/broadwell/romstage/smbus.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
index 2bc1492..8b3cde3 100644
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ b/src/soc/intel/broadwell/romstage/smbus.c
@@ -39,6 +39,8 @@ static const struct reg_script smbus_init_script[] = {
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
/* Clear errors */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
+ /* Indicate the end of this array by REG_SCRIPT_END */
+ REG_SCRIPT_END,
};
void enable_smbus(void)