coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

Patch set updated for coreboot: 7601d82 Broadwell: Synchronization with FRC.
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9208 -gerrit commit 7601d82219fc361e70d2e567bf3287d368ef0e97 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Wed Sep 24 01:18:26 2014 +0800 Broadwell: Synchronization with FRC. Configure IOSF Port and Grant Count. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreoot image and run on Samus to confirm the setting Original-is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 --- src/soc/intel/broadwell/pcie.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f63f6d5..de23f3e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -99,6 +99,27 @@ static void root_port_config_update_gbe_port(void) } } +static void pcie_iosf_port_grant_count(device_t dev) +{ + u8 update_val; + u32 rpcd = (pci_read_config32(dev, 0xfc) > 14) & 0x3; + + switch (rpcd) { + case 1: + case 3: + update_val = 0x02; + break; + case 2: + update_val = 0x22; + break; + default: + update_val = 0x00; + break; + } + + RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val; +} + static void root_port_init_config(device_t dev) { int rp; @@ -108,7 +129,10 @@ static void root_port_init_config(device_t dev) rpc.new_rpfn = rpc.orig_rpfn; rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; - pcie_update_cfg8(dev, 0xf5, 0xa, 0x5); + /* RP0 f5[3:0] = 0101b*/ + pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + + pcie_iosf_port_grant_count(dev); rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port();

1 0

Patch set updated for coreboot: 790f7d6 Broadwell: Synchronization with FRC for power management.
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9211 -gerrit commit 790f7d6d4161c5732c6735ce8f38add8adc7ac19 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 03:14:57 2014 +0800 Broadwell: Synchronization with FRC for power management. Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build a image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/broadwell/broadwell/iobp.h | 1 + src/soc/intel/broadwell/broadwell/rcba.h | 2 ++ src/soc/intel/broadwell/iobp.c | 27 +++++++++++++++++++++++++++ src/soc/intel/broadwell/pcie.c | 11 +++++++++++ 4 files changed, 41 insertions(+) diff --git a/src/soc/intel/broadwell/broadwell/iobp.h b/src/soc/intel/broadwell/broadwell/iobp.h index 48f7673..9f17692 100644 --- a/src/soc/intel/broadwell/broadwell/iobp.h +++ b/src/soc/intel/broadwell/broadwell/iobp.h @@ -23,5 +23,6 @@ u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); #endif diff --git a/src/soc/intel/broadwell/broadwell/rcba.h b/src/soc/intel/broadwell/broadwell/rcba.h index 0d27ae3..c550c2d 100644 --- a/src/soc/intel/broadwell/broadwell/rcba.h +++ b/src/soc/intel/broadwell/broadwell/rcba.h @@ -76,6 +76,8 @@ #define IOBPS_WRITE 0x0700 #define IOBPU 0x233a #define IOBPU_MAGIC 0xf000 +#define IOBP_PCICFG_READ 0x0400 +#define IOBP_PCICFG_WRITE 0x0500 #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index 2bdd131..a0b850e 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -123,3 +123,30 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } + +void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) +{ + if (!data || !resp) + return; + + *resp = -1; + if (!iobp_poll()) + return; + + /* RCBA2330[31:0] = Address */ + RCBA32(IOBPIRI) = addr; + /* RCBA2338[15:8] = opcode */ + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; + /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ + RCBA16(IOBPU) = IOBPU_MAGIC | route_id; + + RCBA32(IOBPD) = *data; + /* Set RCBA2338[0] to trigger IOBP transaction*/ + RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; + + if (!iobp_poll()) + return; + + *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; + *data = RCBA32(IOBPD); +} diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index ccf089f..9491654 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -123,6 +123,8 @@ static void pcie_iosf_port_grant_count(device_t dev) static void root_port_init_config(device_t dev) { int rp; + u32 data; + u8 resp, id; if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); @@ -170,6 +172,15 @@ static void root_port_init_config(device_t dev) } pcie_update_cfg(dev, 0x418, 0, 0x02000430); + + /* set RP0 PCICFG E2h[5:4] = 11b befor configuring ASPM */ + if (root_port_is_first(dev)) { + id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp); + data |= (0x30 << 16); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp); + } + /* Cache pci device. */ rpc.ports[rp - 1] = dev; }

1 0

Patch set updated for coreboot: 52046d3 Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF.
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9210 -gerrit commit 52046d392e79ec965961842864b5164ad22a953a Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 02:48:16 2014 +0800 Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF. OBFF: Disable it by clear bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommeded setting. BUG=None TEST=Build a image and check the setting are applied correctly on Samub. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/broadwell/pcie.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 22eaab9..ccf089f 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -523,8 +523,8 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); } - /* Enable LTR in Root Port. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); + /* Enable LTR in Root Port. Disbale OBFF. */ + pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); @@ -550,6 +550,11 @@ static void pch_pcie_early(struct device *dev) /* Set Extended Capability to offset 200h and Advanced Error Report. */ pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), + (1 << 20) | (3 << 6)); + /* Enable Relaxed Order from Root Port. */ + pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23)); + if (rp == 1 || rp == 5 || rp == 6) pcie_update_cfg8(dev, 0xf7, ~0xc, 0);

1 0

Patch merged into coreboot/master: 86b0c8b chromeos: Add WiFi calibration CBMEM entry pointer to coreboot table
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 86b0c8b48038f537407c1b8ed9015a54d0159403 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 23 15:15:45 2014 -0700 chromeos: Add WiFi calibration CBMEM entry pointer to coreboot table This patch adds plumbing necessary to ensure that the CBMEM WiFi calibration blobs entry, if present, is referenced if the coreboot table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none - the entry is not yet in the CBMEM Change-Id: I072f2368b628440b6fe84f310eebc1ab945f809e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d0330280369753a6520196425e6dfc7d7bd226a3 Original-Change-Id: I04d52934ad1c5466d0d124b32df5ab17c0f59686 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225270 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9232 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9232 for details. -gerrit

1 0

Patch merged into coreboot/master: d775dda broadwell: Clear pending GPE events before entering sleep state
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit d775ddab99f1b3c45e624e6e0d5f59ae728c3a16 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Oct 25 01:49:32 2014 -0700 broadwell: Clear pending GPE events before entering sleep state In the case of an EC wake event that is pending but not cleared it is possible for the EC wake pin (i.e. GPIO27) to be asserted after the kernel triggers the sleep SMI but before the system goes to sleep. If this happens then the GPE will be reported as a wake source when the system wakes up again. BUG=chrome-os-partner:33218 BRANCH=samus,auron TEST=build and boot on samus, use the keyboard to enter suspend with suspend_stress_test and ensure that only the RTC is listed as a wake source upon resume. Change-Id: Id900132bb81e4cf50885a652ed00a142d951ea4d Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 50396ab6a3a3efb3b3dea4f1c2a8f8804fed943e Original-Change-Id: I319dc22e21126a3086415f8f8b2b35eaec66fd50 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225540 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9231 for details. -gerrit

1 0

Patch merged into coreboot/master: e237f5a Baytrail: Change PCIe root disable algorithm
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit e237f5ac95edb227106a888738771755194c82cd Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 12 02:10:53 2014 +0800 Baytrail: Change PCIe root disable algorithm Disable Root Port0 only when there is no PCIe device present on any root port. BUG=None TEST=Boot Rambi with PCIe installed/non-installed on RP0 to confirm the RP0 is correctly enabled/disabled. However, I still need someone to help check if RP0(no device) is still enabled if there is device on other RPs since since I have no devices having slots from RP1/2/3. Change-Id: Iae552975250ed6f309c423b847621b8994172891 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7 Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217791 Original-Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9219 for details. -gerrit

1 0

Patch merged into coreboot/master: 6ecaf65 Baytrail: add _PRT to each PCIe root port device
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 6ecaf65bffde68d60a53aeeeb62db43c4fa6c5c9 Author: Ted Kuo <tedkuo(a)ami.com.tw> Date: Tue Sep 16 15:31:21 2014 +0800 Baytrail: add _PRT to each PCIe root port device Report PCI routing table of all PCIe root ports for legacy interrupt. Some PCIe devices using legacy interrupt can't work if PCI routing table isn't defined. It's necessary and defined in BWG Chapter 28.1.3. BUG=chrome-os-partner:31943 TEST=compiled and tested BRANCH=NONE Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw> Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45 Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b Original-Reviewed-on: https://chromium-review.googlesource.com/218422 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Ted Kuo <tedkuo(a)ami.com.tw> Original-Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> Reviewed-on: http://review.coreboot.org/9201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9201 for details. -gerrit

1 0

Patch merged into coreboot/master: ffc2a3b Samus: fix unused GPIO pin
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit ffc2a3b59b96961a174cdc02f920431ccdc4e302 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Wed Sep 10 06:00:15 2014 +0800 Samus: fix unused GPIO pin Mark GPIO42 as unused according to Samus schematics BUG=None TEST=Make the chnage; Pass the build process; Need someone having the board perform the verification. Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900 Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217344 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9199 for details. -gerrit

1 0

Patch merged into coreboot/master: 70e189e ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASE
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 70e189e9e8ec9c47dc76dcd92e12c5d3124975b4 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 9 10:52:35 2014 -0700 ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASE For now storm bootblock runs with DRAM fully initialized, this patch puts the early console between bootblock and rom phase. BUG=chrome-os-partner:31734 TEST=verified that preram_cbmem_console is set: $ grep preram_cbmem_console cbfs/fallback/bootblock.map 40618000 A preram_cbmem_console Change-Id: I2d63f5fde0d3794062068289c648d8bcda11a9a3 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 6bdadad3787d6a4a2d4828b0f300455fedca2b8d Original-Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9198 for details. -gerrit

1 0

Patch merged into coreboot/master: 51bdc47 smbios: add a family id in smbios type1 family
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 51bdc4781635b99d89e6b7a414a2172be8cb690c Author: Kane Chen <kane.chen(a)intel.com> Date: Mon Sep 8 18:40:30 2014 -0700 smbios: add a family id in smbios type1 family mosys will use this field to identify system BRANCH=none BUG=chromium:359155 TEST=build ok, use dmidecode to check whether data is written correctly Change-Id: I461215c012b6ad712b3f813a3928e90a23bf54f1 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 7adbdab761cd7b4bda0a43e7b1c4070de26f150a Original-Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217400 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/9230 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9230 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2015