coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 2b59a83 vboot: add vbnv flash driver
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 2b59a838b4b6dd68994ae5883d4f1692c2217b16 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Oct 29 11:18:11 2014 -0700 vboot: add vbnv flash driver this adds a driver for vboot to read and write nvdata in spi flash. it's assumed that flash contents are erased to 1-bits and write operations can only change 1-bits to 0-bits. when all nvram space is used, the driver will erase the whole block and start the next write from the beginning. BUG=chrome-os-partner:32774 BRANCH=ToT TEST=Built for cosmos. Change-Id: I40858f847151aa0770e1101e905476d270550f60 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 09713828b7b0cabd13a08de3f34e32bc4dbef4a4 Original-Change-Id: Ia9049f342b21fa4c289cb7b9254ab89ec1ef1699 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226525 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9229 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/9229 for details. -gerrit

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Patch merged into coreboot/master: 2af67c9 broadwell: Add reporting of broadwell MCH revision
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 2af67c9878bb84e10a6f526cfdeb2aacb76e119c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 14 08:37:18 2014 -0700 broadwell: Add reporting of broadwell MCH revision Since the E0 and F0 stepping parts have the same CPUID it is necessary to use the MCH PCI device revision to determine what the actual stepping is. Add this decode table so the early output gives proper identification of the installed CPU type. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus with E0 and F0 parts Change-Id: Idce1e289cd958c77febc87395f27570247512a87 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3 Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223158 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9228 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9228 for details. -gerrit

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Patch merged into coreboot/master: 4b2adb1 broadwell: Change CPUID 306D4 to report "E0 or F0"
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 4b2adb13f1432b0f05a94f1934071d2ec9dc297e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 13 13:14:22 2014 -0700 broadwell: Change CPUID 306D4 to report "E0 or F0" The F0 stepping has the same CPUID as E0 stepping so report it as either stepping to avoid confusion. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I99a83855b4393d736724836b709702417483b5d2 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 55ed3bc880c31c0ca5c8a21c335722af05eb57f7 Original-Change-Id: Ia4955f346ceb9be92e06ecea5b7a8fe2db84cabc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223097 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9226 for details. -gerrit

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Patch merged into coreboot/master: 32dfd06 broadwell: me: Fix typo and add missing phase state
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 32dfd0625587015891d738794503b645ba9455ea Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 9 16:14:39 2014 -0700 broadwell: me: Fix typo and add missing phase state Fix the typo of sate to state and add uKernel phase to just output the current state byte. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5f341ee6c58487aeb927cab0641742cb4071a6b7 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: de6149508c50d0770fedfbe352e9149abea87b4c Original-Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222677 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9225 for details. -gerrit

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Patch merged into coreboot/master: afd6298 pinky: Enable EC_SOFTWARE_SYNC
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit afd6298c957651344686dacc9e6cb2cb1fd55bcd Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 2 11:39:43 2014 -0700 pinky: Enable EC_SOFTWARE_SYNC CQ-DEPEND=CL:218766 BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: Ib3eed77553433e9f8c70af8b148729e628c95747 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 56b3e8c02a4e45653a5369ce47dcbce0c18f7194 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Icbee95350949bd9bfa4490a8a4b6bbf09beb4170 Original-Reviewed-on: https://chromium-review.googlesource.com/221019 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9224 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9224 for details. -gerrit

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Patch merged into coreboot/master: c56d5c5 mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GB
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit c56d5c5aac03a3bba5b4d2b5d219e66a448972f9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:48:51 2015 -0500 mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GB Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/9139 for details. -gerrit

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Patch merged into coreboot/master: 6e523a6 northbridge/amd/amdfam10: Generate SMBIOS tables for RAM
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 6e523a682f0284ec1cb810c6b4b4fb61702d651a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:58:45 2015 -0500 northbridge/amd/amdfam10: Generate SMBIOS tables for RAM TEST: Booted ASUS KFSN4-DRE and verified SMBIOS contents via dmidecode utility. Change-Id: Id656f2f6cf5a4ecafa03e150ad91f69107a4fe88 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/9140 for details. -gerrit

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New patch to review for coreboot: 829ca8a chromeos: Add WiFi calibration CBMEM entry pointer to coreboot table
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9232 -gerrit commit 829ca8a8924d29f83589f5bf97e2abb39f95869e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 23 15:15:45 2014 -0700 chromeos: Add WiFi calibration CBMEM entry pointer to coreboot table This patch adds plumbing necessary to ensure that the CBMEM WiFi calibration blobs entry, if present, is referenced if the coreboot table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none - the entry is not yet in the CBMEM Change-Id: I072f2368b628440b6fe84f310eebc1ab945f809e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d0330280369753a6520196425e6dfc7d7bd226a3 Original-Change-Id: I04d52934ad1c5466d0d124b32df5ab17c0f59686 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225270 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 1 + src/include/cbmem.h | 2 ++ src/lib/coreboot_table.c | 1 + 3 files changed, 4 insertions(+) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index fc44a3c..46c1df5 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -239,6 +239,7 @@ struct lb_range { #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 +#define LB_TAG_WIFI_CALIBRATION 0x0027 struct lb_cbmem_ref { uint32_t tag; uint32_t size; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 8ba0881..8378a17 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -73,6 +73,7 @@ #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_RAM_OOPS 0x05430095 #define CBMEM_ID_MEMINFO 0x494D454D +#define CBMEM_ID_WIFI_CALIBRATION 0x57494649 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_SPINTABLE 0x59175917 #define CBMEM_ID_NONE 0x00000000 @@ -121,6 +122,7 @@ struct cbmem_id_to_name { { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ + { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, \ { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, struct cbmem_entry; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4126e82..d6d84cd 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -239,6 +239,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}, {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, + {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION} }; int i;

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New patch to review for coreboot: 9385a44 broadwell: Clear pending GPE events before entering sleep state
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9231 -gerrit commit 9385a447629f73f261bd08e43779a7bfc96b8799 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Oct 25 01:49:32 2014 -0700 broadwell: Clear pending GPE events before entering sleep state In the case of an EC wake event that is pending but not cleared it is possible for the EC wake pin (i.e. GPIO27) to be asserted after the kernel triggers the sleep SMI but before the system goes to sleep. If this happens then the GPE will be reported as a wake source when the system wakes up again. BUG=chrome-os-partner:33218 BRANCH=samus,auron TEST=build and boot on samus, use the keyboard to enter suspend with suspend_stress_test and ensure that only the RTC is listed as a wake source upon resume. Change-Id: Id900132bb81e4cf50885a652ed00a142d951ea4d Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 50396ab6a3a3efb3b3dea4f1c2a8f8804fed943e Original-Change-Id: I319dc22e21126a3086415f8f8b2b35eaec66fd50 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225540 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/smihandler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 064a9dc..e1f7e5b 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -145,6 +145,9 @@ static void southbridge_smi_sleep(void) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); #endif + /* Clear pending GPE events */ + clear_gpe_status(); + /* Next, do the deed. */

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New patch to review for coreboot: b26e00b smbios: add a family id in smbios type1 family
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9230 -gerrit commit b26e00b6ee794af469e1882d3bffac47be2c724e Author: Kane Chen <kane.chen(a)intel.com> Date: Mon Sep 8 18:40:30 2014 -0700 smbios: add a family id in smbios type1 family mosys will use this field to identify system BRANCH=none BUG=chromium:359155 TEST=build ok, use dmidecode to check whether data is written correctly Change-Id: I461215c012b6ad712b3f813a3928e90a23bf54f1 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 7adbdab761cd7b4bda0a43e7b1c4070de26f150a Original-Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217400 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/arch/x86/boot/smbios.c | 10 ++++++++++ src/include/smbios.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 4c3490d..8b4fd68 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -302,6 +302,13 @@ void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid) /* leave all zero */ } +#ifdef CONFIG_MAINBOARD_FAMILY +const char *smbios_mainboard_family(void) +{ + return CONFIG_MAINBOARD_FAMILY; +} +#endif /* CONFIG_MAINBOARD_FAMILY */ + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -334,6 +341,9 @@ static int smbios_write_type2(unsigned long *current, int handle) t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); +#ifdef CONFIG_MAINBOARD_FAMILY + t->family = smbios_add_string(t->eos, smbios_mainboard_family()); +#endif len = t->length + smbios_string_table_len(t->eos); *current += len; return len; diff --git a/src/include/smbios.h b/src/include/smbios.h index 7d1c333..c6132ec 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -40,6 +40,9 @@ const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); u8 smbios_mainboard_enclosure_type(void); +#ifdef CONFIG_MAINBOARD_FAMILY +const char *smbios_mainboard_family(void); +#endif #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8)

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coreboot-gerrit April 2015