coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 782d876 chromeec: Add battery status event and re-enable _BIX
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9212 -gerrit commit 782d87694f1883735b4e6385986f6c665dc1e104 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:32:19 2014 -0700 chromeec: Add battery status event and re-enable _BIX Add a new host event to send a notify(0x80) to the battery when the EC indicates that battery status has changed. The kernel has fixed the bug with _BIX method so it can be enabled now. BUG=chrome-os-partner:32196 BRANCH=samus TEST=build and boot on samus Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2 Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220320 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/acpi/battery.asl | 4 +--- src/ec/google/chromeec/acpi/ec.asl | 7 +++++++ src/ec/google/chromeec/ec_commands.h | 15 ++++++++++++++- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 2ef1199..5591b33 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -126,9 +126,7 @@ Device (BAT0) Return (PBIF) } - // Extended Battery info method is disabled for now due to - // a bug in the Linux kernel: http://crosbug.com/28747 - Method (XBIX, 0, Serialized) + Method (_BIX, 0, Serialized) { // Last Full Charge Capacity Store (BTDF, Index (PBIX, 3)) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 734d223..7cd8f75 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -312,6 +312,13 @@ Device (EC0) } #endif + // Battery Status + Method (_Q17, 0, NotSerialized) + { + Store ("EC: BATTERY STATUS", Debug) + Notify (BAT0, 0x80) + } + /* * Dynamic Platform Thermal Framework support */ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 0687641..bd94281 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -275,6 +275,9 @@ enum host_event_code { /* PD MCU triggering host event */ EC_HOST_EVENT_PD_MCU = 22, + /* Battery Status flags have changed */ + EC_HOST_EVENT_BATTERY_STATUS = 23, + /* * The high bit of the event mask is not used as a host event code. If * it reads back as set, then the entire event mask should be @@ -1032,6 +1035,13 @@ struct lightbar_params_v1 { struct rgb_s color[8]; /* 0-3 are Google colors */ } __packed; +/* Lightbyte program. */ +#define LB_PROG_LEN 192 +struct lb_program { + uint8_t size; + uint8_t data[LB_PROG_LEN]; +}; + struct ec_params_lightbar { uint8_t cmd; /* Command (see enum lightbar_command) */ union { @@ -1058,6 +1068,7 @@ struct ec_params_lightbar { struct lightbar_params_v0 set_params_v0; struct lightbar_params_v1 set_params_v1; + struct lb_program set_program; }; } __packed; @@ -1090,7 +1101,8 @@ struct ec_response_lightbar { struct { /* no return params */ } off, on, init, set_brightness, seq, reg, set_rgb, - demo, set_params_v0, set_params_v1; + demo, set_params_v0, set_params_v1, + set_program; }; } __packed; @@ -1114,6 +1126,7 @@ enum lightbar_command { LIGHTBAR_CMD_GET_DEMO = 15, LIGHTBAR_CMD_GET_PARAMS_V1 = 16, LIGHTBAR_CMD_SET_PARAMS_V1 = 17, + LIGHTBAR_CMD_SET_PROGRAM = 18, LIGHTBAR_NUM_CMDS };

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New patch to review for coreboot: ff44a38 Broadwell: Synchronization with FRC for power management.
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9211 -gerrit commit ff44a38602965eb405685a4ad8f9ba17940ff520 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 03:14:57 2014 +0800 Broadwell: Synchronization with FRC for power management. Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build a image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/broadwell/broadwell/iobp.h | 1 + src/soc/intel/broadwell/broadwell/rcba.h | 2 ++ src/soc/intel/broadwell/iobp.c | 27 +++++++++++++++++++++++++++ src/soc/intel/broadwell/pcie.c | 11 +++++++++++ 4 files changed, 41 insertions(+) diff --git a/src/soc/intel/broadwell/broadwell/iobp.h b/src/soc/intel/broadwell/broadwell/iobp.h index 48f7673..9f17692 100644 --- a/src/soc/intel/broadwell/broadwell/iobp.h +++ b/src/soc/intel/broadwell/broadwell/iobp.h @@ -23,5 +23,6 @@ u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); #endif diff --git a/src/soc/intel/broadwell/broadwell/rcba.h b/src/soc/intel/broadwell/broadwell/rcba.h index 0d27ae3..c550c2d 100644 --- a/src/soc/intel/broadwell/broadwell/rcba.h +++ b/src/soc/intel/broadwell/broadwell/rcba.h @@ -76,6 +76,8 @@ #define IOBPS_WRITE 0x0700 #define IOBPU 0x233a #define IOBPU_MAGIC 0xf000 +#define IOBP_PCICFG_READ 0x0400 +#define IOBP_PCICFG_WRITE 0x0500 #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index 2bdd131..a0b850e 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -123,3 +123,30 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } + +void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) +{ + if (!data || !resp) + return; + + *resp = -1; + if (!iobp_poll()) + return; + + /* RCBA2330[31:0] = Address */ + RCBA32(IOBPIRI) = addr; + /* RCBA2338[15:8] = opcode */ + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code; + /* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */ + RCBA16(IOBPU) = IOBPU_MAGIC | route_id; + + RCBA32(IOBPD) = *data; + /* Set RCBA2338[0] to trigger IOBP transaction*/ + RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1; + + if (!iobp_poll()) + return; + + *resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1; + *data = RCBA32(IOBPD); +} diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index ccf089f..9491654 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -123,6 +123,8 @@ static void pcie_iosf_port_grant_count(device_t dev) static void root_port_init_config(device_t dev) { int rp; + u32 data; + u8 resp, id; if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); @@ -170,6 +172,15 @@ static void root_port_init_config(device_t dev) } pcie_update_cfg(dev, 0x418, 0, 0x02000430); + + /* set RP0 PCICFG E2h[5:4] = 11b befor configuring ASPM */ + if (root_port_is_first(dev)) { + id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp); + data |= (0x30 << 16); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp); + } + /* Cache pci device. */ rpc.ports[rp - 1] = dev; }

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New patch to review for coreboot: 23200a6 Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF.
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9210 -gerrit commit 23200a6c1d94097bf7437ec5ce86d37e4a191181 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 02:48:16 2014 +0800 Broadwell: Synchronization with FRC for RO, Link Arbiter, and OBFF. OBFF: Disable it by clear bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommeded setting. BUG=None TEST=Build a image and check the setting are applied correctly on Samub. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/broadwell/pcie.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 22eaab9..ccf089f 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -523,8 +523,8 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); } - /* Enable LTR in Root Port. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); + /* Enable LTR in Root Port. Disbale OBFF. */ + pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); @@ -550,6 +550,11 @@ static void pch_pcie_early(struct device *dev) /* Set Extended Capability to offset 200h and Advanced Error Report. */ pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), + (1 << 20) | (3 << 6)); + /* Enable Relaxed Order from Root Port. */ + pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23)); + if (rp == 1 || rp == 5 || rp == 6) pcie_update_cfg8(dev, 0xf7, ~0xc, 0);

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New patch to review for coreboot: 9629119 Broadwell: Revise programming flow for write-once registers
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9209 -gerrit commit 9629119daa528680c870969642de5b9061cb4d7c Author: Kenji Chen <kenji.chen(a)intel.com> Date: Thu Sep 25 21:34:42 2014 +0800 Broadwell: Revise programming flow for write-once registers Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9 Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 --- src/soc/intel/broadwell/pcie.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index de23f3e..22eaab9 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -547,16 +547,15 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg8(dev, 0xf5, 0x0f, 0); + /* Set Extended Capability to offset 200h and Advanced Error Report. */ + pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + if (rp == 1 || rp == 5 || rp == 6) pcie_update_cfg8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); - /* Set something involving advanced error reporting. */ - pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); - pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); - /* Read and write back write-once capability registers. */ pcie_update_cfg(dev, 0x34, ~0, 0); pcie_update_cfg(dev, 0x40, ~0, 0);

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New patch to review for coreboot: 6ea136e Broadwell: Synchronization with FRC.
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9208 -gerrit commit 6ea136ea860140cd2ddd486721431afb24990bac Author: Kenji Chen <kenji.chen(a)intel.com> Date: Wed Sep 24 01:18:26 2014 +0800 Broadwell: Synchronization with FRC. Configure IOSF Port and Grant Count. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreoot image and run on Samus to confirm the setting Original-is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 --- src/soc/intel/broadwell/pcie.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f63f6d5..de23f3e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -99,6 +99,27 @@ static void root_port_config_update_gbe_port(void) } } +static void pcie_iosf_port_grant_count(device_t dev) +{ + u8 update_val; + u32 rpcd = (pci_read_config32(dev, 0xfc) > 14) & 0x3; + + switch (rpcd) { + case 1: + case 3: + update_val = 0x02; + break; + case 2: + update_val = 0x22; + break; + default: + update_val = 0x00; + break; + } + + RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val; +} + static void root_port_init_config(device_t dev) { int rp; @@ -108,7 +129,10 @@ static void root_port_init_config(device_t dev) rpc.new_rpfn = rpc.orig_rpfn; rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; - pcie_update_cfg8(dev, 0xf5, 0xa, 0x5); + /* RP0 f5[3:0] = 0101b*/ + pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + + pcie_iosf_port_grant_count(dev); rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port();

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New patch to review for coreboot: 4839966 vpd: retrieve mac addresses and pass them to bootloader
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9207 -gerrit commit 4839966cfc38bd96e6debbccd7891f339ade2085 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 22 18:48:41 2014 -0700 vpd: retrieve mac addresses and pass them to bootloader Chrome OS devices firmware usually includes an area called VPD (Vital Product Data). VPD is a blob of a certain structure, in particular containing freely defined variable size fields. A field is a tuple of the field name and field contents. MAC addresses of the interfaces are stored in VPD as well. Field names are in the form of 'ethernet_macN', where N is the zero based interface number. This patch retrieves the MAC address(es) from the VPD and populates them in the coreboot table so that they become available to the bootloader. BUG=chrome-os-partner:32152, chromium:417117 TEST=with this and other patches in place the storm device tree shows up with MAC addresses properly initialized. Change-Id: I955207b3a644cde100cc4b48e51a2ab9a3cb1ba0 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 1972b9e97b57cc8503c5e4dc496706970ed2ffbe Original-Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219443 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 13 +++++++ src/lib/coreboot_table.c | 74 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index fc44a3c..0315018 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -262,6 +262,19 @@ struct lb_board_id { uint32_t board_id; }; +#define LB_TAG_MAC_ADDRS 0x0026 +struct mac_address { + uint8_t mac_addr[6]; + uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ +}; + +struct lb_macs { + uint32_t tag; + uint32_t size; + uint32_t count; + struct mac_address mac_addrs[0]; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4126e82..cd197c3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -38,6 +38,7 @@ #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <vendorcode/google/chromeos/cros_vpd.h> #endif #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> @@ -157,9 +158,79 @@ void fill_lb_gpio(struct lb_gpio *gpio, int num, } #if CONFIG_CHROMEOS +static void lb_macs(struct lb_header *header) +{ + /* + * In case there is one or more MAC addresses stored in the VPD, the + * key is "ethernet_mac{0..9}", up to 10 values. + */ + static const char mac_addr_key_base[] = "ethernet_mac0"; + char mac_addr_key[sizeof(mac_addr_key_base)]; + char mac_addr_str[13]; /* 12 symbols and the trailing zero. */ + int count; + struct lb_macs *macs = NULL; + const int index_of_index = sizeof(mac_addr_key) - 2; + + /* + * MAC addresses are stored in the VPD as strings of hex numbers, + * which need to be converted into binary for storing in the coreboot + * table. + */ + strcpy(mac_addr_key, mac_addr_key_base); + count = 0; + do { + int i; + + if (!cros_vpd_gets(mac_addr_key, mac_addr_str, + sizeof(mac_addr_str))) + break; /* No more MAC addresses in VPD */ + + if (!macs) { + macs = (struct lb_macs *)lb_new_record(header); + macs->tag = LB_TAG_MAC_ADDRS; + } + + /* MAC address in symbolic form is in mac_addr_str. */ + for (i = 0; i < sizeof(macs->mac_addrs[0].mac_addr); i++) { + int j; + uint8_t n = 0; + + for (j = 0; j < 2; j++) { + char c = mac_addr_str[i * 2 + j]; + + if (isxdigit(c)) { + if (isdigit(c)) + c -= '0'; + else + c = tolower(c) - 'a' + 10; + } else { + printk(BIOS_ERR, + "%s: non hexadecimal symbol " + "%#2.2x in the VPD field %s\n", + __func__, (uint8_t)c, + mac_addr_key); + c = 0; + } + n <<= 4; + n |= c; + } + macs->mac_addrs[count].mac_addr[i] = n; + } + count++; + mac_addr_key[index_of_index] = '0' + count; + } while (count < 10); + + if (!count) + return; /* No MAC addresses in the VPD. */ + + macs->count = count; + macs->size = sizeof(*macs) + count * sizeof(struct mac_address); +} + static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; + gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; gpios->size = sizeof(*gpios); @@ -445,6 +516,9 @@ unsigned long write_coreboot_table( /* pass along the vboot_handoff address. */ lb_vboot_handoff(head); + + /* Retrieve mac addresses from VPD, if any. */ + lb_macs(head); #endif /* Add board ID if available */

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New patch to review for coreboot: 5397d82 Samus: Synchronization with FRC to enable PCIe Relaxed Order.
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9206 -gerrit commit 5397d82f8e26a683650e9eb452710c117d43506a Author: Kenji Chen <kenji.chen(a)intel.com> Date: Sat Sep 20 01:39:20 2014 +0800 Samus: Synchronization with FRC to enable PCIe Relaxed Order. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 --- src/soc/intel/broadwell/lpc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index d7a3e82..5efcb73 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -207,6 +207,9 @@ static const struct reg_script pch_misc_init_script[] = { /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + /* Enable PCIe Releaxed Order */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE

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New patch to review for coreboot: 5e701cd samus: Ensure PD controller is in RO mode for recovery
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9205 -gerrit commit 5e701cde624f0b4927a5e19c35b227e4c1232872 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:56:04 2014 -0700 samus: Ensure PD controller is in RO mode for recovery In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 44d712e..ca43b81 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -43,7 +43,8 @@ void mainboard_romstage_entry(struct romstage_params *rp) printk(BIOS_INFO, "MLB: board version %d\n", google_chromeec_get_board_version()); - /* Ensure the EC is in the right mode for recovery */ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_pd_init(); google_chromeec_early_init(); /* Initialize GPIOs */

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New patch to review for coreboot: 859d1b7 chromeec: Add commands to check PD image type
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9204 -gerrit commit 859d1b7c3c8bde03246534c2dbaeffcba98e8a3c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:54:02 2014 -0700 chromeec: Add commands to check PD image type Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/ec.c | 55 ++++++++++++++++++++++++++++++++++++++++++++- src/ec/google/chromeec/ec.h | 6 +++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1fadeec..a329b5d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -55,6 +55,7 @@ int google_chromeec_kbbacklight(int percent) cec_cmd.cmd_data_out = &rsp_backlight; cec_cmd.cmd_size_in = sizeof(cmd_backlight); cec_cmd.cmd_size_out = sizeof(rsp_backlight); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n", rsp_backlight.percent, cec_cmd.cmd_code); @@ -87,6 +88,7 @@ static u32 google_chromeec_get_mask(u8 type) cmd.cmd_size_in = sizeof(req); cmd.cmd_data_out = &rsp; cmd.cmd_size_out = sizeof(rsp); + cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) == 0) return rsp.mask; @@ -106,6 +108,7 @@ static int google_chromeec_set_mask(u8 type, u32 mask) cmd.cmd_size_in = sizeof(req); cmd.cmd_data_out = &rsp; cmd.cmd_size_out = sizeof(rsp); + cmd.cmd_dev_index = 0; return google_chromeec_command(&cmd); } @@ -123,16 +126,18 @@ int google_chromeec_clear_events_b(u32 mask) } #ifndef __SMM__ +#ifdef __PRE_RAM__ void google_chromeec_check_ec_image(int expected_type) { struct chromeec_command cec_cmd; - struct ec_response_get_version cec_resp = {{0}}; + struct ec_response_get_version cec_resp = { { 0 } }; cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) { @@ -145,6 +150,7 @@ void google_chromeec_check_ec_image(int expected_type) cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); @@ -163,6 +169,46 @@ void google_chromeec_early_init(void) } } +void google_chromeec_check_pd_image(int expected_type) +{ + struct chromeec_command cec_cmd; + struct ec_response_get_version cec_resp = { { 0 } }; + + cec_cmd.cmd_code = EC_CMD_GET_VERSION; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_out = &cec_resp; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 1; /* PD */ + google_chromeec_command(&cec_cmd); + + if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) { + struct ec_params_reboot_ec reboot_ec; + /* Reboot the PD and make it come back in RO mode */ + reboot_ec.cmd = EC_REBOOT_COLD; + reboot_ec.flags = 0; + cec_cmd.cmd_code = EC_CMD_REBOOT_EC; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &reboot_ec; + cec_cmd.cmd_size_in = sizeof(reboot_ec); + cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 1; /* PD */ + printk(BIOS_DEBUG, "Rebooting PD to RO mode\n"); + google_chromeec_command(&cec_cmd); + udelay(1000); + } +} + +/* Check for recovery mode and ensure PD is in RO */ +void google_chromeec_early_pd_init(void) +{ + /* If in recovery ensure PD is running RO firmware. */ + if (recovery_mode_enabled()) { + google_chromeec_check_pd_image(EC_IMAGE_RO); + } +} +#endif + u16 google_chromeec_get_board_version(void) { struct chromeec_command cmd; @@ -173,6 +219,7 @@ u16 google_chromeec_get_board_version(void) cmd.cmd_size_in = 0; cmd.cmd_size_out = sizeof(board_v); cmd.cmd_data_out = &board_v; + cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) != 0) return 0; @@ -196,6 +243,7 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) cec_cmd.cmd_data_out = &rsp_vbnvcontext; cec_cmd.cmd_size_in = sizeof(cmd_vbnvcontext); cec_cmd.cmd_size_out = is_read ? sizeof(rsp_vbnvcontext) : 0; + cec_cmd.cmd_dev_index = 0; cmd_vbnvcontext.op = is_read ? EC_VBNV_CONTEXT_OP_READ : EC_VBNV_CONTEXT_OP_WRITE; @@ -281,6 +329,7 @@ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, cmd.cmd_size_in = size + write_len; cmd.cmd_data_out = r; cmd.cmd_size_out = sizeof(*r) + read_len; + cmd.cmd_dev_index = 0; rv = google_chromeec_command(&cmd); if (rv != 0) return rv; @@ -384,6 +433,7 @@ int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode) cmd.cmd_data_in = &set_mode; cmd.cmd_size_out = 0; cmd.cmd_data_out = NULL; + cmd.cmd_dev_index = 0; return google_chromeec_command(&cmd); } @@ -403,6 +453,7 @@ int google_chromeec_hello(void) cec_cmd.cmd_data_out = &rsp_hello.out_data; cec_cmd.cmd_size_in = sizeof(cmd_hello.in_data); cec_cmd.cmd_size_out = sizeof(rsp_hello.out_data); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome EC: Hello got back %x status (%x)\n", rsp_hello.out_data, cec_cmd.cmd_code); @@ -425,6 +476,7 @@ void google_chromeec_init(void) cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code) { @@ -451,6 +503,7 @@ void google_chromeec_init(void) cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index e0db8c1..cdf94da 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -36,10 +36,15 @@ int google_ec_running_ro(void); void google_chromeec_init(void); #endif +#ifdef __PRE_RAM__ /* If recovery mode is enabled and EC is not running RO firmware reboot. */ void google_chromeec_early_init(void); +void google_chromeec_early_pd_init(void); /* Reboot if EC firmware is not expected type. */ void google_chromeec_check_ec_image(int expected_type); +void google_chromeec_check_pd_image(int expected_type); +#endif + uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u16 google_chromeec_get_board_version(void); u32 google_chromeec_get_events_b(void); @@ -67,6 +72,7 @@ struct chromeec_command { uint16_t cmd_size_in; /* size of command data */ uint16_t cmd_size_out; /* expected size of command response in, * actual received size out */ + int cmd_dev_index;/* device index for passthru */ }; /*

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New patch to review for coreboot: 501142a chromeec: Add support for v3 commands on LPC
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9203 -gerrit commit 501142ae790d6e272f9d44a144377edd60bda21e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:51:07 2014 -0700 chromeec: Add support for v3 commands on LPC In order to talk to the PD controller with a passthru command coreboot needs to be able to use v3 commands. The command version is automatically detected based on the advertized flags from the EC. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot on samus EVT Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218902 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/ec_lpc.c | 169 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 167 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 5344716..ed0b76a 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -29,6 +29,30 @@ #include "ec.h" #include "ec_commands.h" +static int google_chromeec_command_version(void) +{ + u8 id1, id2, flags; + + id1 = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID); + id2 = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1); + flags = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS); + + if (id1 != 'E' || id2 != 'C') { + printk(BIOS_ERR, "Missing Chromium EC memory map.\n"); + return -1; + } + + if (flags & EC_HOST_CMD_FLAG_VERSION_3) { + return EC_HOST_CMD_FLAG_VERSION_3; + } else if (flags & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) { + return EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED; + } else { + printk(BIOS_ERR, + "Chromium EC command version unsupported\n"); + return -1; + } +} + static int google_chromeec_wait_ready(u16 port) { u8 ec_status = inb(port); @@ -51,7 +75,119 @@ static int google_chromeec_wait_ready(u16 port) return 0; } -int google_chromeec_command(struct chromeec_command *cec_command) +static int google_chromeec_command_v3(struct chromeec_command *cec_command) +{ + struct ec_host_request rq; + struct ec_host_response rs; + const u8 *d; + u8 *dout; + int csum = 0; + int i; + + if (cec_command->cmd_size_in + sizeof(rq) > EC_LPC_HOST_PACKET_SIZE) { + printk(BIOS_ERR, "EC cannot send %d bytes\n", + cec_command->cmd_size_in + sizeof(rq)); + return -1; + } + + if (cec_command->cmd_size_out > EC_LPC_HOST_PACKET_SIZE) { + printk(BIOS_ERR, "EC cannot receive %d bytes\n", + cec_command->cmd_size_out); + return -1; + } + + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC start command %d!\n", + cec_command->cmd_code); + return -1; + } + + /* Fill in request packet */ + rq.struct_version = EC_HOST_REQUEST_VERSION; + rq.checksum = 0; + rq.command = cec_command->cmd_code | + EC_CMD_PASSTHRU_OFFSET(cec_command->cmd_dev_index); + rq.command_version = cec_command->cmd_version; + rq.reserved = 0; + rq.data_len = cec_command->cmd_size_in; + + /* Copy data and start checksum */ + for (i = 0, d = (const u8 *)cec_command->cmd_data_in; + i < cec_command->cmd_size_in; i++, d++) { + outb(*d, EC_LPC_ADDR_HOST_PACKET + sizeof(rq) + i); + csum += *d; + } + + /* Finish checksum */ + for (i = 0, d = (const u8 *)&rq; i < sizeof(rq); i++, d++) + csum += *d; + + /* Write checksum field so the entire packet sums to 0 */ + rq.checksum = (u8)(-csum); + + /* Copy header */ + for (i = 0, d = (const uint8_t *)&rq; i < sizeof(rq); i++, d++) + outb(*d, EC_LPC_ADDR_HOST_PACKET + i); + + /* Start the command */ + outb(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD); + + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", + cec_command->cmd_code); + return -1; + } + + /* Check result */ + cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA); + if (cec_command->cmd_code) { + printk(BIOS_ERR, "EC returned error result code %d\n", + cec_command->cmd_code); + return -i; + } + + /* Read back response header and start checksum */ + csum = 0; + for (i = 0, dout = (u8 *)&rs; i < sizeof(rs); i++, dout++) { + *dout = inb(EC_LPC_ADDR_HOST_PACKET + i); + csum += *dout; + } + + if (rs.struct_version != EC_HOST_RESPONSE_VERSION) { + printk(BIOS_ERR, "EC response version mismatch (%d != %d)\n", + rs.struct_version, EC_HOST_RESPONSE_VERSION); + return -1; + } + + if (rs.reserved) { + printk(BIOS_ERR, "EC response reserved is %d, should be 0\n", + rs.reserved); + return -1; + } + + if (rs.data_len > cec_command->cmd_size_out) { + printk(BIOS_ERR, "EC returned too much data (%d > %d)\n", + rs.data_len, cec_command->cmd_size_out); + return -1; + } + + /* Read back data and update checksum */ + for (i = 0, dout = (uint8_t *)cec_command->cmd_data_out; + i < rs.data_len; i++, dout++) { + *dout = inb(EC_LPC_ADDR_HOST_PACKET + sizeof(rs) + i); + csum += *dout; + } + + /* Verify checksum */ + if ((u8)csum) { + printk(BIOS_ERR, "EC response has invalid checksum\n"); + return -1; + } + + return 0; +} + +static int google_chromeec_command_v1(struct chromeec_command *cec_command) { struct ec_lpc_host_args args; const u8 *d; @@ -134,7 +270,36 @@ int google_chromeec_command(struct chromeec_command *cec_command) return 0; } -#ifndef __PRE_RAM__ +#ifdef __PRE_RAM__ + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + switch (google_chromeec_command_version()) { + case EC_HOST_CMD_FLAG_VERSION_3: + return google_chromeec_command_v3(cec_command); + case EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED: + return google_chromeec_command_v1(cec_command); + } + return -1; +} + +#else /* !__PRE_RAM__ */ + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + static int command_version = 0; + + if (command_version <= 0) + command_version = google_chromeec_command_version(); + + switch (command_version) { + case EC_HOST_CMD_FLAG_VERSION_3: + return google_chromeec_command_v3(cec_command); + case EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED: + return google_chromeec_command_v1(cec_command); + } + return -1; +} #ifndef __SMM__ static void lpc_ec_init(struct device *dev)

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coreboot-gerrit April 2015