Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9201
-gerrit
commit ad1faecaf89cd369362133610d465198a4436cf6
Author: Ted Kuo <tedkuo(a)ami.com.tw>
Date: Tue Sep 16 15:31:21 2014 +0800
Baytrail: add _PRT to each PCIe root port device
Report PCI routing table of all PCIe root ports for legacy interrupt.
Some PCIe devices using legacy interrupt can't work if PCI routing table
isn't defined. It's necessary and defined in BWG Chapter 28.1.3.
BUG=chrome-os-partner:31943
TEST=compiled and tested
BRANCH=NONE
Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw>
Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45
Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b
Original-Reviewed-on: https://chromium-review.googlesource.com/218422
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Ted Kuo <tedkuo(a)ami.com.tw>
Original-Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo(a)ami.com.tw>
---
src/soc/intel/baytrail/acpi/pcie.asl | 109 +++++++++++++++++++++++++++
src/soc/intel/baytrail/acpi/southcluster.asl | 3 +
2 files changed, 112 insertions(+)
diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl
new file mode 100644
index 0000000..5ad4e78
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/pcie.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+ Name (_ADR, 0x001c0000)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+ })
+ }
+ }
+}
+
+Device (RP02)
+{
+ Name (_ADR, 0x001c0001)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+ })
+ }
+ }
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x001c0002)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+ })
+ }
+ }
+}
+
+Device (RP04)
+{
+ Name (_ADR, 0x001c0003)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+ })
+ }
+ }
+}
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 5382182..354515b 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -254,6 +254,9 @@ Device (IOSF)
// IRQ routing for each PCI device
#include "irqroute.asl"
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
Scope (\_SB)
{
// GPIO Devices
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9200
-gerrit
commit 53b2e69fb98deed42040fff144d6353f3c03c8a6
Author: Kein Yuan <kein.yuan(a)intel.com>
Date: Fri Jun 27 09:12:57 2014 -0700
Baytrail: changes to USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current
on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands
for these processors.
Pre-conversion materials are compatible with USB PLL VCO current increase.
Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL
VCO current.
BUG=chrome-os-partner:31199
TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register
has new value.
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b
Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0
Original-Signed-off-by: Kein Yuan <kein.yuan(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211337
Original-Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d)
Original-Reviewed-on: https://chromium-review.googlesource.com/205970
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217772
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6
---
src/soc/intel/baytrail/xhci.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 19339e4..21a0c5f 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -27,6 +27,8 @@
#include <baytrail/iomap.h>
#include <baytrail/iosf.h>
+#include <baytrail/lpc.h>
+#include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
@@ -227,6 +229,13 @@ static void xhci_init(device_t dev)
else
reg_script_run_on_dev(dev, xhci_init_boot_script);
+ /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */
+ if (pattrs_get()->stepping == STEP_C0) {
+ uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL);
+ reg |= 0x00700000;
+ iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg);
+ }
+
/* Finalize Initialization */
reg_script_run_on_dev(dev, xhci_hc_init);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9198
-gerrit
commit 171618f01e37c497c14d4bb0a6d2eb3fd2658276
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Tue Sep 9 10:52:35 2014 -0700
ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASE
For now storm bootblock runs with DRAM fully initialized, this patch
puts the early console between bootblock and rom phase.
BUG=chrome-os-partner:31734
TEST=verified that preram_cbmem_console is set:
$ grep preram_cbmem_console cbfs/fallback/bootblock.map
40618000 A preram_cbmem_console
Change-Id: I2d63f5fde0d3794062068289c648d8bcda11a9a3
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 6bdadad3787d6a4a2d4828b0f300455fedca2b8d
Original-Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217291
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/qualcomm/ipq806x/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index fc78ecc..013d86c 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -55,6 +55,10 @@ config SYS_SDRAM_BASE
hex
default 0x40000000
+config CBMEM_CONSOLE_PRERAM_BASE
+ hex "memory address of the pre-RAM CBMEM console buffer"
+ default 0x40618000
+
config STACK_TOP
hex
default 0x40600000
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9197
-gerrit
commit 6e319915a59d9a7aec97110e7658908d64aaa044
Author: Kane Chen <kane.chen(a)intel.com>
Date: Tue Sep 9 15:53:09 2014 -0700
broadwell: pcie update from BWG/RC code
According to BIOS spec 8.14
B0:D28:F0[5:4] should be set to 11
BRANCH=none
BUG=chrome-os-partner:28234
TEST=build ok, boot to Auron and Samus
make sure register is set and PCIE is working
Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360
Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8
Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217414
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/broadwell/pcie.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index bd1c55a..f63f6d5 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev)
rpc.pin_ownership = pci_read_config32(dev, 0x410);
root_port_config_update_gbe_port();
+ pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
if (dev->chip_info != NULL) {
config_t *config = dev->chip_info;
rpc.coalesce = config->pcie_port_coalesce;
the following patch was just integrated into master:
commit 3e91cffd894336c7ec802f0fc49e25e2a3b4efc6
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Apr 1 08:49:41 2015 -0500
mainboards: fix spd generation
echo is evaluated by a shell builtin producing non-binary
spd data of the form '-e -n \<byte>'. Correct this by
using printf builtin which does the equivalent and is
more cross platform friendly.
Boards changed:
gizmosphere/gizmo
gizmosphere/gizmo2
google/bolt
google/falco
google/link
google/peppy
google/rambi
google/samus
google/slippy
pcengines/apu1
Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9196
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9196 for details.
-gerrit
the following patch was just integrated into master:
commit a30f7e667ca56fdfeea98cbe736b61b67048c621
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Mar 31 20:33:53 2015 -0500
cbfs: correct types used for accessing files
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the
Makefile's were updated to use named types for cbfs
file addition. However, the call sites were not checked to
ensure the types matched. Correct all call sites to use the
named types.
Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9195
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/9195 for details.
-gerrit
the following patch was just integrated into master:
commit 2a567eeb1d14d2f04d338a1ef6fbc7e46e90ed53
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Thu Sep 18 13:47:33 2014 -0700
cbfs: more accurate size check for simple buffer mapping
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data
fails due to the overly strict check. this change allows cbfs_simple_buffer_map
to use all the cache space to the last byte.
BUG=None
TEST=Booted Nyan Blaze.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f
Original-Reviewed-on: https://chromium-review.googlesource.com/218883
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit b0b31da336fa2f87fe73f063782d6243f8262d10)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I15e11e574cd14484fe83c9c3674bb5c2d14422f6
Reviewed-on: http://review.coreboot.org/9178
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9178 for details.
-gerrit