coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: f14ebe0 samus: Clean up touch wake sources
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9214 -gerrit commit f14ebe03050dd6b9521121352f92c95dcd8317de Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 09:27:13 2014 -0700 samus: Clean up touch wake sources Move _PRW to the ACPI devices for the touchpad and touchscreen. Add a _DSW method, but disable it by default for now until a spurious wake issue can be resolved. BUG=chrome-os-partner:32232 BRANCH=samus TEST=build and boot on samus, ensure trackpad does not spuriously wake the system. Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220325 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 42 ++++++++++++++++++--------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 45a0c64..6a2cb97 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#undef ENABLE_TOUCH_WAKE + Scope (\_SB) { Device (LID0) @@ -36,20 +38,6 @@ Scope (\_SB) Name(_HID, EisaId("PNP0C0C")) } - Device (TPAD) - { - Name (_HID, EisaId("PNP0C0E")) - Name (_UID, 1) - Name (_PRW, Package() { 13, 0x3 }) // GPIO13 - } - - Device (TSCR) - { - Name (_HID, EisaId("PNP0C0E")) - Name (_UID, 2) - Name (_PRW, Package() { 14, 0x3 }) // GPIO14 - } - // Keyboard Backlight interface via EC Device (KBLT) { Name (_HID, "GOOG0002") @@ -134,6 +122,7 @@ Scope (\_SB.PCI0.I2C0) Name (_UID, 2) Name (_S0W, 4) Name (ISTP, 1) /* Touchpad */ + Name (GPIO, 13) /* TRACKPAD_INT_L */ Name (_CRS, ResourceTemplate() { @@ -149,6 +138,18 @@ Scope (\_SB.PCI0.I2C0) Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } }) + Name (_PRW, Package() { GPIO, 3 }) + +#ifdef ENABLE_TOUCH_WAKE + Method (_DSW, 3, NotSerialized) + { + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) + } + } +#endif + Method (_STA) { If (LEqual (\S1EN, 1)) { @@ -254,6 +255,7 @@ Scope (\_SB.PCI0.I2C1) Name (_UID, 5) Name (_S0W, 4) Name (ISTP, 0) /* TouchScreen */ + Name (GPIO, 14) /* TOUCH_INT_L */ Name (_CRS, ResourceTemplate() { @@ -269,6 +271,18 @@ Scope (\_SB.PCI0.I2C1) Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } }) + Name (_PRW, Package() { GPIO, 3 }) + +#ifdef ENABLE_TOUCH_WAKE + Method (_DSW, 3, NotSerialized) + { + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) + } + } +#endif + Method (_STA) { If (LEqual (\S2EN, 1)) {

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Patch set updated for coreboot: e599c33 broadwell: Update PCIe configuration to follow BWG
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9197 -gerrit commit e599c3357e3267129af6280750b2370dfb140518 Author: Kane Chen <kane.chen(a)intel.com> Date: Tue Sep 9 15:53:09 2014 -0700 broadwell: Update PCIe configuration to follow BWG According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/broadwell/pcie.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd1c55a..f63f6d5 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev) rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); + pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); if (dev->chip_info != NULL) { config_t *config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce;

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Patch set updated for coreboot: 5d4ee08 samus: Ensure PD controller is in RO mode for recovery
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9205 -gerrit commit 5d4ee0828ab98845e0e9e44faf25925d53d93900 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:56:04 2014 -0700 samus: Ensure PD controller is in RO mode for recovery In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 44d712e..ca43b81 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -43,7 +43,8 @@ void mainboard_romstage_entry(struct romstage_params *rp) printk(BIOS_INFO, "MLB: board version %d\n", google_chromeec_get_board_version()); - /* Ensure the EC is in the right mode for recovery */ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_pd_init(); google_chromeec_early_init(); /* Initialize GPIOs */

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Patch set updated for coreboot: 146a4b9 Broadwell: Reg_Script: add END tag to array "smbus_init_script"
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9221 -gerrit commit 146a4b9014228f045764b03f15c616e1a020ee4b Author: Ryan Lin <ryan.lin(a)intel.com> Date: Wed Oct 1 15:53:39 2014 -0700 Broadwell: Reg_Script: add END tag to array "smbus_init_script" Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script. BUG=chromium:416651 TEST=test on Auron. Change-Id: Ieeaf6c705aa673acc9bb2635e103c4148bc8742f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 172c5fc259a2f6d09daccb1fe53fe0aa7c5601e1 Original-Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e Original-Signed-off-by: Ryan Lin <ryan.lin(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220934 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/broadwell/romstage/smbus.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c index 2bc1492..8b3cde3 100644 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ b/src/soc/intel/broadwell/romstage/smbus.c @@ -39,6 +39,8 @@ static const struct reg_script smbus_init_script[] = { REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), /* Clear errors */ REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, }; void enable_smbus(void)

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Patch set updated for coreboot: e83c0e1 chromeec: Add commands to check PD image type
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9204 -gerrit commit e83c0e1f26e4e5a86f85c16a1573da38173101b7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:54:02 2014 -0700 chromeec: Add commands to check PD image type Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/ec.c | 55 ++++++++++++++++++++++++++++++++++++++++++++- src/ec/google/chromeec/ec.h | 6 +++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1fadeec..a329b5d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -55,6 +55,7 @@ int google_chromeec_kbbacklight(int percent) cec_cmd.cmd_data_out = &rsp_backlight; cec_cmd.cmd_size_in = sizeof(cmd_backlight); cec_cmd.cmd_size_out = sizeof(rsp_backlight); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n", rsp_backlight.percent, cec_cmd.cmd_code); @@ -87,6 +88,7 @@ static u32 google_chromeec_get_mask(u8 type) cmd.cmd_size_in = sizeof(req); cmd.cmd_data_out = &rsp; cmd.cmd_size_out = sizeof(rsp); + cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) == 0) return rsp.mask; @@ -106,6 +108,7 @@ static int google_chromeec_set_mask(u8 type, u32 mask) cmd.cmd_size_in = sizeof(req); cmd.cmd_data_out = &rsp; cmd.cmd_size_out = sizeof(rsp); + cmd.cmd_dev_index = 0; return google_chromeec_command(&cmd); } @@ -123,16 +126,18 @@ int google_chromeec_clear_events_b(u32 mask) } #ifndef __SMM__ +#ifdef __PRE_RAM__ void google_chromeec_check_ec_image(int expected_type) { struct chromeec_command cec_cmd; - struct ec_response_get_version cec_resp = {{0}}; + struct ec_response_get_version cec_resp = { { 0 } }; cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) { @@ -145,6 +150,7 @@ void google_chromeec_check_ec_image(int expected_type) cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); @@ -163,6 +169,46 @@ void google_chromeec_early_init(void) } } +void google_chromeec_check_pd_image(int expected_type) +{ + struct chromeec_command cec_cmd; + struct ec_response_get_version cec_resp = { { 0 } }; + + cec_cmd.cmd_code = EC_CMD_GET_VERSION; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_out = &cec_resp; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 1; /* PD */ + google_chromeec_command(&cec_cmd); + + if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) { + struct ec_params_reboot_ec reboot_ec; + /* Reboot the PD and make it come back in RO mode */ + reboot_ec.cmd = EC_REBOOT_COLD; + reboot_ec.flags = 0; + cec_cmd.cmd_code = EC_CMD_REBOOT_EC; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &reboot_ec; + cec_cmd.cmd_size_in = sizeof(reboot_ec); + cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 1; /* PD */ + printk(BIOS_DEBUG, "Rebooting PD to RO mode\n"); + google_chromeec_command(&cec_cmd); + udelay(1000); + } +} + +/* Check for recovery mode and ensure PD is in RO */ +void google_chromeec_early_pd_init(void) +{ + /* If in recovery ensure PD is running RO firmware. */ + if (recovery_mode_enabled()) { + google_chromeec_check_pd_image(EC_IMAGE_RO); + } +} +#endif + u16 google_chromeec_get_board_version(void) { struct chromeec_command cmd; @@ -173,6 +219,7 @@ u16 google_chromeec_get_board_version(void) cmd.cmd_size_in = 0; cmd.cmd_size_out = sizeof(board_v); cmd.cmd_data_out = &board_v; + cmd.cmd_dev_index = 0; if (google_chromeec_command(&cmd) != 0) return 0; @@ -196,6 +243,7 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) cec_cmd.cmd_data_out = &rsp_vbnvcontext; cec_cmd.cmd_size_in = sizeof(cmd_vbnvcontext); cec_cmd.cmd_size_out = is_read ? sizeof(rsp_vbnvcontext) : 0; + cec_cmd.cmd_dev_index = 0; cmd_vbnvcontext.op = is_read ? EC_VBNV_CONTEXT_OP_READ : EC_VBNV_CONTEXT_OP_WRITE; @@ -281,6 +329,7 @@ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, cmd.cmd_size_in = size + write_len; cmd.cmd_data_out = r; cmd.cmd_size_out = sizeof(*r) + read_len; + cmd.cmd_dev_index = 0; rv = google_chromeec_command(&cmd); if (rv != 0) return rv; @@ -384,6 +433,7 @@ int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode) cmd.cmd_data_in = &set_mode; cmd.cmd_size_out = 0; cmd.cmd_data_out = NULL; + cmd.cmd_dev_index = 0; return google_chromeec_command(&cmd); } @@ -403,6 +453,7 @@ int google_chromeec_hello(void) cec_cmd.cmd_data_out = &rsp_hello.out_data; cec_cmd.cmd_size_in = sizeof(cmd_hello.in_data); cec_cmd.cmd_size_out = sizeof(rsp_hello.out_data); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome EC: Hello got back %x status (%x)\n", rsp_hello.out_data, cec_cmd.cmd_code); @@ -425,6 +476,7 @@ void google_chromeec_init(void) cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code) { @@ -451,6 +503,7 @@ void google_chromeec_init(void) cec_cmd.cmd_data_in = &reboot_ec; cec_cmd.cmd_size_in = sizeof(reboot_ec); cec_cmd.cmd_size_out = 0; /* ignore response, if any */ + cec_cmd.cmd_dev_index = 0; printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); post_code(0); /* clear current post code */ google_chromeec_command(&cec_cmd); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index e0db8c1..cdf94da 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -36,10 +36,15 @@ int google_ec_running_ro(void); void google_chromeec_init(void); #endif +#ifdef __PRE_RAM__ /* If recovery mode is enabled and EC is not running RO firmware reboot. */ void google_chromeec_early_init(void); +void google_chromeec_early_pd_init(void); /* Reboot if EC firmware is not expected type. */ void google_chromeec_check_ec_image(int expected_type); +void google_chromeec_check_pd_image(int expected_type); +#endif + uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u16 google_chromeec_get_board_version(void); u32 google_chromeec_get_events_b(void); @@ -67,6 +72,7 @@ struct chromeec_command { uint16_t cmd_size_in; /* size of command data */ uint16_t cmd_size_out; /* expected size of command response in, * actual received size out */ + int cmd_dev_index;/* device index for passthru */ }; /*

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Patch set updated for coreboot: 98e6a5d samus: Fix and clean up GPIOs and EC info/events
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9220 -gerrit commit 98e6a5d044e0865f33db8c0014fb8e8a65567d47 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:35:29 2014 -0700 samus: Fix and clean up GPIOs and EC info/events - Define specific GPIOs in gpio.h instaed of smihandler.c - Add battery status event to SCI list - Remove old proto board version defines and SPD index usage - Do not disable cmd_pwr training now that it works on EVT board BUG=chrome-os-partner:32196,chrome-os-partner:29117 BRANCH=samus TEST=build and boot on samus Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220321 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/ec.h | 5 +---- src/mainboard/google/samus/gpio.h | 2 ++ src/mainboard/google/samus/romstage.c | 7 ------- src/mainboard/google/samus/smihandler.c | 17 +++++++---------- src/mainboard/google/samus/spd/spd.c | 4 ---- src/mainboard/google/samus/spd/spd.h | 1 - 6 files changed, 10 insertions(+), 26 deletions(-) diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h index 612d591..1ba1677 100644 --- a/src/mainboard/google/samus/ec.h +++ b/src/mainboard/google/samus/ec.h @@ -22,10 +22,6 @@ #include <ec/google/chromeec/ec_commands.h> -#define SAMUS_EC_BOARD_PROTO1_9 0 -#define SAMUS_EC_BOARD_PROTO2_A 1 -#define SAMUS_EC_BOARD_PROTO2_B 2 - #define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ #define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ @@ -37,6 +33,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index df74a1a..f293dee 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -24,6 +24,8 @@ #define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23 #define SAMUS_GPIO_SSD_RESET_L 47 +#define SAMUS_GPIO_WLAN_DISABLE_L 42 +#define SAMUS_GPIO_LTE_DISABLE_L 59 static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index ca43b81..39a23f0 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -56,13 +56,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; - /* - * Disable use of PEI saved data to work around memory issues. - */ - if (cpu_family_model() == BROADWELL_FAMILY_ULT) { - pei_data.disable_cmd_pwr = 1; - } - /* Initalize memory */ romstage_common(rp); diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c index 932d606..a97f426 100644 --- a/src/mainboard/google/samus/smihandler.c +++ b/src/mainboard/google/samus/smihandler.c @@ -31,10 +31,7 @@ #include <broadwell/pm.h> #include <broadwell/smm.h> #include "ec.h" - -#define GPIO_SSD_RESET_L 47 -#define GPIO_WLAN_DISABLE_L 42 -#define GPIO_LTE_DISABLE_L 59 +#include "gpio.h" int mainboard_io_trap_handler(int smif) { @@ -104,11 +101,11 @@ void mainboard_smi_sleep(u8 slp_typ) } /* Put SSD in reset to prevent leak. */ - set_gpio(GPIO_SSD_RESET_L, 0); + set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S3. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); + set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); + set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); @@ -122,11 +119,11 @@ void mainboard_smi_sleep(u8 slp_typ) } /* Put SSD in reset to prevent leak. */ - set_gpio(GPIO_SSD_RESET_L, 0); + set_gpio(SAMUS_GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S5. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); + set_gpio(SAMUS_GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); + set_gpio(SAMUS_GPIO_LTE_DISABLE_L, 0); /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 00e694e..0051fee 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -93,10 +93,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) int spd_file_len; struct cbfs_file *spd_file; - /* Proto2B boards use a different GPIO for SPD index bit 3 */ - if (google_chromeec_get_board_version() <= SAMUS_EC_BOARD_PROTO2_A) - spd_bits[3] = SPD_GPIO_BIT3_OLD; - spd_gpio[0] = get_gpio(spd_bits[0]); spd_gpio[1] = get_gpio(spd_bits[1]); spd_gpio[2] = get_gpio(spd_bits[2]); diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 4b2f3aa..27d1469 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -37,7 +37,6 @@ #define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT2 67 #define SPD_GPIO_BIT3 65 -#define SPD_GPIO_BIT3_OLD 66 struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);

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Patch set updated for coreboot: b03e159 vpd: retrieve mac addresses and pass them to bootloader
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9207 -gerrit commit b03e15944a22326e363402548d3092415c300fc0 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 22 18:48:41 2014 -0700 vpd: retrieve mac addresses and pass them to bootloader Chrome OS devices firmware usually includes an area called VPD (Vital Product Data). VPD is a blob of a certain structure, in particular containing freely defined variable size fields. A field is a tuple of the field name and field contents. MAC addresses of the interfaces are stored in VPD as well. Field names are in the form of 'ethernet_macN', where N is the zero based interface number. This patch retrieves the MAC address(es) from the VPD and populates them in the coreboot table so that they become available to the bootloader. BUG=chrome-os-partner:32152, chromium:417117 TEST=with this and other patches in place the storm device tree shows up with MAC addresses properly initialized. Change-Id: I955207b3a644cde100cc4b48e51a2ab9a3cb1ba0 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 1972b9e97b57cc8503c5e4dc496706970ed2ffbe Original-Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219443 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 13 +++++++ src/lib/coreboot_table.c | 74 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 46c1df5..0efb8fd 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -263,6 +263,19 @@ struct lb_board_id { uint32_t board_id; }; +#define LB_TAG_MAC_ADDRS 0x0026 +struct mac_address { + uint8_t mac_addr[6]; + uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ +}; + +struct lb_macs { + uint32_t tag; + uint32_t size; + uint32_t count; + struct mac_address mac_addrs[0]; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d6d84cd..a8b5edf 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -38,6 +38,7 @@ #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <vendorcode/google/chromeos/cros_vpd.h> #endif #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> @@ -157,9 +158,79 @@ void fill_lb_gpio(struct lb_gpio *gpio, int num, } #if CONFIG_CHROMEOS +static void lb_macs(struct lb_header *header) +{ + /* + * In case there is one or more MAC addresses stored in the VPD, the + * key is "ethernet_mac{0..9}", up to 10 values. + */ + static const char mac_addr_key_base[] = "ethernet_mac0"; + char mac_addr_key[sizeof(mac_addr_key_base)]; + char mac_addr_str[13]; /* 12 symbols and the trailing zero. */ + int count; + struct lb_macs *macs = NULL; + const int index_of_index = sizeof(mac_addr_key) - 2; + + /* + * MAC addresses are stored in the VPD as strings of hex numbers, + * which need to be converted into binary for storing in the coreboot + * table. + */ + strcpy(mac_addr_key, mac_addr_key_base); + count = 0; + do { + int i; + + if (!cros_vpd_gets(mac_addr_key, mac_addr_str, + sizeof(mac_addr_str))) + break; /* No more MAC addresses in VPD */ + + if (!macs) { + macs = (struct lb_macs *)lb_new_record(header); + macs->tag = LB_TAG_MAC_ADDRS; + } + + /* MAC address in symbolic form is in mac_addr_str. */ + for (i = 0; i < sizeof(macs->mac_addrs[0].mac_addr); i++) { + int j; + uint8_t n = 0; + + for (j = 0; j < 2; j++) { + char c = mac_addr_str[i * 2 + j]; + + if (isxdigit(c)) { + if (isdigit(c)) + c -= '0'; + else + c = tolower(c) - 'a' + 10; + } else { + printk(BIOS_ERR, + "%s: non hexadecimal symbol " + "%#2.2x in the VPD field %s\n", + __func__, (uint8_t)c, + mac_addr_key); + c = 0; + } + n <<= 4; + n |= c; + } + macs->mac_addrs[count].mac_addr[i] = n; + } + count++; + mac_addr_key[index_of_index] = '0' + count; + } while (count < 10); + + if (!count) + return; /* No MAC addresses in the VPD. */ + + macs->count = count; + macs->size = sizeof(*macs) + count * sizeof(struct mac_address); +} + static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; + gpios = (struct lb_gpios *)lb_new_record(header); gpios->tag = LB_TAG_GPIO; gpios->size = sizeof(*gpios); @@ -446,6 +517,9 @@ unsigned long write_coreboot_table( /* pass along the vboot_handoff address. */ lb_vboot_handoff(head); + + /* Retrieve mac addresses from VPD, if any. */ + lb_macs(head); #endif /* Add board ID if available */

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Patch set updated for coreboot: 5b63293 Samus: Synchronization with FRC to enable PCIe Relaxed Order.
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9206 -gerrit commit 5b632930942b2c44241954fb9f5f609a818582ed Author: Kenji Chen <kenji.chen(a)intel.com> Date: Sat Sep 20 01:39:20 2014 +0800 Samus: Synchronization with FRC to enable PCIe Relaxed Order. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 --- src/soc/intel/broadwell/lpc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index d7a3e82..5efcb73 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -207,6 +207,9 @@ static const struct reg_script pch_misc_init_script[] = { /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + /* Enable PCIe Releaxed Order */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE

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Patch set updated for coreboot: fa05648 arm: Prevent compilation of old, experimental SMP support
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9222 -gerrit commit fa0564886926c367123d15927c3d1e1d6ecb2400 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 23 20:53:20 2014 -0700 arm: Prevent compilation of old, experimental SMP support The ARM SMP feature was added a long time ago and has never really been used by anyone since. We are still always compiling cpu_info() even though we don't use it, and it makes some dangerous assumptions about stack alignment that are not guaranteed anywhere. I'm planning to change the way the stack boundaries are defined. Rather than trying to work that into this unsafe, unused and hard to test feature, I think we should just seal it off with police tape and make sure that if anyone ever tries to use it again (which currently seems unlikely), they get forced to do their due diligence on making sure it works as intended. BUG=None TEST=Compiled Veyron_Pinky. Change-Id: Id25545cab88f29200c7672ef02c7804f0ac26399 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 5b517fc46b030a6e50ef2f5e4d4a449b98ce16c6 Original-Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219680 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/arm/Makefile.inc | 2 +- src/arch/arm/cpu.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 25f764c..e739d0b 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -117,7 +117,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y) ramstage-y += stages.c ramstage-y += div0.c -ramstage-y += cpu.c +ramstage-$(CONFIG_COOP_MULTITASKING) += cpu.c ramstage-y += eabi_compat.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index f90c759..e02fed3 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -34,6 +34,11 @@ */ struct cpu_info *cpu_info(void) { +#error "This is BROKEN! ARM stacks are currently not guaranteed to be " \ + "STACK_SIZE-aligned in any way. If you ever plan to revive this " \ + "feature, make sure you add the proper assertions " \ + "(and maybe consider revising the whole thing to work closer to what " \ + "arm64 is doing now)." uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0), CONFIG_STACK_SIZE); addr -= sizeof(struct cpu_info);

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Patch set updated for coreboot: 0277cc1 baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9200 -gerrit commit 0277cc16e506ba9d93871444a7e7ae796f225529 Author: Kein Yuan <kein.yuan(a)intel.com> Date: Fri Jun 27 09:12:57 2014 -0700 baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 --- src/soc/intel/baytrail/xhci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 19339e4..21a0c5f 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -27,6 +27,8 @@ #include <baytrail/iomap.h> #include <baytrail/iosf.h> +#include <baytrail/lpc.h> +#include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/ramstage.h> @@ -227,6 +229,13 @@ static void xhci_init(device_t dev) else reg_script_run_on_dev(dev, xhci_init_boot_script); + /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ + if (pattrs_get()->stepping == STEP_C0) { + uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); + reg |= 0x00700000; + iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); + } + /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init);

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coreboot-gerrit April 2015