coreboot-gerrit April 2015

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Patch set updated for coreboot: d5cced3 program loading: introduce struct prog
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8839 -gerrit commit d5cced33270786bec88e0b51551e3628b7308c1b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 13:00:20 2015 -0500 program loading: introduce struct prog The struct prog serves as way to consolidate program loading. This abstraction can be used to perform more complicated execution paths such as running a program on a separate CPU after it has been loaded. Currently t124 and t132 need to do that in the boot path. Follow on patches will allow the platform to decide how to execute a particular program. Note: the vboot path is largely untouched because it's already broken in the coreboot.org tree. After getting all the necessary patches pushed then vboot will be fixed. Change-Id: Ic6e6fe28c5660fb41edee5fd8661eaf58222f883 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/boot.c | 11 ++- src/arch/arm64/boot.c | 16 +++-- src/arch/mips/boot.c | 4 +- src/arch/riscv/boot.c | 5 +- src/arch/x86/boot/boot.c | 5 +- src/include/cbfs.h | 3 + src/include/program_loading.h | 119 +++++++++++++++++++------------- src/lib/arch_ops.c | 1 - src/lib/cbfs.c | 53 +++++++++++--- src/lib/loaders/cbfs_payload_loader.c | 5 +- src/lib/loaders/cbfs_ramstage_loader.c | 29 +++----- src/lib/loaders/load_and_run_payload.c | 22 +++--- src/lib/loaders/load_and_run_ramstage.c | 43 +++++------- src/lib/loaders/load_and_run_romstage.c | 12 ++-- src/lib/ramstage_cache.c | 55 ++++++++------- src/lib/selfboot.c | 2 +- 16 files changed, 215 insertions(+), 170 deletions(-) diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 5217a9f..9dc6dbd 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -18,17 +18,14 @@ */ #include <arch/cache.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> #include <program_loading.h> void arch_payload_run(const struct payload *payload) { - void (*doit)(void *) = payload->entry; - void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); + void (*doit)(void *); - printk(BIOS_SPEW, "entry = %p\n", payload->entry); cache_sync_instructions(); - doit(cb_tables); + + doit = prog_entry(&payload->prog); + doit(prog_entry_arg(&payload->prog)); } diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 01630f3..74282a9 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -23,21 +23,23 @@ #include <arch/stages.h> #include <arch/spintable.h> #include <arch/transition.h> -#include <cbmem.h> #include <console/console.h> #include <program_loading.h> #include <string.h> void arch_payload_run(const struct payload *payload) { - void (*payload_entry)(void *) = payload->entry; + void (*doit)(void *); + void *arg; + + doit = prog_entry(&payload->prog); + arg = prog_entry_arg(&payload->prog); - void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); uint8_t current_el = get_current_el(); - printk(BIOS_SPEW, "entry = %p\n", payload->entry); + printk(BIOS_SPEW, "entry = %p\n", doit); - secmon_run(payload_entry, cb_tables); + secmon_run(doit, arg); /* Start the other CPUs spinning. */ spintable_start(); @@ -46,7 +48,7 @@ void arch_payload_run(const struct payload *payload) if (current_el != EL3) { cache_sync_instructions(); /* Point of no-return */ - payload_entry(cb_tables); + doit(arg); } /* If current EL is EL3, we transition to payload in EL2. */ @@ -57,5 +59,5 @@ void arch_payload_run(const struct payload *payload) exc_state.elx.spsr = get_eret_el(EL2, SPSR_USE_L); cache_sync_instructions(); - transition_with_entry(payload->entry, cb_tables, &exc_state); + transition_with_entry(doit, arg, &exc_state); } diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index b213ffc..6e12d10 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -17,12 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/stages.h> #include <program_loading.h> void arch_payload_run(const struct payload *payload) { - printk(BIOS_SPEW, "entry = %p\n", payload->entry); - stage_exit(payload->entry); + stage_exit(prog_entry(&payload->prog)); } diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ff65cc3..4c2be03 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/stages.h> #include <program_loading.h> -#include <console/uart.h> void arch_payload_run(const struct payload *payload) { - printk(BIOS_SPEW, "entry = %p\n", payload->entry); // uart_rx_byte(0); - stage_exit(payload->entry); + stage_exit(prog_entry(&payload->prog)); } diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 8f7f0e0..1fb36e2 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -126,8 +126,9 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) void arch_payload_run(const struct payload *payload) { if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) - jmp_payload_no_bounce_buffer(payload->entry); + jmp_payload_no_bounce_buffer(prog_entry(&payload->prog)); else - jmp_payload(payload->entry, (uintptr_t)payload->bounce.data, + jmp_payload(prog_entry(&payload->prog), + (uintptr_t)payload->bounce.data, payload->bounce.size); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 4911848..fcc55b5 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -57,6 +57,9 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, uint16_t device, void * dest); void *cbfs_load_stage(struct cbfs_media *media, const char *name); void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset); +/* Load a stage from a prog structure. Returns < 0 on error. 0 on success. */ +struct prog; +int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog); /* Simple buffer for streaming media. */ struct cbfs_simple_buffer { diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 85ccd3c..38047c7 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -29,10 +29,67 @@ enum { SEG_FINAL = 1 << 0, }; -/* Called for each segment of a program loaded. The PROG_FLAG_FINAL will be +/* Called for each segment of a program loaded. The SEG_FINAL flag will be * set on the last segment loaded. */ void arch_segment_loaded(uintptr_t start, size_t size, int flags); +struct buffer_area { + void *data; + size_t size; +}; + +enum prog_type { + PROG_ROMSTAGE, + PROG_RAMSTAGE, + PROG_PAYLOAD, +}; + +/* Representation of a program. */ +struct prog { + enum prog_type type; + const char *name; + /* The area can mean different things depending on what type the + * program is. e.g. a payload prog uses this field for the backing + * store of the payload_segments and data. */ + struct buffer_area area; + /* Entry to program with optional argument. It's up to the architecture + * to decide if argument is passed. */ + void (*entry)(void *); + void *arg; +}; + +static inline size_t prog_size(const struct prog *prog) +{ + return prog->area.size; +} + +static inline void *prog_start(const struct prog *prog) +{ + return prog->area.data; +} + +static inline void *prog_entry(const struct prog *prog) +{ + return prog->entry; +} + +static inline void *prog_entry_arg(const struct prog *prog) +{ + return prog->arg; +} + +static inline void prog_set_area(struct prog *prog, void *start, size_t size) +{ + prog->area.data = start; + prog->area.size = size; +} + +static inline void prog_set_entry(struct prog *prog, void *e, void *arg) +{ + prog->entry = e; + prog->arg = arg; +} + /************************ * ROMSTAGE LOADING * ************************/ @@ -45,67 +102,35 @@ void run_romstage(void); ************************/ struct romstage_handoff; -struct cbmem_entry; - -#if defined(__PRE_RAM__) -#if CONFIG_RELOCATABLE_RAMSTAGE -/* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined - * to be weak so that board and chipset code may override them. Their job is to - * cache and load the ramstage for quick S3 resume. By default a copy of the - * relocated ramstage is saved using the cbmem infrastructure. These - * functions are only valid during romstage. */ - -/* The implementer of cache_loaded_ramstage() may use the romstage_handoff - * structure to store information, but note that the handoff variable can be - * NULL. The ramstage cbmem_entry represents the region occupied by the loaded - * ramstage. */ -void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point); -/* Return NULL on error or entry point on success. The ramstage cbmem_entry is - * the region where to load the cached contents to. */ -void * load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage); -#else /* CONFIG_RELOCATABLE_RAMSTAGE */ - -static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point) -{ -} - -static inline void * -load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) -{ - return NULL; -} - -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#endif /* defined(__PRE_RAM__) */ +#if IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) +/* Cache the loaded ramstage described by prog. */ +void cache_loaded_ramstage(struct romstage_handoff *, struct prog *p); +/* Load ramstage from cache filling in struct prog. */ +void load_cached_ramstage(struct romstage_handoff *h, struct prog *p); +#else +static inline void cache_loaded_ramstage(struct romstage_handoff *h, + struct prog *p) {} +static inline void load_cached_ramstage(struct romstage_handoff *h, + struct prog *p) {} +#endif /* Run ramstage from romstage. */ void run_ramstage(void); struct ramstage_loader_ops { const char *name; - void *(*load)(uint32_t cbmem_id, const char *name, - const struct cbmem_entry **cbmem_entry); + /* Returns 0 on succes. < 0 on error. */ + int (*load)(struct prog *ramstage); }; /*********************** * PAYLOAD LOADING * ***********************/ -struct buffer_area { - void *data; - size_t size; -}; - struct payload { - const char *name; - struct buffer_area backing_store; + struct prog prog; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; - void *entry; }; /* Load payload into memory in preparation to run. */ diff --git a/src/lib/arch_ops.c b/src/lib/arch_ops.c index b9f5719..ac1be77 100644 --- a/src/lib/arch_ops.c +++ b/src/lib/arch_ops.c @@ -26,4 +26,3 @@ void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, { /* do nothing */ } - diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index ebcc134..fc6e887 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -74,17 +74,18 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset) +static int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, + struct prog *prog, ssize_t offset) { struct cbfs_stage stage; struct cbfs_media backing_store; if (init_backing_media(&media, &backing_store)) - return (void *)-1; + return -1; if (cbfs_read(media, &stage, offset, sizeof(stage)) != sizeof(stage)) { ERROR("ERROR: failed to read stage header\n"); - return (void *)-1; + return -1; } LOG("loading stage @ 0x%llx (%d bytes), entry @ 0x%llx\n", @@ -97,41 +98,71 @@ void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset) if (cbfs_read(media, (void *)(uintptr_t)stage.load, offset + sizeof(stage), stage.len) != stage.len) { ERROR("ERROR: Reading stage failed.\n"); - return (void *)-1; + return -1; } } else { void *data = media->map(media, offset + sizeof(stage), stage.len); if (data == CBFS_MEDIA_INVALID_MAP_ADDRESS) { ERROR("ERROR: Mapping stage failed.\n"); - return (void *)-1; + return -1; } if (!cbfs_decompress(stage.compression, data, (void *)(uintptr_t)stage.load, stage.len)) - return (void *)-1; + return -1; media->unmap(media, data); } arch_segment_loaded(stage.load, stage.memlen, SEG_FINAL); DEBUG("stage loaded\n"); - return (void *)(uintptr_t)stage.entry; + prog_set_area(prog, (void *)(uintptr_t)stage.load, stage.memlen); + prog_set_entry(prog, (void *)(uintptr_t)stage.entry, NULL); + + return 0; } -void *cbfs_load_stage(struct cbfs_media *media, const char *name) +int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog) { struct cbfs_file file; ssize_t offset; struct cbfs_media backing_store; if (init_backing_media(&media, &backing_store)) - return (void *)-1; + return -1; - offset = cbfs_locate_file(media, &file, name); + offset = cbfs_locate_file(media, &file, prog->name); if (offset < 0 || file.type != CBFS_TYPE_STAGE) + return -1; + + if (cbfs_load_prog_stage_by_offset(media, prog, offset) < 0) + return -1; + + return 0; +} + +void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset) +{ + struct prog prog = { + .name = NULL, + }; + + if (cbfs_load_prog_stage_by_offset(media, &prog, offset) < 0) + return (void *)-1; + + return prog_entry(&prog); +} + +void *cbfs_load_stage(struct cbfs_media *media, const char *name) +{ + struct prog prog = { + .name = name, + }; + + if (cbfs_load_prog_stage(media, &prog) < 0) return (void *)-1; - return cbfs_load_stage_by_offset(media, offset); + return prog_entry(&prog); } /* Simple buffer */ diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 22f4c2f..609d123 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -26,14 +26,13 @@ static int cbfs_locate_payload(struct payload *payload) size_t size; const int type = CBFS_TYPE_PAYLOAD; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, + buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->prog.name, type, &size); if (buffer == NULL) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + prog_set_area(&payload->prog, buffer, size); return 0; } diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c index 5155aea..27be88e 100644 --- a/src/lib/loaders/cbfs_ramstage_loader.c +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -19,44 +19,37 @@ */ #include <console/console.h> #include <cbfs.h> -#include <arch/stages.h> #include <program_loading.h> -#include <timestamp.h> #if CONFIG_RELOCATABLE_RAMSTAGE #include <rmodule.h> +#include <cbmem.h> -static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, - const struct cbmem_entry **cbmem_entry) +static int cbfs_load_ramstage(struct prog *ramstage) { struct rmod_stage_load rmod_ram = { - .cbmem_id = cbmem_id, - .name = name, + .cbmem_id = CBMEM_ID_RAMSTAGE, + .name = ramstage->name, }; if (rmodule_stage_load_from_cbfs(&rmod_ram)) { printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return NULL; + return -1; } - *cbmem_entry = rmod_ram.cbmem_entry; + prog_set_area(ramstage, cbmem_entry_start(rmod_ram.cbmem_entry), + cbmem_entry_size(rmod_ram.cbmem_entry)); + prog_set_entry(ramstage, rmod_ram.entry, NULL); - return rmod_ram.entry; + return 0; } #else /* CONFIG_RELOCATABLE_RAMSTAGE */ -static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, - const struct cbmem_entry **cbmem_entry) +static int cbfs_load_ramstage(struct prog *ramstage) { - void *entry; + return cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, ramstage); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); - - if ((void *)entry == (void *) -1) - entry = NULL; - - return entry; } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 89b6da6..8e745c9 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <stdlib.h> +#include <cbmem.h> #include <console/console.h> #include <fallback.h> #include <lib.h> @@ -36,7 +37,10 @@ static const struct payload_loader_ops *payload_ops[] = { }; static struct payload global_payload = { - .name = CONFIG_CBFS_PREFIX "/payload", + .prog = { + .name = CONFIG_CBFS_PREFIX "/payload", + .type = PROG_PAYLOAD, + }, }; void __attribute__((weak)) mirror_payload(struct payload *payload) @@ -47,9 +51,9 @@ void __attribute__((weak)) mirror_payload(struct payload *payload) void payload_load(void) { int i; - void *entry; const struct payload_loader_ops *ops; struct payload *payload = &global_payload; + struct prog * prog = &payload->prog; for (i = 0; i < ARRAY_SIZE(payload_ops); i++) { ops = payload_ops[i]; @@ -59,8 +63,7 @@ void payload_load(void) continue; } printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); + ops->name, prog_start(prog), prog_size(prog)); break; } @@ -69,12 +72,12 @@ void payload_load(void) mirror_payload(payload); - entry = selfload(payload); - - payload->entry = entry; + /* Pass cbtables to payload if architecture desires it. */ + prog_set_entry(&payload->prog, selfload(payload), + cbmem_find(CBMEM_ID_CBTABLE)); out: - if (payload->entry == NULL) + if (prog_entry(&payload->prog) == NULL) die("Payload not loaded.\n"); } @@ -85,7 +88,8 @@ void payload_run(void) /* Reset to booting from this image as late as possible */ boot_successful(); - printk(BIOS_DEBUG, "Jumping to boot code at %p\n", payload->entry); + printk(BIOS_DEBUG, "Jumping to boot code at %p(%p)\n", + prog_entry(&payload->prog), prog_entry_arg(&payload->prog)); post_code(POST_ENTER_ELF_BOOT); timestamp_add_now(TS_SELFBOOT_JUMP); diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index b24e29f..82bc1e0 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <arch/stages.h> #include <cbfs.h> -#include <cbmem.h> #include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> @@ -36,46 +35,32 @@ static const struct ramstage_loader_ops *loaders[] = { &cbfs_ramstage_loader, }; -static const char *ramstage_name = CONFIG_CBFS_PREFIX "/ramstage"; -static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; - static void -load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +load_ramstage(const struct ramstage_loader_ops *ops, + struct romstage_handoff *handoff, struct prog *ramstage) { - const struct cbmem_entry *cbmem_entry; - void *entry_point; - timestamp_add_now(TS_START_COPYRAM); - entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); - if (entry_point == NULL) + if (ops->load(ramstage)) return; - cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + cache_loaded_ramstage(handoff, ramstage); timestamp_add_now(TS_END_COPYRAM); - stage_exit(entry_point); + stage_exit(prog_entry(ramstage)); } -static void run_ramstage_from_resume(struct romstage_handoff *handoff) +static void run_ramstage_from_resume(struct romstage_handoff *handoff, + struct prog *ramstage) { - void *entry; - const struct cbmem_entry *cbmem_entry; - if (handoff != NULL && handoff->s3_resume) { - cbmem_entry = cbmem_entry_find(ramstage_id); - - /* No place to load ramstage. */ - if (cbmem_entry == NULL) - return; - /* Load the cached ramstage to runtime location. */ - entry = load_cached_ramstage(handoff, cbmem_entry); + load_cached_ramstage(handoff, ramstage); - if (entry != NULL) { + if (prog_entry(ramstage) != NULL) { printk(BIOS_DEBUG, "Jumping to image.\n"); - stage_exit(entry); + stage_exit(prog_entry(ramstage)); } } } @@ -85,15 +70,19 @@ void run_ramstage(void) struct romstage_handoff *handoff; const struct ramstage_loader_ops *ops; int i; + struct prog ramstage = { + .name = CONFIG_CBFS_PREFIX "/ramstage", + .type = PROG_RAMSTAGE, + }; handoff = romstage_handoff_find_or_add(); - run_ramstage_from_resume(handoff); + run_ramstage_from_resume(handoff, &ramstage); for (i = 0; i < ARRAY_SIZE(loaders); i++) { ops = loaders[i]; printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); - load_ramstage(ops, handoff); + load_ramstage(ops, handoff, &ramstage); } die("Ramstage was not loaded!\n"); diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index ebc1243..3ad9176 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -27,16 +27,16 @@ void run_romstage(void) { - void *entry; + struct prog romstage = { + .name = CONFIG_CBFS_PREFIX "/romstage", + .type = PROG_ROMSTAGE, + }; - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - - if (entry == (void *)-1) { + if (cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, &romstage) < 0) { if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) die("Couldn't load romstage.\n"); halt(); } - stage_exit(entry); + stage_exit(prog_entry(&romstage)); } diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c index d61f1c1..1dd40c7 100644 --- a/src/lib/ramstage_cache.c +++ b/src/lib/ramstage_cache.c @@ -27,8 +27,7 @@ #if CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, - void *entry_point) + struct prog *ramstage) { struct ramstage_cache *cache; uint32_t total_size; @@ -36,8 +35,8 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, void *ramstage_base; long cache_size = 0; - ramstage_size = cbmem_entry_size(ramstage); - ramstage_base = cbmem_entry_start(ramstage); + ramstage_size = prog_size(ramstage); + ramstage_base = prog_start(ramstage); cache = ramstage_cache_location(&cache_size); @@ -56,7 +55,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, } cache->magic = RAMSTAGE_CACHE_MAGIC; - cache->entry_point = (uint32_t)entry_point; + cache->entry_point = (uint32_t)prog_entry(ramstage); cache->load_address = (uint32_t)ramstage_base; cache->size = ramstage_size; @@ -68,11 +67,11 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, if (handoff == NULL) return; - handoff->ramstage_entry_point = (uint32_t)entry_point; + handoff->ramstage_entry_point = cache->entry_point; } -void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) +void load_cached_ramstage(struct romstage_handoff *handoff, + struct prog *ramstage) { struct ramstage_cache *cache; long size = 0; @@ -82,14 +81,15 @@ void *load_cached_ramstage(struct romstage_handoff *handoff, if (!ramstage_cache_is_valid(cache)) { printk(BIOS_DEBUG, "Invalid ramstage cache found.\n"); ramstage_cache_invalid(cache); - return NULL; + return; } printk(BIOS_DEBUG, "Loading ramstage from %p.\n", cache); - memcpy((void *)cache->load_address, &cache->program[0], cache->size); + prog_set_area(ramstage, (void *)cache->load_address, cache->size); + prog_set_entry(ramstage, (void *)cache->entry_point, NULL); - return (void *)cache->entry_point; + memcpy((void *)cache->load_address, &cache->program[0], cache->size); } #else @@ -97,7 +97,7 @@ void *load_cached_ramstage(struct romstage_handoff *handoff, /* Cache relocated ramstage in CBMEM. */ void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point) + struct prog *ramstage) { uint32_t ramstage_size; const struct cbmem_entry *entry; @@ -105,7 +105,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, if (handoff == NULL) return; - ramstage_size = cbmem_entry_size(ramstage); + ramstage_size = prog_size(ramstage); /* cbmem_entry_add() does a find() before add(). */ entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size); @@ -113,30 +113,37 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, return; /* Keep track of the entry point in the handoff structure. */ - handoff->ramstage_entry_point = (uint32_t)entry_point; + handoff->ramstage_entry_point = (uint32_t)prog_entry(ramstage); - memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage), - ramstage_size); + memcpy(cbmem_entry_start(entry), prog_start(ramstage), ramstage_size); } -void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) +void load_cached_ramstage(struct romstage_handoff *handoff, + struct prog *ramstage) { const struct cbmem_entry *entry_cache; + const struct cbmem_entry *entry_dest; if (handoff == NULL) - return NULL; + return; entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE); if (entry_cache == NULL) - return NULL; + return; - /* Load the cached ramstage copy into the to-be-run region. */ - memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache), - cbmem_entry_size(ramstage)); + entry_dest = cbmem_entry_find(CBMEM_ID_RAMSTAGE); + + if (entry_dest == NULL) + return; - return (void *)handoff->ramstage_entry_point; + prog_set_area(ramstage, cbmem_entry_start(entry_dest), + cbmem_entry_size(entry_dest)); + prog_set_entry(ramstage, (void *)handoff->ramstage_entry_point, NULL); + + /* Load the cached ramstage copy into the to-be-run region. */ + memcpy(prog_start(ramstage), cbmem_entry_start(entry_cache), + prog_size(ramstage)); } #endif diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index b29a34e..164dce9 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -220,7 +220,7 @@ static int build_self_segment_list( struct segment *ptr; struct cbfs_payload_segment *segment, *first_segment; struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + cbfs_payload = prog_start(&payload->prog); memset(head, 0, sizeof(*head)); head->next = head->prev = head; first_segment = segment = &cbfs_payload->segments;

1 0

Patch set updated for coreboot: 38e9b71 program loading: add prog_run() function
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8846 -gerrit commit 38e9b71ea4876194472e7925dd19aa44c1efce07 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 15:55:08 2015 -0500 program loading: add prog_run() function The prog_run() function abstracts away what is required for running a given program. Within it, there are 2 calls: 1. platform_prog_run() and 2. arch_prog_run(). The platform_prog_run() allows for a chipset to intercept a program that will be run. This allows for CPU switching as currently needed in t124 and t132. Change-Id: I22a5dd5bfb1018e7e46475e47ac993a0941e2a8c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/Makefile.inc | 2 ++ src/arch/arm/boot.c | 11 +++++++--- src/arch/arm64/Makefile.inc | 2 ++ src/arch/arm64/boot.c | 27 ++++++++++++++++++++--- src/arch/mips/boot.c | 9 ++++++-- src/arch/riscv/Makefile.inc | 2 ++ src/arch/riscv/boot.c | 14 ++++++++---- src/arch/x86/boot/Makefile.inc | 1 + src/arch/x86/boot/boot.c | 10 ++++++++- src/include/program_loading.h | 12 +++++++++- src/lib/Makefile.inc | 8 +++---- src/lib/arch_ops.c | 28 ----------------------- src/lib/loaders/load_and_run_payload.c | 2 +- src/lib/loaders/load_and_run_ramstage.c | 4 ++-- src/lib/loaders/load_and_run_romstage.c | 2 +- src/lib/prog_ops.c | 39 +++++++++++++++++++++++++++++++++ 16 files changed, 123 insertions(+), 50 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index e739d0b..ffbc841 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -54,6 +54,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) bootblock-y += id.S $(obj)/arch/arm/id.bootblock.o: $(obj)/build.h +bootblock-y += boot.c bootblock-y += stages.c bootblock-y += eabi_compat.c bootblock-y += memset.S @@ -89,6 +90,7 @@ verstage-y += stages.c ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) +romstage-y += boot.c romstage-y += stages.c romstage-y += div0.c romstage-y += eabi_compat.c diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 9dc6dbd..6a2934b 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -20,12 +20,17 @@ #include <arch/cache.h> #include <program_loading.h> -void arch_payload_run(const struct payload *payload) +void arch_prog_run(struct prog *prog) { void (*doit)(void *); cache_sync_instructions(); - doit = prog_entry(&payload->prog); - doit(prog_entry_arg(&payload->prog)); + doit = prog_entry(prog); + doit(prog_entry_arg(prog)); +} + +void arch_payload_run(struct payload *payload) +{ + arch_prog_run(&payload->prog); } diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6d23dab..c1f1112 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -57,6 +57,7 @@ bootblock-y += div0.c bootblock-y += id.S $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h +bootblock-y += boot.c bootblock-y += c_entry.c bootblock-y += stage_entry.S bootblock-y += stages.c @@ -81,6 +82,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) +romstage-y += boot.c romstage-y += c_entry.c romstage-y += stage_entry.S romstage-y += stages.c diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 74282a9..b5e3751 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -25,15 +25,16 @@ #include <arch/transition.h> #include <console/console.h> #include <program_loading.h> +#include <rules.h> #include <string.h> -void arch_payload_run(const struct payload *payload) +static void run_payload(struct prog *prog) { void (*doit)(void *); void *arg; - doit = prog_entry(&payload->prog); - arg = prog_entry_arg(&payload->prog); + doit = prog_entry(prog); + arg = prog_entry_arg(prog); uint8_t current_el = get_current_el(); @@ -61,3 +62,23 @@ void arch_payload_run(const struct payload *payload) cache_sync_instructions(); transition_with_entry(doit, arg, &exc_state); } + +void arch_prog_run(struct prog *prog) +{ + void (*doit)(void *); + void *arg; + + if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) + run_payload(prog); + return; + + doit = prog_entry(prog); + arg = prog_entry_arg(prog); + + doit(prog_entry_arg(prog)); +} + +void arch_payload_run(struct payload *payload) +{ + arch_prog_run(&payload->prog); +} diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index 6e12d10..ebc45bb 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -20,7 +20,12 @@ #include <arch/stages.h> #include <program_loading.h> -void arch_payload_run(const struct payload *payload) +void arch_prog_run(struct prog *prog) { - stage_exit(prog_entry(&payload->prog)); + stage_exit(prog_entry(prog)); +} + +void arch_payload_run(struct payload *payload) +{ + arch_prog_run(&payload->prog); } diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 242fd40..30c84a9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock_lds = $(src)/arch/riscv/bootblock.ld bootblock-y = bootblock.S stages.c +bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ $(top)/src/lib/memchr.c \ @@ -52,6 +53,7 @@ endif ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) +romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c romstage-y += \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 4c2be03..f66c02f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -17,11 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/stages.h> #include <program_loading.h> -void arch_payload_run(const struct payload *payload) +void arch_prog_run(struct prog *prog) { -// uart_rx_byte(0); - stage_exit(prog_entry(&payload->prog)); + void (*doit)(void *); + + doit = prog_entry(prog); + doit(prog_entry_arg(prog)); +} + +void arch_payload_run(struct payload *payload) +{ + arch_prog_run(&payload->prog); } diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9f06b4f..7810ba8 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) romstage-y += cbmem.c +romstage-y += boot.c endif # CONFIG_ARCH_ROMSTAGE_X86_32 diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 1fb36e2..d536584 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -123,7 +123,7 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) ); } -void arch_payload_run(const struct payload *payload) +void arch_payload_run(struct payload *payload) { if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) jmp_payload_no_bounce_buffer(prog_entry(&payload->prog)); @@ -132,3 +132,11 @@ void arch_payload_run(const struct payload *payload) (uintptr_t)payload->bounce.data, payload->bounce.size); } + +void arch_prog_run(struct prog *prog) +{ + __asm__ volatile ( + "jmp *%%edi\n" + :: "D"(prog_entry(prog)) + ); +} diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 38047c7..1df1825 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -90,6 +90,16 @@ static inline void prog_set_entry(struct prog *prog, void *e, void *arg) prog->arg = arg; } +/* Run the program described by prog. */ +void prog_run(struct prog *prog); +/* Per architecture implementation running a program. */ +void arch_prog_run(struct prog *prog); +/* Platform (SoC/chipset) specific overrides for running a program. This is + * called prior to calling the arch_prog_run. Thus, if there is anything + * special that needs to be done by the platform similar to the architecture + * code it needs to that as well. */ +void platform_prog_run(struct prog *prog); + /************************ * ROMSTAGE LOADING * ************************/ @@ -143,7 +153,7 @@ void payload_run(void); void mirror_payload(struct payload *payload); /* architecture specific function to run payload. */ -void arch_payload_run(const struct payload *payload); +void arch_payload_run(struct payload *payload); /* Payload loading operations. */ struct payload_loader_ops { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 67cf577..5f149c9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -18,7 +18,7 @@ # subdirs-y += loaders -bootblock-y += arch_ops.c +bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c @@ -26,7 +26,7 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c -verstage-y += arch_ops.c +verstage-y += prog_ops.c verstage-y += delay.c verstage-y += cbfs.c verstage-y += memcmp.c @@ -35,7 +35,7 @@ verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c verstage-y += tlcl.c verstage-$(CONFIG_GENERIC_UDELAY) += timer.c -romstage-y += arch_ops.c +romstage-y += prog_ops.c romstage-y += memchr.c romstage-y += memcmp.c $(foreach arch,$(ARCH_SUPPORTED),\ @@ -60,7 +60,7 @@ romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif -ramstage-y += arch_ops.c +ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c ramstage-y += coreboot_table.c diff --git a/src/lib/arch_ops.c b/src/lib/arch_ops.c deleted file mode 100644 index ac1be77..0000000 --- a/src/lib/arch_ops.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <program_loading.h> - -/* For each segment of a program loaded this function is called*/ -void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, - int flags) -{ - /* do nothing */ -} diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 8e745c9..e3208a9 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -83,7 +83,7 @@ out: void payload_run(void) { - const struct payload *payload = &global_payload; + struct payload *payload = &global_payload; /* Reset to booting from this image as late as possible */ boot_successful(); diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 82bc1e0..9067a28 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -48,7 +48,7 @@ load_ramstage(const struct ramstage_loader_ops *ops, timestamp_add_now(TS_END_COPYRAM); - stage_exit(prog_entry(ramstage)); + prog_run(ramstage); } static void run_ramstage_from_resume(struct romstage_handoff *handoff, @@ -60,7 +60,7 @@ static void run_ramstage_from_resume(struct romstage_handoff *handoff, if (prog_entry(ramstage) != NULL) { printk(BIOS_DEBUG, "Jumping to image.\n"); - stage_exit(prog_entry(ramstage)); + prog_run(ramstage); } } } diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index 3ad9176..8467e90 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -38,5 +38,5 @@ void run_romstage(void) halt(); } - stage_exit(prog_entry(&romstage)); + prog_run(&romstage); } diff --git a/src/lib/prog_ops.c b/src/lib/prog_ops.c new file mode 100644 index 0000000..755b135 --- /dev/null +++ b/src/lib/prog_ops.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <program_loading.h> + +/* For each segment of a program loaded this function is called*/ +void __attribute__ ((weak)) arch_segment_loaded(uintptr_t start, size_t size, + int flags) +{ + /* do nothing */ +} + +void prog_run(struct prog *prog) +{ + platform_prog_run(prog); + arch_prog_run(prog); +} + +void __attribute__ ((weak)) platform_prog_run(struct prog *prog) +{ + /* do nothing */ +}

1 0

Patch set updated for coreboot: 58533c7 tegra124: implement platform_prog_run()
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8847 -gerrit commit 58533c76e071e4696454c58964d544c6be46d99c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 20 16:42:17 2015 -0500 tegra124: implement platform_prog_run() The tegra124 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting bootblock it runs romstage from its faster armv7 core. Instead of hard coding the stage loading operations use run_romstage(). Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra124/bootblock.c | 39 ++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index f08ca41..1ccc394 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -22,16 +22,30 @@ #include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> +#include <program_loading.h> #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> #include <vendorcode/google/chromeos/chromeos.h> #include "pinmux.h" #include "power.h" -void main(void) +static void run_next_stage(void *entry) { - void *entry; + ASSERT(entry); + clock_cpu0_config(entry); + + power_enable_and_ungate_cpu(); + + /* Repair ram on cluster0 and cluster1 after CPU is powered on. */ + ram_repair(); + + clock_cpu0_remove_reset(); + clock_halt_avp(); +} + +void main(void) +{ // enable pinmux clamp inputs clamp_tristate_inputs(); @@ -70,21 +84,10 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); - if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) - entry = NULL; - else - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - - ASSERT(entry); - clock_cpu0_config(entry); - - power_enable_and_ungate_cpu(); - - /* Repair ram on cluster0 and cluster1 after CPU is powered on. */ - ram_repair(); - - clock_cpu0_remove_reset(); + run_romstage(); +} - clock_halt_avp(); +void platform_prog_run(struct prog *prog) +{ + run_next_stage(prog_entry(prog)); }

1 0

Patch merged into coreboot/master: d9f9507 broadwell: Disable ADSP power gating feature by default
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit d9f95070650675599e0c1dee67f0b0074eced678 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 1 13:47:20 2014 -0700 broadwell: Disable ADSP power gating feature by default Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable. BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9218 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9218 for details. -gerrit

1 0

Patch merged into coreboot/master: 767d245 chromeec: Add wakeup delay after SPI /CS assertion
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 767d245ebf2d6d797bf759d23778553ed6f2a0b2 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Sep 27 20:04:49 2014 -0700 chromeec: Add wakeup delay after SPI /CS assertion Some ECs may require a few microseconds to ramp up their clock after being awaken by /CS assertion. This adds a Kconfig variable that can be overridden at the mainboard-level which will force a delay between asserting /CS and beginning a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585 Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220242 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9217 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/9217 for details. -gerrit

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Patch merged into coreboot/master: 8429786 samus: Fix codec interrupt and add GPIO defines
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 842978631580333becf635cc78f1901615d34929 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 09:30:36 2014 -0700 samus: Fix codec interrupt and add GPIO defines The codec interrupt needs to come from codec GPIO1, so use the HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The This means codec interrupt is GPIO46 which is PIRQO and should be interrupt 30. Also add GPIO defines for the GPIOs attached to the codec itself. These are defined by index, and I used the same "jack detect" and "mic present" indices that were used in baytrail. The codec interrupt to the host is added at index 2 and the hostword detect interrupt to the host is added at index 3. These can be changed as we work through the implementation in the kernel driver. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706 Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220326 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9216 for details. -gerrit

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Patch merged into coreboot/master: b12e9be chromeec: Fix logging of EC wake events
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit b12e9becfe47f8f02046274181ce8bae122ab58a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 13:04:06 2014 -0700 chromeec: Fix logging of EC wake events The EC behavior for reading events from the ACPI interface was broken with this commit: d899fda lpc: ACPI query-next-event drops masked events https://chromium-review.googlesource.com/194935 This is causing no EC wake events to be logged. To make sure they are logged once again set the wake mask before querying for events. Also remove the check for port80 event logging since this is no longer used as we now store the port80 code in CMOS and this is unnecessary commands to do for the resume path. BUG=chrome-os-partner:32462 BRANCH=samus,auron TEST=build and boot on samus, check for EC wake events for keyboard and lid in the event log. Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7 Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220373 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9215 for details. -gerrit

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Patch merged into coreboot/master: 3b6a88e samus: Clean up touch wake sources
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 3b6a88ed7e49a71be5399755aa2640985547d34b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 09:27:13 2014 -0700 samus: Clean up touch wake sources Move _PRW to the ACPI devices for the touchpad and touchscreen. Add a _DSW method, but disable it by default for now until a spurious wake issue can be resolved. BUG=chrome-os-partner:32232 BRANCH=samus TEST=build and boot on samus, ensure trackpad does not spuriously wake the system. Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220325 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9214 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9214 for details. -gerrit

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Patch merged into coreboot/master: cdcc9a4 broadwell: Add event log entry for GPIO27
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit cdcc9a4635ab8f5f40a143d5d297418206a412ee Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:38:04 2014 -0700 broadwell: Add event log entry for GPIO27 Add event log entry if GPIO27 is used to wake the system. This GPIO is treated separately from other GPE and it is one of the only events that can wake from Deep Sx. BUG=chrome-os-partner:31549 BRANCH=samus TEST=samus: suspend/resume and wake from keypress, check for GPIO27 event in event log. Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95 Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220323 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9213 for details. -gerrit

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Patch merged into coreboot/master: 635ee51 arm: Prevent compilation of old, experimental SMP support
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 635ee51b0d5cffc155e09fbbe644c2914ce54b6a Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 23 20:53:20 2014 -0700 arm: Prevent compilation of old, experimental SMP support The ARM SMP feature was added a long time ago and has never really been used by anyone since. We are still always compiling cpu_info() even though we don't use it, and it makes some dangerous assumptions about stack alignment that are not guaranteed anywhere. I'm planning to change the way the stack boundaries are defined. Rather than trying to work that into this unsafe, unused and hard to test feature, I think we should just seal it off with police tape and make sure that if anyone ever tries to use it again (which currently seems unlikely), they get forced to do their due diligence on making sure it works as intended. BUG=None TEST=Compiled Veyron_Pinky. Change-Id: Id25545cab88f29200c7672ef02c7804f0ac26399 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 5b517fc46b030a6e50ef2f5e4d4a449b98ce16c6 Original-Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219680 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/9222 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9222 for details. -gerrit

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coreboot-gerrit April 2015