coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: af9cbaa Broadwell: Reg_Script: add END tag to array "smbus_init_script"
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit af9cbaa1827f796fff13c5d73351454ea683fc34 Author: Ryan Lin <ryan.lin(a)intel.com> Date: Wed Oct 1 15:53:39 2014 -0700 Broadwell: Reg_Script: add END tag to array "smbus_init_script" Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script. BUG=chromium:416651 TEST=test on Auron. Change-Id: Ieeaf6c705aa673acc9bb2635e103c4148bc8742f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 172c5fc259a2f6d09daccb1fe53fe0aa7c5601e1 Original-Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e Original-Signed-off-by: Ryan Lin <ryan.lin(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220934 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com> Reviewed-on: http://review.coreboot.org/9221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9221 for details. -gerrit

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Patch merged into coreboot/master: 1247b87 samus: Fix and clean up GPIOs and EC info/events
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 1247b8734d20f623a9d6fc7ee62e77920b096d37 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:35:29 2014 -0700 samus: Fix and clean up GPIOs and EC info/events - Define specific GPIOs in gpio.h instaed of smihandler.c - Add battery status event to SCI list - Remove old proto board version defines and SPD index usage - Do not disable cmd_pwr training now that it works on EVT board BUG=chrome-os-partner:32196,chrome-os-partner:29117 BRANCH=samus TEST=build and boot on samus Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220321 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9220 for details. -gerrit

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Patch merged into coreboot/master: d840118 chromeec: Add battery status event and re-enable _BIX
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit d840118ef59bdd0f89c989c0c1d43d32e13ce9d1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:32:19 2014 -0700 chromeec: Add battery status event and re-enable _BIX Add a new host event to send a notify(0x80) to the battery when the EC indicates that battery status has changed. The kernel has fixed the bug with _BIX method so it can be enabled now. BUG=chrome-os-partner:32196 BRANCH=samus TEST=build and boot on samus Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2 Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220320 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9212 for details. -gerrit

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Patch merged into coreboot/master: e383feb Broadwell: Synchronize for power management with FRC
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit e383feb7c8e1b46639c32df9a11fac6cf3d62403 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 03:14:57 2014 +0800 Broadwell: Synchronize for power management with FRC Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build an image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Reviewed-on: http://review.coreboot.org/9211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9211 for details. -gerrit

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Patch merged into coreboot/master: c373f50 Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit c373f503dbbfc2a70e91f576fac01f66126556c2 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Sep 26 02:48:16 2014 +0800 Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC OBFF: Disable it by clearing bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommended setting. BUG=None TEST=Build an image and check the setting are applied correctly on Samus. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Reviewed-on: http://review.coreboot.org/9210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9210 for details. -gerrit

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Patch merged into coreboot/master: 8ef55ee Broadwell: Revise programming flow for write-once registers
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 8ef55ee9969de3003eae9e3113b7497799ba14ec Author: Kenji Chen <kenji.chen(a)intel.com> Date: Thu Sep 25 21:34:42 2014 +0800 Broadwell: Revise programming flow for write-once registers Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9 Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 Reviewed-on: http://review.coreboot.org/9209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9209 for details. -gerrit

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Patch merged into coreboot/master: 87d4a20 broadwell: Configure IOSF Port and Grant Count
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 87d4a201aba0cb1c422546a42fdc7e9b10c61fdb Author: Kenji Chen <kenji.chen(a)intel.com> Date: Wed Sep 24 01:18:26 2014 +0800 broadwell: Configure IOSF Port and Grant Count Synchronize the code with FRC. Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreboot image and run on Samus to confirm the setting is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9208 for details. -gerrit

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Patch merged into coreboot/master: 274ef41 vpd: retrieve mac addresses and pass them to bootloader
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 274ef4186ff7120309ac89343e35ba57608d0f4d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 22 18:48:41 2014 -0700 vpd: retrieve mac addresses and pass them to bootloader Chrome OS devices firmware usually includes an area called VPD (Vital Product Data). VPD is a blob of a certain structure, in particular containing freely defined variable size fields. A field is a tuple of the field name and field contents. MAC addresses of the interfaces are stored in VPD as well. Field names are in the form of 'ethernet_macN', where N is the zero based interface number. This patch retrieves the MAC address(es) from the VPD and populates them in the coreboot table so that they become available to the bootloader. BUG=chrome-os-partner:32152, chromium:417117 TEST=with this and other patches in place the storm device tree shows up with MAC addresses properly initialized. Change-Id: I955207b3a644cde100cc4b48e51a2ab9a3cb1ba0 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 1972b9e97b57cc8503c5e4dc496706970ed2ffbe Original-Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219443 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9207 for details. -gerrit

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Patch merged into coreboot/master: 074a028 Samus: Synchronization with FRC to enable PCIe Relaxed Order.
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 074a028ef715763ecda99386d472c751092150a1 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Sat Sep 20 01:39:20 2014 +0800 Samus: Synchronization with FRC to enable PCIe Relaxed Order. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 Reviewed-on: http://review.coreboot.org/9206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9206 for details. -gerrit

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Patch merged into coreboot/master: f6d7baa samus: Ensure PD controller is in RO mode for recovery
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit f6d7baa8fa31a87e4a6f47fc3da82fc093f114a3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:56:04 2014 -0700 samus: Ensure PD controller is in RO mode for recovery In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9205 for details. -gerrit

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coreboot-gerrit April 2015