coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 60e6bf8 chromeec: Add support for v3 commands on LPC
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 60e6bf80dbad367250b19374e8b9d155cdb3fe90 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:51:07 2014 -0700 chromeec: Add support for v3 commands on LPC In order to talk to the PD controller with a passthru command coreboot needs to be able to use v3 commands. The command version is automatically detected based on the advertized flags from the EC. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot on samus EVT Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218902 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9203 for details. -gerrit

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Patch merged into coreboot/master: fc0f517 chromeec: Add commands to check PD image type
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit fc0f5175fbf8a60dbc1894484c69d8da246dd671 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:54:02 2014 -0700 chromeec: Add commands to check PD image type Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9204 for details. -gerrit

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Patch merged into coreboot/master: 8caa80b chromeec: Update ec_commands.h from EC repository
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 8caa80b84feb421e2e08671d43bb9a8218ad8fa9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 18 12:48:06 2014 -0700 chromeec: Update ec_commands.h from EC repository This latest version includes PD passthru support. BUG=chrome-os-partner:30079 BRANCH=None TEST=build and boot on samus Change-Id: Ie718b73a6b125a863ae28e63769dd54edc267f0b Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: fbca0743a4b45828a466d05afc3a2e94d2e3da2e Original-Change-Id: I79d160219564155008f6231fec35808d1fbd6f04 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218901 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9202 for details. -gerrit

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Patch merged into coreboot/master: c9bf446 baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit c9bf446ee93fb2334117b97e8ed94b8f78e6856d Author: Kein Yuan <kein.yuan(a)intel.com> Date: Fri Jun 27 09:12:57 2014 -0700 baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 Reviewed-on: http://review.coreboot.org/9200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9200 for details. -gerrit

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Patch merged into coreboot/master: 642e598 broadwell: Update PCIe configuration to follow BWG
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 642e598102a48a5ffd76aae0d21795881a56c6d8 Author: Kane Chen <kane.chen(a)intel.com> Date: Tue Sep 9 15:53:09 2014 -0700 broadwell: Update PCIe configuration to follow BWG According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9197 for details. -gerrit

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Patch set updated for coreboot: 0ff650e chromeec: Add wakeup delay after SPI /CS assertion
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9217 -gerrit commit 0ff650e8644c1987f58e848d017a4e133e2450a3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Sep 27 20:04:49 2014 -0700 chromeec: Add wakeup delay after SPI /CS assertion Some ECs may require a few microseconds to ramp up their clock after being awaken by /CS assertion. This adds a Kconfig variable that can be overridden at the mainboard-level which will force a delay between asserting /CS and beginning a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585 Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220242 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 7 +++++++ src/ec/google/chromeec/ec_spi.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index bec12fb..32a4213 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -43,6 +43,13 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS depends on EC_GOOGLE_CHROMEEC_SPI hex "SPI bus for Google's Chrome EC" +config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US + depends on EC_GOOGLE_CHROMEEC_SPI + int + default 0 + help + Force delay after asserting /CS to allow EC to wakeup. + config EC_GOOGLE_CHROMEEC_SPI_CHIP depends on EC_GOOGLE_CHROMEEC_SPI hex diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 4b3e587..d11348c 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <delay.h> #include "ec.h" #include "ec_commands.h" #include <spi-generic.h> @@ -50,6 +51,10 @@ static int crosec_spi_io(size_t req_size, size_t resp_size, void *context) spi_claim_bus(slave); + /* Allow EC to ramp up clock after being awaken. + * See chrome-os-partner:32223 for more details. */ + udelay(CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US); + if (spi_xfer(slave, req_buf, req_size, NULL, 0)) { printk(BIOS_ERR, "%s: Failed to send request.\n", __func__); spi_release_bus(slave);

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Patch set updated for coreboot: 0cd4d87 samus: Fix codec interrupt and add GPIO defines
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9216 -gerrit commit 0cd4d8729bb75a732cda08d7c8a190ad587fc90c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 09:30:36 2014 -0700 samus: Fix codec interrupt and add GPIO defines The codec interrupt needs to come from codec GPIO1, so use the HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The This means codec interrupt is GPIO46 which is PIRQO and should be interrupt 30. Also add GPIO defines for the GPIOs attached to the codec itself. These are defined by index, and I used the same "jack detect" and "mic present" indices that were used in baytrail. The codec interrupt to the host is added at index 2 and the hostword detect interrupt to the host is added at index 3. These can be changed as we work through the implementation in the kernel driver. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706 Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220326 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 57 +++++++++++++++++---------- src/mainboard/google/samus/gpio.h | 4 +- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 6a2cb97..2bb34fd 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -169,6 +169,8 @@ Scope (\_SB.PCI0.I2C0) Name (_HID, "RT5677CE") Name (_DDN, "RT5667 Codec") Name (_UID, 1) + Name (WAKE, 45) /* DSP_INT (use as codec wake) */ + Name (_CRS, ResourceTemplate() { I2cSerialBus ( @@ -178,38 +180,53 @@ Scope (\_SB.PCI0.I2C0) AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0", // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow){ 30 } - }) - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - Device (HOTW) - { - Name (_HID, "PNP0A05") - Name (_DDN, "Hotword Wake") - Name (_UID, 1) - Name (GPIO, 46) /* HOTWORD_DET_L_3V3 */ + /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */ + Interrupt (ResourceConsumer, Edge, ActiveLow) { 30 } + + /* + * Codec GPIOs are 1-based in the schematic + * + * [0] = Jack Detect (INPUT) + * [1] = Mic Present (INPUT) + * [2] = Interrupt to the host (OUTPUT) + * [3] = Interrupt to the host (OUTPUT) + */ + + /* Index 0: Jack Detect - PLUG_DET is GPIO5 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, + "\\_SB.PCI0.I2C0.CODC") { 4 } + + /* Index 1: Mic Present - MIC_PRESENT_L is GPIO6 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, + "\\_SB.PCI0.I2C0.CODC") { 5 } + + /* Index 2: Codec IRQ - HOTWORD_DET_L is GPIO1 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 0 } + + /* Index 3: Codec Wake - DSP_INT is GPIO4 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 3 } + }) - Name (_PRW, Package() { GPIO, 3 }) + Name (_PRW, Package() { WAKE, 3 }) Method (_DSW, 3, NotSerialized) { If (LEqual (Arg0, 1)) { // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) + \_SB.PCI0.LPCB.GPIO.GWAK (^WAKE) } } Method (_STA) { - Return (0xF) + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } } } } diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index f293dee..393a14f 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -73,8 +73,8 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 42: WLAN_DISABLE_L */ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ PCH_GPIO_UNUSED, /* 44: UNUSED */ - PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */ - PCH_GPIO_ACPI_SCI, /* 46: HOTWORD_DET_L_3V3 (WAKE) */ + PCH_GPIO_ACPI_SCI, /* 45: DSP_INT - Codec Wake */ + PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */ PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */ PCH_GPIO_UNUSED, /* 48: UNUSED */ PCH_GPIO_UNUSED, /* 49: UNUSED */

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Patch set updated for coreboot: e0eeb06 broadwell: Disable ADSP power gating feature by default
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9218 -gerrit commit e0eeb06f0939191c73046120b921774e77eb7db6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 1 13:47:20 2014 -0700 broadwell: Disable ADSP power gating feature by default Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable. BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/adsp.c | 26 +++++++++++++++----------- src/soc/intel/broadwell/chip.h | 5 +++-- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 9ecbe95..bf77763 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -69,21 +69,25 @@ static void adsp_init(struct device *dev) /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); - if (config->adsp_d3_pg_disable) { - if (pch_is_wpt()) { - tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; - tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; + if (pch_is_wpt()) { + if (config->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; + if (config->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; } else { - tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; - tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; } } else { - if (pch_is_wpt()) { - tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; - tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; - } else { + if (config->adsp_d3_pg_enable) { tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; - tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + if (config->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; } } pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 005ab36..703c865 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -84,8 +84,9 @@ struct soc_intel_broadwell_config { uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; - /* Disable ADSP power gating in D3 */ - uint8_t adsp_d3_pg_disable; + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; /* * Clock Disable Map:

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Patch set updated for coreboot: df33b40 broadwell: Add event log entry for GPIO27
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9213 -gerrit commit df33b400a5bda1b3342cbd9f7979124a49794b58 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 08:38:04 2014 -0700 broadwell: Add event log entry for GPIO27 Add event log entry if GPIO27 is used to wake the system. This GPIO is treated separately from other GPE and it is one of the only events that can wake from Deep Sx. BUG=chrome-os-partner:31549 BRANCH=samus TEST=samus: suspend/resume and wake from keypress, check for GPIO27 event in event log. Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95 Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220323 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/elog.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index bb7e7ba..30f64e0 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -63,6 +63,10 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + /* GPIO27 */ + if (ps->gpe0_sts[GPE_STD] & GP27_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); + /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);

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Patch set updated for coreboot: 4f44291 chromeec: Fix logging of EC wake events
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9215 -gerrit commit 4f44291b7e69e99375912f373abd3b308e27f7fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 29 13:04:06 2014 -0700 chromeec: Fix logging of EC wake events The EC behavior for reading events from the ACPI interface was broken with this commit: d899fda lpc: ACPI query-next-event drops masked events https://chromium-review.googlesource.com/194935 This is causing no EC wake events to be logged. To make sure they are logged once again set the wake mask before querying for events. Also remove the check for port80 event logging since this is no longer used as we now store the port80 code in CMOS and this is unnecessary commands to do for the resume path. BUG=chrome-os-partner:32462 BRANCH=samus,auron TEST=build and boot on samus, check for EC wake events for keyboard and lid in the event log. Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7 Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220373 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/ec.c | 33 ++++++--------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a329b5d..83c22d3 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -379,43 +379,22 @@ u32 google_chromeec_get_wake_mask(void) EC_CMD_HOST_EVENT_GET_WAKE_MASK); } -#if CONFIG_ELOG -/* Find the last port80 code from the previous boot */ -static u16 google_chromeec_get_port80_last_boot(void) -{ - struct ec_response_port80_last_boot rsp; - struct chromeec_command cmd = { - .cmd_code = EC_CMD_PORT80_LAST_BOOT, - .cmd_data_out = &rsp, - .cmd_size_out = sizeof(rsp), - }; - - /* Get last port80 code */ - if (google_chromeec_command(&cmd) == 0) - return rsp.code; - - return 0; -} -#endif - void google_chromeec_log_events(u32 mask) { #if CONFIG_ELOG u8 event; - u16 code; - - /* Find the last port80 code */ - code = google_chromeec_get_port80_last_boot(); + u32 wake_mask; - /* Log the last post code only if it is abornmal */ - if (code > 0 && code != POST_OS_BOOT && code != POST_OS_RESUME) - printk(BIOS_DEBUG, "Chrome EC: Last POST code was 0x%02x\n", - code); + /* Set wake mask so events will be read from ACPI interface */ + wake_mask = google_chromeec_get_wake_mask(); + google_chromeec_set_wake_mask(mask); while ((event = google_chromeec_get_event()) != 0) { if (EC_HOST_EVENT_MASK(event) & mask) elog_add_event_byte(ELOG_TYPE_EC_EVENT, event); } + + google_chromeec_set_wake_mask(wake_mask); #endif }

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coreboot-gerrit April 2015