coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 1fd5a9b pinky: Force delay for EC SPI transfers
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 1fd5a9b36d8b817614ef7f0c301291da0cdb7466 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Sep 27 20:10:41 2014 -0700 pinky: Force delay for EC SPI transfers This gives the EC some time to wake-up between asserting /CS and starting a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer on Pinky Original-Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220243 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Commit-Queue: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Change-Id: I103542517d3ebd7da4f0394b3ae4f68f58403b1e (cherry picked from commit bdb67fe489b7cbea7a26492fa0536ca452434052) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9238 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9238 for details. -gerrit

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New patch to review for coreboot: 7878884 rockchip: support i2c clock setting
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9241 -gerrit commit 78788849fe5f7fddbde001339ffcf8b34553be14 Author: huang lin <hl(a)rock-chips.com> Date: Sat Sep 27 12:02:27 2014 +0800 rockchip: support i2c clock setting BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/mainboard.c | 3 +++ src/soc/rockchip/rk3288/Makefile.inc | 1 + src/soc/rockchip/rk3288/bootblock.c | 5 ++++ src/soc/rockchip/rk3288/clock.c | 2 +- src/soc/rockchip/rk3288/clock.h | 1 - src/soc/rockchip/rk3288/i2c.c | 39 +++++++++++++++++++++++++++ src/soc/rockchip/rk3288/i2c.h | 26 ++++++++++++++++++ 7 files changed, 75 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 22c9b0e..232010d 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -31,6 +31,7 @@ #include <soc/rockchip/rk3288/clock.h> #include <soc/rockchip/rk3288/rk808.h> #include <soc/rockchip/rk3288/spi.h> +#include <soc/rockchip/rk3288/i2c.h> #include "board.h" @@ -81,6 +82,7 @@ static void configure_emmc(void) static void configure_codec(void) { writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */ + i2c_init(2, 400000); /* CODEC I2C */ writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); @@ -124,6 +126,7 @@ static void mainboard_init(device_t dev) { setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */ setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */ + i2c_init(0, 400000); /* PMIC I2C */ gpio_output(GPIO_RESET, 0); diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 37abe57..95d72c9 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -30,6 +30,7 @@ bootblock-y += clock.c bootblock-y += spi.c bootblock-y += media.c bootblock-y += gpio.c +bootblock-y += i2c.c verstage-y += monotonic_timer.c verstage-y += spi.c diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 635eee4..d7bc67a 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,6 +26,7 @@ #include "grf.h" #include "spi.h" #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/rockchip/rk3288/i2c.h> static void bootblock_cpu_init(void) { @@ -34,11 +35,15 @@ static void bootblock_cpu_init(void) writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); /*i2c1 for tpm*/ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); rk3288_init_timer(); console_init(); rkclk_init(); + + /*i2c1 for tpm 400khz*/ + i2c_init(1, 400000); rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); setup_chromeos_gpios(); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index d106245..8202ef2 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -157,8 +157,8 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); * aclk_periph = * periph_clk_src / (peri_aclk_div_con + 1) */ +#define PERI_ACLK_DIV_SHIFT (0x0) #define PERI_ACLK_DIV_MSK (0x1F) -#define PERI_ACLK_DIV_SHIFT (0) /*******************CLKSEL37 BITS***************************/ #define L2_DIV_MSK (0x7) diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index c28d181..b206baa 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -40,5 +40,4 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_i2s(unsigned int hz); - #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c index 9348b6c..142ec4a 100644 --- a/src/soc/rockchip/rk3288/i2c.c +++ b/src/soc/rockchip/rk3288/i2c.c @@ -30,6 +30,9 @@ #include "addressmap.h" #include "grf.h" #include "soc.h" +#include "i2c.h" +#include "clock.h" + #define RETRY_COUNT 3 /* 100000us = 100ms */ #define I2C_TIMEOUT_US 100000 @@ -275,3 +278,39 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) } return res; } + +void i2c_init(unsigned int bus, unsigned int hz) +{ + unsigned int clk_div; + unsigned int divl; + unsigned int divh; + unsigned int i2c_src_clk; + struct rk3288_i2c_regs *regs = i2c_bus[bus]; + + /*i2c0,i2c2 src clk from pd_bus_pclk + other i2c src clk from peri_pclk + */ + switch (bus) { + case 0: + case 2: + i2c_src_clk = PD_BUS_PCLK_HZ; + break; + case 1: + case 3: + case 4: + case 5: + i2c_src_clk = PERI_PCLK_HZ; + break; + default: + break; + } + + /*SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1) + SCL = PCLK/ SCLK Divisor + */ + clk_div = div_round_up(i2c_src_clk, hz * 8) - 2; + divh = clk_div / 2; + divl = ALIGN_UP(clk_div, 2) / 2; + assert((divh < 65536) && (divl < 65536)); + writel((divh << 16) | (divl << 0), &regs->i2c_clkdiv); +} diff --git a/src/soc/rockchip/rk3288/i2c.h b/src/soc/rockchip/rk3288/i2c.h new file mode 100644 index 0000000..84d9b75 --- /dev/null +++ b/src/soc/rockchip/rk3288/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__ +#define __SOC_ROCKCHIP_RK3288_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif +

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New patch to review for coreboot: 61c06e8 rockchip: support pwm regulator
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9240 -gerrit commit 61c06e88ff4ee590f24756cf85d2145dffb5f088 Author: huang lin <hl(a)rock-chips.com> Date: Thu Sep 25 16:33:38 2014 +0800 rockchip: support pwm regulator BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/romstage.c | 23 +++++++ src/soc/rockchip/rk3288/Makefile.inc | 2 + src/soc/rockchip/rk3288/clock.c | 95 ++++++++++++++++++++++++++-- src/soc/rockchip/rk3288/clock.h | 8 +++ src/soc/rockchip/rk3288/grf.h | 2 + src/soc/rockchip/rk3288/pwm.c | 90 ++++++++++++++++++++++++++ src/soc/rockchip/rk3288/pwm.h | 26 ++++++++ 7 files changed, 240 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 31317a0..f972ee2 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -28,11 +28,32 @@ #include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> +#include <stdlib.h> +#include <assert.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/rockchip/rk3288/sdram.h> #include <soc/rockchip/rk3288/clock.h> +#include <soc/rockchip/rk3288/pwm.h> +#include <soc/rockchip/rk3288/grf.h> #include "timer.h" +static void regulate_vdd_log(unsigned int mv) +{ + unsigned int duty_ns; + const u32 period_ns = 2000; /* pwm period: 2000ns */ + const u32 max_regulator_mv = 1350; /* 1.35V */ + const u32 min_regulator_mv = 870; /* 0.87V */ + + writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1); + + assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); + + duty_ns = (max_regulator_mv - mv) * period_ns / + (max_regulator_mv - min_regulator_mv); + + pwm_init(1, period_ns, duty_ns); +} + void main(void) { #if CONFIG_COLLECT_TIMESTAMPS @@ -49,6 +70,8 @@ void main(void) console_init(); + /* vdd_log 1200mv is enough for ddr run 666Mhz */ + regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 095c555..37abe57 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += gpio.c romstage-y += spi.c romstage-y += media.c romstage-y += sdram.c +romstage-y += pwm.c ramstage-y += soc.c ramstage-y += cbmem.c @@ -61,6 +62,7 @@ ramstage-y += spi.c ramstage-y += gpio.c ramstage-y += media.c ramstage-y += rk808.c +ramstage-y += pwm.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 6d62628..d106245 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -109,6 +109,32 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); /* m0 core axi clock div: clk = clk_src / (div_con + 1) */ #define M0_DIV_MSK (0xF) +/*******************CLKSEL1 BITS***************************/ +/* pd bus clk pll sel: codec or general */ +#define PD_BUS_SEL_PLL_MSK (1 << 15) +#define PD_BUS_SEL_CPLL (0 << 15) +#define PD_BUS_SEL_GPLL (1 << 15) + +/* pd bus pclk div: + * pclk = pd_bus_aclk /(div + 1) + */ +#define PD_BUS_PCLK_DIV_SHIFT (12) +#define PD_BUS_PCLK_DIV_MSK (0x7 << 12) + +/* pd bus hclk div: + * aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 + */ +#define PD_BUS_HCLK_DIV_SHIFT (8) +#define PD_BUS_HCLK_DIV_MSK (0x3 << 8) + +/* pd bus aclk div: + * pd_bus_aclk = pd_bus_src_clk /(div0 * div1) + */ +#define PD_BUS_ACLK_DIV0_SHIFT (3) +#define PD_BUS_ACLK_DIV0_MASK (0x1f << 3) +#define PD_BUS_ACLK_DIV1_SHIFT (0) +#define PD_BUS_ACLK_DIV1_MASK (0x7 << 0) + /*******************CLKSEL10 BITS***************************/ /* peripheral bus clk pll sel: codec or general */ #define PERI_SEL_PLL_MSK (1 << 15) @@ -132,6 +158,7 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); * periph_clk_src / (peri_aclk_div_con + 1) */ #define PERI_ACLK_DIV_MSK (0x1F) +#define PERI_ACLK_DIV_SHIFT (0) /*******************CLKSEL37 BITS***************************/ #define L2_DIV_MSK (0x7) @@ -185,8 +212,28 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg) return 0; } +/* + TODO: + it should be replaced by lib.h function + 'unsigned long log2(unsigned long x)' +*/ +static unsigned int log2(unsigned int value) +{ + unsigned int div = 0; + + while (value != 1) { + div++; + value = ALIGN_UP(value, 2) / 2; + } + return div; +} + void rkclk_init(void) { + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + /* pll enter slow-mode */ writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW) | RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) @@ -231,15 +278,51 @@ void rkclk_init(void) &cru_ptr->cru_clksel_con[37]); /* + * pd_bus clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * PD_BUS_HCLK_HZ == + PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); + + pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * PD_BUS_PCLK_HZ == + PD_BUS_ACLK_HZ && pclk_div < 0x7); + + writel(RK_SETBITS(PD_BUS_SEL_GPLL) + | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, + pclk_div << PD_BUS_PCLK_DIV_SHIFT) + | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, + hclk_div << PD_BUS_HCLK_DIV_SHIFT) + | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, + aclk_div << PD_BUS_ACLK_DIV0_SHIFT) + | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0), + &cru_ptr->cru_clksel_con[1]); + + /* * peri clock pll source selection and * set up dependent divisors for PCLK/HCLK and ACLK clocks. - * peri clock select gpll, gpll clk = 594MHz - * aclk = 148.5MHz, hclk = 148.5Mhz, pclk = 74.25MHz */ - writel(RK_SETBITS(PERI_SEL_PLL_MSK) - | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, 1 << PERI_PCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, 0 << PERI_HCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, 3 << 0), + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + writel(RK_SETBITS(PERI_SEL_GPLL) + | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, + pclk_div << PERI_PCLK_DIV_SHIFT) + | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, + hclk_div << PERI_HCLK_DIV_SHIFT) + | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, + aclk_div << PERI_ACLK_DIV_SHIFT), &cru_ptr->cru_clksel_con[10]); /* PLL enter normal-mode */ diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index 4613c72..c28d181 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -26,6 +26,14 @@ #define GPLL_HZ 594000000 #define CPLL_HZ 384000000 +#define PD_BUS_ACLK_HZ 148500000 +#define PD_BUS_HCLK_HZ 148500000 +#define PD_BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + void rkclk_init(void); void rkclk_configure_spi(unsigned int bus, unsigned int hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); diff --git a/src/soc/rockchip/rk3288/grf.h b/src/soc/rockchip/rk3288/grf.h index e0dfc02..e84359b 100644 --- a/src/soc/rockchip/rk3288/grf.h +++ b/src/soc/rockchip/rk3288/grf.h @@ -87,6 +87,7 @@ struct rk3288_grf_regs { union { u32 gpio7a_iomux; u32 iomux_pwm0; + u32 iomux_pwm1; }; u32 gpio7b_iomux; union { @@ -215,4 +216,5 @@ static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; 2 << 2 | 2 << 0) #define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) #define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) +#define IOMUX_PWM1 RK_SETBITS(1 << 2) #endif diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c new file mode 100644 index 0000000..7f659f2 --- /dev/null +++ b/src/soc/rockchip/rk3288/pwm.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdlib.h> +#include <assert.h> +#include <timer.h> +#include <delay.h> + +#include "addressmap.h" +#include "grf.h" +#include "soc.h" +#include "pwm.h" +#include "clock.h" + +struct pwm_ctl { + u32 pwm_cnt; + u32 pwm_period_hpr; + u32 pwm_duty_lpr; + u32 pwm_ctrl; +}; + +struct rk3288_pwm_regs { + struct pwm_ctl pwm[4]; + u32 intsts; + u32 int_en; +}; +check_member(rk3288_pwm_regs, int_en, 0x44); + +#define RK_PWM_DISABLE (0 << 0) +#define RK_PWM_ENABLE (1 << 0) + + +#define PWM_ONE_SHOT (0 << 1) +#define PWM_CONTINUOUS (1 << 1) +#define RK_PWM_CAPTURE (1 << 2) + +#define PWM_DUTY_POSTIVE (1 << 3) +#define PWM_DUTY_NEGATIVE (0 << 3) + +#define PWM_INACTIVE_POSTIVE (1 << 4) +#define PWM_INACTIVE_NEGATIVE (0 << 4) + +#define PWM_OUTPUT_LEFT (0 << 5) +#define PWM_OUTPUT_CENTER (1 << 5) + +#define PWM_LP_ENABLE (1 << 8) +#define PWM_LP_DISABLE (0 << 8) + +#define PWM_SEL_SCALE_CLK (1 << 9) +#define PWM_SEL_SRC_CLK (0 << 9) + +struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE; + +void pwm_init(u32 id, u32 period_ns, u32 duty_ns) +{ + unsigned long period, duty; + + /*use rk pwm*/ + writel(RK_SETBITS(1 << 0), &rk3288_grf->soc_con2); + + writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | + PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | + RK_PWM_DISABLE, + &rk3288_pwm->pwm[id].pwm_ctrl); + + period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC; + duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC; + + writel(period, &rk3288_pwm->pwm[id].pwm_period_hpr); + writel(duty, &rk3288_pwm->pwm[id].pwm_duty_lpr); + setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); +} diff --git a/src/soc/rockchip/rk3288/pwm.h b/src/soc/rockchip/rk3288/pwm.h new file mode 100644 index 0000000..168d8a7 --- /dev/null +++ b/src/soc/rockchip/rk3288/pwm.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__ +#define __SOC_ROCKCHIP_RK3288_PWM_H__ + +void pwm_init(u32 id, u32 period_ns, u32 duty_ns); + +#endif +

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New patch to review for coreboot: 891fc7f coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9239 -gerrit commit 891fc7f17270d6de6d6d18ad02da19d13a5ed8e4 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Sep 25 20:27:26 2014 -0700 coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/sdram_configs.c | 2 +- .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ++++++++++++++++++++++ src/soc/rockchip/rk3288/sdram.c | 37 +++++++--- 3 files changed, 105 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 21a483c..cc29de0 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -28,7 +28,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */ diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc new file mode 100644 index 0000000..3fdbecf --- /dev/null +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4B4G1646D-BYK0 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666000000, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 7ac84f0..6c0c7fd 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -340,12 +340,12 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = { #define PRT_DLLSRST(n) ((n) << 0) /* PTR1 */ -#define PRT_DINIT1(n) ((n) << 19) #define PRT_DINIT0(n) ((n) << 0) +#define PRT_DINIT1(n) ((n) << 19) /* PTR2 */ -#define PRT_DINIT3(n) ((n) << 17) #define PRT_DINIT2(n) ((n) << 0) +#define PRT_DINIT3(n) ((n) << 17) /* DCR */ #define DDRMD_LPDDR 0 @@ -442,6 +442,7 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = { #define DPDE_CMD (9) #define LPDDR2_MA(n) (((n) & 0xff) << 4) +#define LPDDR2_OP(n) (((n) & 0xff) << 12) #define START_CMD (1u << 31) @@ -620,7 +621,7 @@ static void pctl_cfg(u32 channel, writel(sdram_params->pctl_timing.tcwl - 1, &ddr_pctl_regs->dfitphywrlat); writel(MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN - | DDR2_DDR3_BL_8 | TFAW_CFG(5) | PD_EXIT_SLOW + | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg); writel(MSCH_MAINDDR3(channel, 1), &rk3288_grf->soc_con0); @@ -650,12 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) writel(sdram_params->noc_activate, &msch_regs->activate); writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), &msch_regs->devtodev); - writel(PRT_ITMSRST(8) | PRT_DLLLOCK(2750) | PRT_DLLSRST(27), - &ddr_publ_regs->ptr[0]); - /* tDINIT1=400ns (533MHz), tDINIT0=500us (533MHz) */ - writel(PRT_DINIT1(213) | PRT_DINIT0(266525), &ddr_publ_regs->ptr[1]); - /* tDINIT3=1us (533MHz), tDINIT2=200us (533MHz) */ - writel(PRT_DINIT3(534) | PRT_DINIT2(106610), &ddr_publ_regs->ptr[2]); + writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000 + * 5120, 1000)) + | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000 + * 50, 1000)) + | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]); + writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000 + * 500000, 1000)) + | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000 + * 400, 1000)), &ddr_publ_regs->ptr[1]); + writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000 + * 200000, 1000)) + | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000 + * 1000, 1000)), &ddr_publ_regs->ptr[2]); switch (sdram_params->dramtype) { case LPDDR3: @@ -860,7 +868,7 @@ static int data_training(u32 channel, } } /* send some auto refresh to complement the lost while DTT */ - for (i = 0; i < (rank > 1 ? 4 : 2); i++) + for (i = 0; i < (rank > 1 ? 8 : 4); i++) send_command(ddr_pctl_regs, rank, REF_CMD, 0); if (sdram_params->dramtype != LPDDR3) @@ -962,7 +970,10 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) int zqcr; printk(BIOS_INFO, "Starting SDRAM initialization...\n"); - if (sdram_params->ddr_freq > 533000000) + if ((sdram_params->dramtype == DDR3 + && sdram_params->ddr_freq > 800000000) + || (sdram_params->dramtype == LPDDR3 + && sdram_params->ddr_freq > 533000000)) die("SDRAM frequency is to high!"); rkclk_configure_ddr(sdram_params->ddr_freq); @@ -1011,6 +1022,10 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) if (sdram_params->dramtype == LPDDR3) { /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ udelay(10); + send_command(ddr_pctl_regs, + (sdram_params->ch[channel].rank | 1), + MRS_CMD, LPDDR2_MA(11) | + sdram_params->odt ? LPDDR2_OP(3) : 0); if (channel == 0) { writel(0, &ddr_pctl_regs->mrrcfg0); send_command(ddr_pctl_regs, 1, MRR_CMD,

1 0

New patch to review for coreboot: 0faea77 pinky: Force delay for EC SPI transfers
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9238 -gerrit commit 0faea77485573bfdd7e0830fa01f72be9563efec Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Sep 27 20:10:41 2014 -0700 pinky: Force delay for EC SPI transfers This gives the EC some time to wake-up between asserting /CS and starting a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer on Pinky Original-Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220243 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Commit-Queue: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Change-Id: I103542517d3ebd7da4f0394b3ae4f68f58403b1e (cherry picked from commit bdb67fe489b7cbea7a26492fa0536ca452434052) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 07b31ff..7f981b4 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -49,6 +49,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0 +config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US + int + default 100 + config VBOOT_RAMSTAGE_INDEX hex default 0x3

1 0

Patch merged into coreboot/master: 8f3883d veyron_pinky: Add rev2 support, clean up mainboard.c
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 8f3883d5f444d3b72661d585e4671d0996771305 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 26 21:01:08 2014 -0700 veyron_pinky: Add rev2 support, clean up mainboard.c This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730 Reviewed-on: http://review.coreboot.org/9237 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9237 for details. -gerrit

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Patch merged into coreboot/master: 5c2988c veyron: select rw romstage using vboot2
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 5c2988c4616d8326f56037e7ef5e8280c134ef7d Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Sep 24 09:39:16 2014 -0700 veyron: select rw romstage using vboot2 this change makes veyron pinky to select a rw romstage using vboot2. BUG=None TEST=Booted Veyron Pinky. Verified firmware selection in the log. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> CQ-DEPEND=CL:219100 Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f Original-Reviewed-on: https://chromium-review.googlesource.com/219103 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475 Reviewed-on: http://review.coreboot.org/9234 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9234 for details. -gerrit

1 0

New patch to review for coreboot: 401235e veyron_pinky: Add rev2 support, clean up mainboard.c
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9237 -gerrit commit 401235e8e7a4fdf85fe864bebdd16757749a767f Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 26 21:01:08 2014 -0700 veyron_pinky: Add rev2 support, clean up mainboard.c This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730 --- src/mainboard/google/veyron_pinky/Makefile.inc | 3 + src/mainboard/google/veyron_pinky/board.h | 32 ++++++ src/mainboard/google/veyron_pinky/chromeos.c | 6 +- src/mainboard/google/veyron_pinky/mainboard.c | 133 +++++++++++++------------ src/mainboard/google/veyron_pinky/reset.c | 4 +- src/soc/rockchip/rk3288/rk808.c | 7 ++ src/soc/rockchip/rk3288/rk808.h | 1 + 7 files changed, 121 insertions(+), 65 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc index 63fefe4..c33cfa3 100644 --- a/src/mainboard/google/veyron_pinky/Makefile.inc +++ b/src/mainboard/google/veyron_pinky/Makefile.inc @@ -17,12 +17,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## bootblock-y += bootblock.c +bootblock-y += boardid.c bootblock-y += chromeos.c bootblock-y += reset.c +verstage-y += boardid.c verstage-y += chromeos.c verstage-y += reset.c +romstage-y += boardid.c romstage-y += romstage.c romstage-y += chromeos.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h new file mode 100644 index 0000000..2ffa9cf --- /dev/null +++ b/src/mainboard/google/veyron_pinky/board.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H + +#include <boardid.h> +#include <soc/rockchip/rk3288/gpio.h> + +#define PMIC_BUS 0 + +#define GPIO_RESET (board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2)) + +/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */ + +#endif /* __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H */ diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 50dc494..827b004 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -25,8 +25,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/rockchip/rk3288/gpio.h> +#include "board.h" + #define GPIO_WP GPIO(7, A, 6) -#define GPIO_LID GPIO(7, B, 5) +#define GPIO_LID (board_id() > 0 ? GPIO(0, A, 6) : GPIO(7, B, 5)) #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) @@ -34,7 +36,7 @@ void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); gpio_input_pullup(GPIO_LID); - gpio_input_pullup(GPIO_POWER); + gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); } diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 0bbd496..22c9b0e 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -32,97 +32,106 @@ #include <soc/rockchip/rk3288/rk808.h> #include <soc/rockchip/rk3288/spi.h> -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) +#include "board.h" -static void setup_gpio(void) +static void configure_usb(void) { - /*SOC and TPM reset GPIO, active high.*/ - gpio_output(GPIO(0, B, 2), 0); + gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ + gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ + + switch (board_id()) { + case 0: + gpio_output(GPIO(7, B, 3), 1); /* 5V_DRV */ + break; + default: + break; /* 5V_DRV moved to EC after rev1 */ + } +} - /* Configure GPIO for lcd_bl_en */ - gpio_output(GPIO(7, A, 2), 1); +static void configure_sdmmc(void) +{ + writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0); - /*Configure backlight PWM 100% brightness*/ - gpio_output(GPIO(7, A, 0), 0); + /* use sdmmc0 io, disable JTAG function */ + writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0); - /* Configure GPIO for lcd_en */ - gpio_output(GPIO(7, B, 7), 1); + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 8, 3300); /* VCCIO_SD */ + gpio_output(GPIO(7, C, 5), 1); /* SD_EN */ + break; + default: + rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */ + rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */ + break; + } + + gpio_input(GPIO(7, A, 5)); /* SD_DET */ } -static void setup_iomux(void) +static void configure_emmc(void) { - /*i2c0 for pmic*/ - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); - - /*i2c2 for codec*/ - writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); - - writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); - writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); - writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); - writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0); writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata); writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren); writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd); -} - -static void setup_usb_poweron(void) -{ - /* Configure GPIO for usb1_pwr_en */ - gpio_output(GPIO(0, B, 3), 1); - /* Configure GPIO for usb2_pwr_en */ - gpio_output(GPIO(0, B, 4), 1); - - /* Configure GPIO for 5v_drv */ - gpio_output(GPIO(7, B, 3), 1); + gpio_output(GPIO(7, B, 4), 1); /* EMMC_RST_L */ } -static void configure_sdmmc(void) +static void configure_codec(void) { - /* Configure GPIO for sd_en */ - gpio_output(GPIO(7, C, 5), 1); + writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */ - /* Configure GPIO for sd_detec */ - gpio_input_pullup(GPIO(7, A, 5)); + writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); + writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); - /*use sdmmc0 io, disable JTAG function*/ - writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0); -} + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 5, 1800); /* VCC18_CODEC */ + break; + default: + rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */ + break; + } -static void configure_emmc(void) -{ - /* Configure GPIO for emmc_pwrctrl */ - gpio_output(GPIO(7, B, 4), 1); -} - -static void configure_i2s(void) -{ - /*AUDIO IO domain 1.8V voltage selection*/ + /* AUDIO IO domain 1.8V voltage selection */ writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel); rkclk_configure_i2s(12288000); } -static void pmic_init(unsigned int bus) +static void configure_lcd(void) { - rk808_configure_ldo(bus, 4, 1800); /* VCC18_LCD */ - rk808_configure_ldo(bus, 5, 1800); /* VCC18_CODEC */ - rk808_configure_ldo(bus, 6, 1000); /* VCC10_LCD */ - rk808_configure_ldo(bus, 8, 3300); /* VCCIO_SD */ + writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); + + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 4, 1800); /* VCC18_LCD */ + rk808_configure_ldo(PMIC_BUS, 6, 1000); /* VCC10_LCD */ + gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */ + break; + default: + rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */ + rk808_configure_ldo(PMIC_BUS, 7, 3300); /* VCC10_LCD_PWREN_H */ + rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */ + break; + } + + gpio_output(GPIO(7, A, 0), 0); /* LCDC_BL */ + gpio_output(GPIO(7, A, 2), 1); /* BL_EN */ } static void mainboard_init(device_t dev) { - setup_iomux(); - pmic_init(0); - setup_gpio(); - setup_usb_poweron(); + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */ + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */ + + gpio_output(GPIO_RESET, 0); + + configure_usb(); configure_sdmmc(); configure_emmc(); - configure_i2s(); + configure_codec(); + configure_lcd(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c index d769665..45c28b2 100644 --- a/src/mainboard/google/veyron_pinky/reset.c +++ b/src/mainboard/google/veyron_pinky/reset.c @@ -21,8 +21,10 @@ #include <soc/rockchip/rk3288/gpio.h> #include <reset.h> +#include "board.h" + void hard_reset(void) { - gpio_output(GPIO(0, B, 2), 1); + gpio_output(GPIO_RESET, 1); while (1); } diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index 0d629ca..50df96d 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -26,6 +26,7 @@ #define RK808_ADDR 0x1b +#define DCDC_EN 0x23 #define LDO_EN 0x24 #define LDO_ONSEL(i) (0x39 + 2 * i) #define LDO_SLPSEL(i) (0x3a + 2 * i) @@ -39,6 +40,12 @@ static void rk808_clrsetbits(uint8_t bus, uint8_t reg, uint8_t clr, uint8_t set) printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg); } +void rk808_configure_switch(uint8_t bus, int sw, int enabled) +{ + assert(sw == 1 || sw == 2); + rk808_clrsetbits(bus, DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4)); +} + void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts) { uint8_t vsel; diff --git a/src/soc/rockchip/rk3288/rk808.h b/src/soc/rockchip/rk3288/rk808.h index a6ba67c..0052075 100644 --- a/src/soc/rockchip/rk3288/rk808.h +++ b/src/soc/rockchip/rk3288/rk808.h @@ -20,6 +20,7 @@ #ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ #define __SOC_ROCKCHIP_RK3288_PMIC_H__ +void rk808_configure_switch(uint8_t bus, int sw, int enabled); void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); #endif

1 0

New patch to review for coreboot: f844fa0 veyron_pinky: Add rev2 support, clean up mainboard.c
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9236 -gerrit commit f844fa0bad924c14b4e990c947ac5b2e36615fac Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 26 21:01:08 2014 -0700 veyron_pinky: Add rev2 support, clean up mainboard.c This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/veyron_pinky/Makefile.inc | 3 + src/mainboard/google/veyron_pinky/board.h | 32 ++++++ src/mainboard/google/veyron_pinky/chromeos.c | 6 +- src/mainboard/google/veyron_pinky/mainboard.c | 133 +++++++++++++------------ src/mainboard/google/veyron_pinky/reset.c | 4 +- src/soc/rockchip/rk3288/rk808.c | 7 ++ src/soc/rockchip/rk3288/rk808.h | 1 + 7 files changed, 121 insertions(+), 65 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc index 63fefe4..c33cfa3 100644 --- a/src/mainboard/google/veyron_pinky/Makefile.inc +++ b/src/mainboard/google/veyron_pinky/Makefile.inc @@ -17,12 +17,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## bootblock-y += bootblock.c +bootblock-y += boardid.c bootblock-y += chromeos.c bootblock-y += reset.c +verstage-y += boardid.c verstage-y += chromeos.c verstage-y += reset.c +romstage-y += boardid.c romstage-y += romstage.c romstage-y += chromeos.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h new file mode 100644 index 0000000..2ffa9cf --- /dev/null +++ b/src/mainboard/google/veyron_pinky/board.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H + +#include <boardid.h> +#include <soc/rockchip/rk3288/gpio.h> + +#define PMIC_BUS 0 + +#define GPIO_RESET (board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2)) + +/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */ + +#endif /* __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H */ diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 50dc494..827b004 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -25,8 +25,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/rockchip/rk3288/gpio.h> +#include "board.h" + #define GPIO_WP GPIO(7, A, 6) -#define GPIO_LID GPIO(7, B, 5) +#define GPIO_LID (board_id() > 0 ? GPIO(0, A, 6) : GPIO(7, B, 5)) #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) @@ -34,7 +36,7 @@ void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); gpio_input_pullup(GPIO_LID); - gpio_input_pullup(GPIO_POWER); + gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); } diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 0bbd496..22c9b0e 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -32,97 +32,106 @@ #include <soc/rockchip/rk3288/rk808.h> #include <soc/rockchip/rk3288/spi.h> -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) +#include "board.h" -static void setup_gpio(void) +static void configure_usb(void) { - /*SOC and TPM reset GPIO, active high.*/ - gpio_output(GPIO(0, B, 2), 0); + gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ + gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ + + switch (board_id()) { + case 0: + gpio_output(GPIO(7, B, 3), 1); /* 5V_DRV */ + break; + default: + break; /* 5V_DRV moved to EC after rev1 */ + } +} - /* Configure GPIO for lcd_bl_en */ - gpio_output(GPIO(7, A, 2), 1); +static void configure_sdmmc(void) +{ + writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0); - /*Configure backlight PWM 100% brightness*/ - gpio_output(GPIO(7, A, 0), 0); + /* use sdmmc0 io, disable JTAG function */ + writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0); - /* Configure GPIO for lcd_en */ - gpio_output(GPIO(7, B, 7), 1); + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 8, 3300); /* VCCIO_SD */ + gpio_output(GPIO(7, C, 5), 1); /* SD_EN */ + break; + default: + rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */ + rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */ + break; + } + + gpio_input(GPIO(7, A, 5)); /* SD_DET */ } -static void setup_iomux(void) +static void configure_emmc(void) { - /*i2c0 for pmic*/ - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); - - /*i2c2 for codec*/ - writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); - - writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); - writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); - writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); - writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0); writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata); writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren); writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd); -} - -static void setup_usb_poweron(void) -{ - /* Configure GPIO for usb1_pwr_en */ - gpio_output(GPIO(0, B, 3), 1); - /* Configure GPIO for usb2_pwr_en */ - gpio_output(GPIO(0, B, 4), 1); - - /* Configure GPIO for 5v_drv */ - gpio_output(GPIO(7, B, 3), 1); + gpio_output(GPIO(7, B, 4), 1); /* EMMC_RST_L */ } -static void configure_sdmmc(void) +static void configure_codec(void) { - /* Configure GPIO for sd_en */ - gpio_output(GPIO(7, C, 5), 1); + writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */ - /* Configure GPIO for sd_detec */ - gpio_input_pullup(GPIO(7, A, 5)); + writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); + writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); - /*use sdmmc0 io, disable JTAG function*/ - writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0); -} + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 5, 1800); /* VCC18_CODEC */ + break; + default: + rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */ + break; + } -static void configure_emmc(void) -{ - /* Configure GPIO for emmc_pwrctrl */ - gpio_output(GPIO(7, B, 4), 1); -} - -static void configure_i2s(void) -{ - /*AUDIO IO domain 1.8V voltage selection*/ + /* AUDIO IO domain 1.8V voltage selection */ writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel); rkclk_configure_i2s(12288000); } -static void pmic_init(unsigned int bus) +static void configure_lcd(void) { - rk808_configure_ldo(bus, 4, 1800); /* VCC18_LCD */ - rk808_configure_ldo(bus, 5, 1800); /* VCC18_CODEC */ - rk808_configure_ldo(bus, 6, 1000); /* VCC10_LCD */ - rk808_configure_ldo(bus, 8, 3300); /* VCCIO_SD */ + writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc); + + switch (board_id()) { + case 0: + rk808_configure_ldo(PMIC_BUS, 4, 1800); /* VCC18_LCD */ + rk808_configure_ldo(PMIC_BUS, 6, 1000); /* VCC10_LCD */ + gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */ + break; + default: + rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */ + rk808_configure_ldo(PMIC_BUS, 7, 3300); /* VCC10_LCD_PWREN_H */ + rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */ + break; + } + + gpio_output(GPIO(7, A, 0), 0); /* LCDC_BL */ + gpio_output(GPIO(7, A, 2), 1); /* BL_EN */ } static void mainboard_init(device_t dev) { - setup_iomux(); - pmic_init(0); - setup_gpio(); - setup_usb_poweron(); + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */ + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */ + + gpio_output(GPIO_RESET, 0); + + configure_usb(); configure_sdmmc(); configure_emmc(); - configure_i2s(); + configure_codec(); + configure_lcd(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c index d769665..45c28b2 100644 --- a/src/mainboard/google/veyron_pinky/reset.c +++ b/src/mainboard/google/veyron_pinky/reset.c @@ -21,8 +21,10 @@ #include <soc/rockchip/rk3288/gpio.h> #include <reset.h> +#include "board.h" + void hard_reset(void) { - gpio_output(GPIO(0, B, 2), 1); + gpio_output(GPIO_RESET, 1); while (1); } diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index 0d629ca..50df96d 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -26,6 +26,7 @@ #define RK808_ADDR 0x1b +#define DCDC_EN 0x23 #define LDO_EN 0x24 #define LDO_ONSEL(i) (0x39 + 2 * i) #define LDO_SLPSEL(i) (0x3a + 2 * i) @@ -39,6 +40,12 @@ static void rk808_clrsetbits(uint8_t bus, uint8_t reg, uint8_t clr, uint8_t set) printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg); } +void rk808_configure_switch(uint8_t bus, int sw, int enabled) +{ + assert(sw == 1 || sw == 2); + rk808_clrsetbits(bus, DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4)); +} + void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts) { uint8_t vsel; diff --git a/src/soc/rockchip/rk3288/rk808.h b/src/soc/rockchip/rk3288/rk808.h index a6ba67c..0052075 100644 --- a/src/soc/rockchip/rk3288/rk808.h +++ b/src/soc/rockchip/rk3288/rk808.h @@ -20,6 +20,7 @@ #ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ #define __SOC_ROCKCHIP_RK3288_PMIC_H__ +void rk808_configure_switch(uint8_t bus, int sw, int enabled); void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); #endif

1 0

New patch to review for coreboot: ca229ed Clean up architecture-specific Kconfigs
by Patrick Georgi 02 Apr '15

02 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9235 -gerrit commit ca229edfcd2e0a4dd844c47452f17792b1133300 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 19 13:18:16 2014 -0700 Clean up architecture-specific Kconfigs It's an unfortunate side effect of our different-archs-per-stage mechanism that all src/arch/*/Kconfig files are always parsed with no if blocks to exclude them if they're not relevant. This makes it very easy to accidentally rely on a Kconfig default set by a totally different and not applying architecture. This patch moves a few Kconfigs from ARM and X86 that leaked out like this into a common Kconfig file for clarity. It also gives ARM64 its own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech off the ARM one (currently not used by any board). In the future, we should maybe prefix all options in the arch/*/Kconfig files with the architecture name (such as X86_BOOTBLOCK_NORMAL and ARM_LPAE are already doing), to make it more apparent when they are used in the wrong place. BUG=None TEST=None (tested together with dependent changes) Change-Id: I3e8bb3dfbb2c4edada621ce16d130bd7387d4eb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5528aa9252cdf711af3c160da387c6a7bebe9e76 Original-Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219171 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 12 ++++++++++++ src/arch/arm/Kconfig | 8 -------- src/arch/arm64/Kconfig | 6 ++++++ src/arch/arm64/armv8/Makefile.inc | 5 ++--- src/arch/x86/Kconfig | 4 ---- 5 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7aee478..aa4d6ee 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -311,6 +311,14 @@ source src/drivers/intel/fsp/Kconfig endmenu +config CPU_HAS_BOOTBLOCK_INIT + bool + default n + +config MAINBOARD_HAS_BOOTBLOCK_INIT + bool + default n + source src/device/Kconfig menu "Generic Drivers" @@ -337,6 +345,10 @@ config HEAP_SIZE hex default 0x4000 +config STACK_SIZE + hex + default 0x1000 + config MAX_CPUS int default 1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 124dc3f..77ed41a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -24,14 +24,6 @@ config ARM_BOOTBLOCK_CUSTOM bool default n -config CPU_HAS_BOOTBLOCK_INIT - bool - default n - -config MAINBOARD_HAS_BOOTBLOCK_INIT - bool - default n - config ARM_LPAE bool default n diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 2465bb1..16830bc 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -26,3 +26,9 @@ config ARCH_SPINTABLE depends on ARCH_RAMSTAGE_ARM64 source src/arch/arm64/armv8/Kconfig + +# If a custom bootblock is necessary, this option should be "select"-ed by +# the thing that needs it, probably the CPU. +config ARM64_BOOTBLOCK_CUSTOM + bool + default n diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 955ca67..ae9f38d 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -32,11 +32,10 @@ armv8_asm_flags = $(armv8_flags) ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) -ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) +ifneq ($(CONFIG_ARM64_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.S +bootblock-y += bootblock_simple.c endif -bootblock-$(CONFIG_ARM_BOOTBLOCK_SIMPLE) += bootblock_simple.c -bootblock-$(CONFIG_ARM_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += cache.c bootblock-y += cpu.S bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 580814f..93474a8 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -49,10 +49,6 @@ config RAMBASE hex default 0x100000 -config STACK_SIZE - hex - default 0x1000 - # This is something you almost certainly don't want to mess with. # How many SIPIs do we send when starting up APs and cores? # The answer in 2000 or so was '2'. Nowadays, on many systems,

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coreboot-gerrit April 2015