coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2cebbcb pistachio: allow more room for bootblock
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9190 -gerrit commit 2cebbcbfef378c5ae56fe611f97cf3c24b84421d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:28:23 2014 -0800 pistachio: allow more room for bootblock 32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index c7d4658..de2e52e 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -42,12 +42,12 @@ config BOOTBLOCK_BASE config CBFS_ROM_OFFSET hex - default 0x4100 + default 0x8100 config CBFS_HEADER_ROM_OFFSET # Effectively the maximum size of the bootblock hex - default 0x4000 + default 0x8000 config ROMSTAGE_BASE hex

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Patch set updated for coreboot: 0fce80b pistachio: enable early console
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9189 -gerrit commit 0fce80bdbde3c6558d8d9fa84c8fe21930deec55 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 19:55:07 2014 -0800 pistachio: enable early console Adding this configuration option enables romstage console output. Ideally this setting should be enabled automatically in case the bootblock console is enabled. BRANCH=none BUG=chrome-os-partner:31438 TEST=romstage messages show up on the console Change-Id: I5823fc737f4c65a4222592a8857ac89e7fe0ba3e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 30f5f64ffcb8ab938781d87b7928dc3b19c58504 Original-Change-Id: I710e05ce24e1aeccc90aead50336f00dec52fff0 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229202 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 2e8b700..c7d4658 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -24,6 +24,7 @@ config CPU_IMGTEC_PISTACHIO select DYNAMIC_CBMEM select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select EARLY_CONSOLE select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING

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Patch merged into coreboot/master: b71d9b8 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit b71d9b8a0f02d5f458620cb21cdfe7799b1faf84 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Oct 10 03:08:15 2014 +0800 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/9223 for details. -gerrit

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Patch set updated for coreboot: 4b7459e Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9223 -gerrit commit 4b7459ed0808405eef5123dc61716b822636e509 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Oct 10 03:08:15 2014 +0800 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/pcie.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index c147663..2e70f45 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd1c55a..be17874 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -611,8 +611,15 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) pci_write_config32(dev, 0x94, (device << 16) | vendor); } +static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) +{ + /* Set max snoop and non-snoop latency for Broadwell */ + pci_mmio_write_config32(dev, off, 0x10031003); +} + static struct pci_operations pcie_ops = { .set_subsystem = pcie_set_subsystem, + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; static struct device_operations device_ops = {

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Patch merged into coreboot/master: 1d84ef5 pistachio: add gpio type definition
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 1d84ef57c2f095e1b7fc63546860b018dfea1889 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Oct 28 19:15:52 2014 -0700 pistachio: add gpio type definition This is necessary to support generic gpio interface in src/lib. This file will be later populated with more GPIO definitions. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226181 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/9184 for details. -gerrit

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Patch merged into coreboot/master: c3e7c4e Clean up architecture-specific Kconfigs
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit c3e7c4e7b43ebba54a141896b74572eaa9e75abf Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 19 13:18:16 2014 -0700 Clean up architecture-specific Kconfigs It's an unfortunate side effect of our different-archs-per-stage mechanism that all src/arch/*/Kconfig files are always parsed with no if blocks to exclude them if they're not relevant. This makes it very easy to accidentally rely on a Kconfig default set by a totally different and not applying architecture. This patch moves a few Kconfigs from ARM and X86 that leaked out like this into a common Kconfig file for clarity. It also gives ARM64 its own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech off the ARM one (currently not used by any board). In the future, we should maybe prefix all options in the arch/*/Kconfig files with the architecture name (such as X86_BOOTBLOCK_NORMAL and ARM_LPAE are already doing), to make it more apparent when they are used in the wrong place. BUG=None TEST=None (tested together with dependent changes) Change-Id: I3e8bb3dfbb2c4edada621ce16d130bd7387d4eb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5528aa9252cdf711af3c160da387c6a7bebe9e76 Original-Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219171 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9235 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/9235 for details. -gerrit

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Patch merged into coreboot/master: db27306 build system: extend src-to-obj for non-.c/.S files
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit db273065f67ef432937399a324364822539ca559 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 17:03:28 2015 +0100 build system: extend src-to-obj for non-.c/.S files It also creates file names in the build directory and with the stage sliced in, but keeps the extension for anything not .c or .S. Also some handling for non-.c/.S files was adapted to match. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: If8f89a7daffcf51f430b64c3293d2a817ae5120f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9175 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/9175 for details. -gerrit

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Patch merged into coreboot/master: 5c9f534 urara: Fix CBFS header definitions
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 5c9f5342699a85b5c06f74924d730733591a64bd Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 4 16:12:05 2014 -0800 urara: Fix CBFS header definitions Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/9187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/9187 for details. -gerrit

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Patch set updated for coreboot: 29a81d1 urara: Select CONSOLE_SERIAL
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9186 -gerrit commit 29a81d123b0e6c2d6a2b7f7a4c213d635d9389dd Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Oct 31 17:55:59 2014 +0000 urara: Select CONSOLE_SERIAL CONSOLE_SERIAL selected in Pistachio configuration file; configuration needed to enable UART. BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed exepected console output BRANCH=none Change-Id: I1a56ae34ce553e66b4d18f0561ca4b3287863d1e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: f9a83da568e5cfb4c377f3b33a8ce11a7d8d0bd5 Original-Change-Id: I4947ea8608593ec3f44e336ebdf3930f44493ec9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226841 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/imgtec/pistachio/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 83408bd..183c457 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -24,6 +24,7 @@ config CPU_IMGTEC_PISTACHIO select DYNAMIC_CBMEM select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select CONSOLE_SERIAL select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING

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New patch to review for coreboot: 65fec0d nyan*: known-good drive for fast-train only
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9248 -gerrit commit 65fec0de5b13c9e3c22bc5793eea792953f9eabc Author: Neil Chen <neilc(a)nvidia.com> Date: Wed Sep 24 10:41:08 2014 +0800 nyan*: known-good drive for fast-train only A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 --- src/soc/nvidia/tegra124/dp.c | 3 +++ src/soc/nvidia/tegra124/sor.c | 48 ++++++++++++++++++++++--------------------- src/soc/nvidia/tegra124/sor.h | 1 + 3 files changed, 29 insertions(+), 23 deletions(-) diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 9ff50ea..35a5c73 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -1254,6 +1254,9 @@ static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp, printk(BIOS_ERR, "dp: full link training failed\n"); return ret; } + } else { + /* set to a known-good drive setting if fast link succeeded */ + tegra_dc_sor_set_voltage_swing(&dp->sor); } /* Everything goes well, double check the link config */ diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 1f9df6c..3eaae0e 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -832,11 +832,34 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, 0xf0, 0x0); } -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) { - u32 pad_ctrl = 0; u32 drive_current = 0; u32 pre_emphasis = 0; + + /* Set to a known-good pre-calibrated setting */ + switch (sor->link_cfg->link_bw) { + case SOR_LINK_SPEED_G1_62: + case SOR_LINK_SPEED_G2_7: + drive_current = 0x13131313; + pre_emphasis = 0; + break; + case SOR_LINK_SPEED_G5_4: + printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); + default: + printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", + sor->link_cfg->link_bw); + return; + } + + tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), + drive_current); + tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); +} + +void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) +{ + u32 pad_ctrl = 0; int err = 0; switch (sor->link_cfg->lane_count) { @@ -873,27 +896,6 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) "Wait for lane power down failed: %d\n", err); return; } - - /* Set to a known-good pre-calibrated setting */ - switch (sor->link_cfg->link_bw) { - case SOR_LINK_SPEED_G1_62: - case SOR_LINK_SPEED_G2_7: - drive_current = 0x13131313; - pre_emphasis = 0; - break; - case SOR_LINK_SPEED_G5_4: - drive_current = 0x19191919; - pre_emphasis = 0x09090909; - break; - default: - printk(BIOS_ERR, "Invalid sor link bandwidth: %d\n", - sor->link_cfg->link_bw); - return; - } - - tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), - drive_current); - tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); } void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h index 4e4211e..569cdb9 100644 --- a/src/soc/nvidia/tegra124/sor.h +++ b/src/soc/nvidia/tegra124/sor.h @@ -920,6 +920,7 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor); void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,

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coreboot-gerrit April 2015