coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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3044 discussions

New patch to review for coreboot: 60dc6d6 t132: Enable SMMU translations
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9258 -gerrit commit 60dc6d6ec60da98d678f60603da1c9bb8a3c4b01 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Oct 10 01:31:02 2014 -0700 t132: Enable SMMU translations BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson <olofj(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 --- src/soc/nvidia/tegra132/addressmap.c | 3 +++ src/soc/nvidia/tegra132/mc.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 3df15b7..a18e1b8 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -188,4 +188,7 @@ void trustzone_region_init(void) /* Set the carveout region. */ write32(tz_base_mib << 20, &mc->security_cfg0); write32(tz_size_mib, &mc->security_cfg1); + + /* Enable SMMU translations */ + write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config); } diff --git a/src/soc/nvidia/tegra132/mc.h b/src/soc/nvidia/tegra132/mc.h index c9faa49..3ce7900 100644 --- a/src/soc/nvidia/tegra132/mc.h +++ b/src/soc/nvidia/tegra132/mc.h @@ -117,6 +117,8 @@ struct tegra_mc_regs { }; enum { + MC_SMMU_CONFIG_ENABLE = 1, + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,

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New patch to review for coreboot: 69f9b8a tegra132: Store ODMDATA from BCT into PMC scratch for use by kernel
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9257 -gerrit commit 69f9b8a3611a501f9ef917188dd8cf001eda2605 Author: Tom Warren <twarren(a)nvidia.com> Date: Thu Oct 9 16:01:33 2014 -0700 tegra132: Store ODMDATA from BCT into PMC scratch for use by kernel In able to do earlyprintk spew on LP0 resume, the kernel needs to know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info, and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word from the BCT copy stored in IRAM by the BootROM. BUG=chrome-os-partner:32015 BRANCH=none TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell on Rush and confirmed value is what's in odmdata.cfg. Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222402 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd --- src/soc/nvidia/tegra132/bootblock.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6481eb3..6f25050 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -29,6 +29,29 @@ #include "power.h" +#define BCT_OFFSET_IN_BIT 0x50 +#define ODMDATA_OFFSET_IN_BCT 0x6A8 +#define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) + +static void save_odmdata(void) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + uintptr_t bct_offset; + u32 odmdata; + + // pmc.odmdata: [18:19]: console type, [15:17]: UART id. + // TODO(twarren) ODMDATA is stored in the BCT, from bct/odmdata.cfg. + // I use the BCT offset in the BIT in SRAM to locate the BCT, and + // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT + // struct header from cbootimage, but it seems like overkill for this. + + bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); + if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { + odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); + write32(odmdata, &pmc->odmdata); + } +} + void __attribute__((weak)) bootblock_mainboard_early_init(void) { /* Empty default implementation. */ @@ -52,6 +75,9 @@ void main(void) CLK_H_APBDMA, 0, CLK_V_MSELECT, 0, 0); + /* Find ODMDATA in IRAM and save it to scratch reg */ + save_odmdata(); + bootblock_mainboard_early_init(); if (CONFIG_BOOTBLOCK_CONSOLE) {

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New patch to review for coreboot: aec1970 tegra132: remove framebuffer reservation
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9256 -gerrit commit aec1970dc1954d429556af89fb051d3adedc332f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 7 16:16:48 2014 -0500 tegra132: remove framebuffer reservation There's no need to reserve the framebuffer within corebot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 --- src/soc/nvidia/tegra132/addressmap.c | 15 --------------- src/soc/nvidia/tegra132/cbmem.c | 22 +++++++++++----------- src/soc/nvidia/tegra132/include/soc/addressmap.h | 3 --- src/soc/nvidia/tegra132/include/soc/display.h | 2 -- src/soc/nvidia/tegra132/soc.c | 6 ------ 5 files changed, 11 insertions(+), 37 deletions(-) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index d7ade2f..3df15b7 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <console/console.h> #include <soc/addressmap.h> -#include <soc/display.h> #include <soc/id.h> #include "mc.h" #include "sdram.h" @@ -166,20 +165,6 @@ void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib) memory_in_range(base_mib, end_mib, 0); } -uintptr_t framebuffer_attributes(size_t *size_mib) -{ - uintptr_t begin; - uintptr_t end; - - /* Place the framebuffer just below the 32-bit addressable limit. */ - memory_in_range_below_4gb(&begin, &end); - - *size_mib = FB_SIZE_MB; - end -= *size_mib; - - return end; -} - void trustzone_region_init(void) { struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c index da08520..914b57e 100644 --- a/src/soc/nvidia/tegra132/cbmem.c +++ b/src/soc/nvidia/tegra132/cbmem.c @@ -23,18 +23,18 @@ void *cbmem_top(void) { static uintptr_t addr; - size_t fb_size; - /* - * FIXME(adurbin): The TZ registers are not accessible to the AVP. - * Therefore, if there is a TZ carveout then it needs to be handled - * here while executing on the AVP in order to properly place the - * CBMEM region. - */ + if (addr == 0) { + uintptr_t begin_mib; + uintptr_t end_mib; - /* CBMEM starts downwards from the framebuffer. */ - if (addr == 0) - addr = framebuffer_attributes(&fb_size); + memory_in_range_below_4gb(&begin_mib, &end_mib); + /* Make sure we consume everything up to 4GIB. */ + if (end_mib == 4096) + addr = ~(uint32_t)0; + else + addr = end_mib << 20; + } - return (void *)(addr << 20UL); + return (void *)addr; } diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index ebe50f5..dc8ba61 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -130,7 +130,4 @@ void mainboard_add_memory_ranges(struct memranges *map); */ void trustzone_region_init(void); -/* Return pointer and size in 1MiB units. */ -uintptr_t framebuffer_attributes(size_t *size_mib); - #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h index 2c21292..a6cd1a4 100644 --- a/src/soc/nvidia/tegra132/include/soc/display.h +++ b/src/soc/nvidia/tegra132/include/soc/display.h @@ -197,6 +197,4 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq); -#define FB_SIZE_MB (32) - #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 2c03db7..25a8e7e 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -47,12 +47,6 @@ static void soc_read_resources(device_t dev) reserved_ram_resource(dev, index++, begin * KiB, size * KiB); } - /* - * TODO: Frame buffer needs to handled as a carveout from the below_4G - * uintptr_t framebuffer_begin = framebuffer_attributes(&framebuffer_size); - */ - - memory_in_range_below_4gb(&begin, &end); size = end - begin; ram_resource(dev, index++, begin * KiB, size * KiB);

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New patch to review for coreboot: 7a44133 arm64: Add verstage support
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9255 -gerrit commit 7a44133833d95bdeafa676cc624f572ed827e755 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 2 16:43:19 2014 -0700 arm64: Add verstage support This stage is not tested on any hardware. BUG=None BRANCH=None TEST=Compiles successfully for rush_ryu and veyron_pinky Original-Change-Id: I6dd266471c815895bb3dd53d34aacc8fe825eeb6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221911 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 907ea2d1f8c9f01d815e8673695dd5271322c7a8) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I617a742d4a387be947086dae33e9a913f742a8d1 --- src/arch/arm64/Makefile.inc | 20 ++++++++++++++++++++ src/arch/arm64/armv8/Makefile.inc | 14 ++++++++++++++ src/arch/arm64/armv8/lib/Makefile.inc | 4 ++++ 3 files changed, 38 insertions(+) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6d23dab..768dd73 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -75,6 +75,26 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(b endif # CONFIG_ARCH_BOOTBLOCK_ARM64 +############################################################################### +# verification stage +############################################################################### + +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) + +$(objcbfs)/verstage.debug: $$(verstage-objs) $$(VB2_LIB) + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(call link,verstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld,--gc-sections) + +verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += div0.c +verstage-y += eabi_compat.c +verstage-y += ../../lib/memset.c +verstage-y += ../../lib/memcpy.c +verstage-y += ../../lib/memmove.c +verstage-y += stages.c + +endif # CONFIG_ARCH_VERSTAGE_ARM64 + ################################################################################ # romstage ################################################################################ diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index ae9f38d..f0c5bbb 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -46,6 +46,20 @@ bootblock-S-ccopts += $(armv8_asm_flags) endif ################################################################################ +## verstage +################################################################################ +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM_V8_64),y) + +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception.c + +verstage-c-ccopts += $(armv8_flags) +verstage-S-ccopts += $(armv8_asm_flags) + +endif + +################################################################################ ## romstage ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index 0622593..7e647bd 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -26,6 +26,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) bootblock-y += $(lib_access) endif +ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y) +verstage-y += $(lib_access) +endif + ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += $(lib_access) endif

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New patch to review for coreboot: 3977e55 veyron_pinky/rk3288: Use KHz, MHz and GHz constants
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9254 -gerrit commit 3977e55646c43e202c7a52a13a3b82515dd1754e Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 6 13:41:28 2014 -0700 veyron_pinky/rk3288: Use KHz, MHz and GHz constants Use the previously added frequency constants. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac --- src/mainboard/google/veyron_pinky/bootblock.c | 4 +-- .../sdram_inf/sdram-ddr3-hynix-2GB.inc | 2 +- .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 2 +- .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- src/soc/rockchip/rk3288/clock.c | 15 +++++----- src/soc/rockchip/rk3288/clock.h | 18 ++++++------ src/soc/rockchip/rk3288/sdram.c | 32 +++++++++++----------- src/soc/rockchip/rk3288/spi.c | 2 +- src/soc/rockchip/rk3288/timer.c | 1 - src/soc/rockchip/rk3288/timer.h | 5 ++-- 10 files changed, 41 insertions(+), 42 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d4f82de..3ed8e27 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc index 409a7ca..07161c0 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ .noc_timing = 0x2891E41D, .noc_activate = 0x5B6, .ddrconfig = 3, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc index 3fdbecf..f5793d1 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x30B25564, .noc_activate = 0x627, .ddrconfig = 3, - .ddr_freq = 666000000, + .ddr_freq = 666*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 315e542..f42f1b1 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, .ddrconfig = 2, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, .stride = 9, diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 8202ef2..0ce3f94 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -65,8 +65,8 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PLL_DIVISORS(hz, _nr, _no) {\ - .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\ - _Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / (24*MHz)), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / (24*MHz)) * (24*MHz) /\ (_nr * _no) == hz,\ #hz "Hz cannot be hit with PLL divisors in " __FILE__); @@ -337,10 +337,10 @@ void rkclk_configure_ddr(unsigned int hz) { struct pll_div dpll_cfg; - if (hz <= 150000000) { + if (hz <= 150*MHz) { dpll_cfg.nr = 3; dpll_cfg.no = 8; - } else if (hz <= 540000000) { + } else if (hz <= 540*MHz) { dpll_cfg.nr = 6; dpll_cfg.no = 4; } else { @@ -348,10 +348,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg.no = 1; } - dpll_cfg.nf = (hz / 1000 * dpll_cfg.nr * dpll_cfg.no) / 24000; - assert(dpll_cfg.nf < 4096 - && hz == dpll_cfg.nf * 24000 / (dpll_cfg.nr * dpll_cfg.no) - * 1000); + dpll_cfg.nf = (hz/KHz * dpll_cfg.nr * dpll_cfg.no) / (24*KHz); + assert(dpll_cfg.nf < 4096 && hz == dpll_cfg.nf * (24*KHz) / + (dpll_cfg.nr * dpll_cfg.no) * 1000); /* pll enter slow-mode */ writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), &cru_ptr->cru_mode_con); diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index b206baa..7a1dba0 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -22,17 +22,17 @@ #include "addressmap.h" -#define APLL_HZ 816000000 -#define GPLL_HZ 594000000 -#define CPLL_HZ 384000000 +#define APLL_HZ (816*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) -#define PD_BUS_ACLK_HZ 148500000 -#define PD_BUS_HCLK_HZ 148500000 -#define PD_BUS_PCLK_HZ 74250000 +#define PD_BUS_ACLK_HZ (148500*KHz) +#define PD_BUS_HCLK_HZ (148500*KHz) +#define PD_BUS_PCLK_HZ (74250*KHz) -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 +#define PERI_ACLK_HZ (148500*KHz) +#define PERI_HCLK_HZ (148500*KHz) +#define PERI_PCLK_HZ (74250*KHz) void rkclk_init(void); void rkclk_configure_spi(unsigned int bus, unsigned int hz); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 6c0c7fd..2b0a396 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -538,8 +538,8 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 freq) { int i; - if (freq <= 250000000) { - if (freq <= 150000000) + if (freq <= 250*MHz) { + if (freq <= 150*MHz) clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); @@ -651,19 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) writel(sdram_params->noc_activate, &msch_regs->activate); writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), &msch_regs->devtodev); - writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000 - * 5120, 1000)) - | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000 - * 50, 1000)) + writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz + * 5120, 1000)) + | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz + * 50, 1000)) | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]); - writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000 - * 500000, 1000)) - | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000 - * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000 - * 200000, 1000)) - | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000 - * 1000, 1000)), &ddr_publ_regs->ptr[2]); + writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz + * 500000, 1000)) + | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz + * 400, 1000)), &ddr_publ_regs->ptr[1]); + writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz + * 200000, 1000)) + | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz + * 1000, 1000)), &ddr_publ_regs->ptr[2]); switch (sdram_params->dramtype) { case LPDDR3: @@ -971,9 +971,9 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) printk(BIOS_INFO, "Starting SDRAM initialization...\n"); if ((sdram_params->dramtype == DDR3 - && sdram_params->ddr_freq > 800000000) + && sdram_params->ddr_freq > 800*MHz) || (sdram_params->dramtype == LPDDR3 - && sdram_params->ddr_freq > 533000000)) + && sdram_params->ddr_freq > 533*MHz)) die("SDRAM frequency is to high!"); rkclk_configure_ddr(sdram_params->ddr_freq); diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 431b2d3..a74d423 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -36,7 +36,7 @@ struct rockchip_spi_slave { }; #define SPI_TIMEOUT_US 1000 -#define SPI_SRCCLK_HZ 99000000 +#define SPI_SRCCLK_HZ (99*MHz) #define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[3] = { diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 3a2c34d..91186cc 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -18,7 +18,6 @@ */ #include <console/console.h> -#include <timer.h> #include <delay.h> #include <arch/io.h> #include "timer.h" diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h index 1820f56..9f1fbaf 100644 --- a/src/soc/rockchip/rk3288/timer.h +++ b/src/soc/rockchip/rk3288/timer.h @@ -21,10 +21,11 @@ #define __SOC_ROCKCHIP_RK3288_TIMER_H__ #include <inttypes.h> +#include <timer.h> #include "addressmap.h" -#define SYS_CLK_FREQ 24000000 -static const u32 clocks_per_usec = SYS_CLK_FREQ/1000000; +#define SYS_CLK_FREQ (24*MHz) +static const u32 clocks_per_usec = SYS_CLK_FREQ/USECS_PER_SEC; struct rk3288_timer { u32 timer_load_count0;

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New patch to review for coreboot: 57bd777 stddef: Add KHz, MHz and GHz constants
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9253 -gerrit commit 57bd777c3b5bbaf87450b29eab808f99941ee5ce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 2 15:43:12 2015 -0500 stddef: Add KHz, MHz and GHz constants This patch adds some simple constants to more easily write and do math with frequencies, analogous to the existing KiB, MiB and GiB constants for sizes. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1e708b0aa53533c9ab999793ca2273c6dc68b5f6 --- src/include/stddef.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/stddef.h b/src/include/stddef.h index 60e3459..e79b90a 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -26,6 +26,10 @@ typedef unsigned int wint_t; /* Could we ever run into this one? I hope we get this much memory! */ #define TiB (1<<40) +#define KHz (1000) +#define MHz (1000*KHz) +#define GHz (1000*MHz) + #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) #define check_member(structure, member, offset) _Static_assert( \

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New patch to review for coreboot: 520a3fc armv4: Add verstage to armv4
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9252 -gerrit commit 520a3fcb6d3136935b9dd4c575da61134af1fd21 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 2 16:31:18 2014 -0700 armv4: Add verstage to armv4 BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I7735a2148da5330f220bd9a87b09e9fe3e37ffd1 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221322 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5e43dfe1aab813f45f1123b0e2432cdab5738d87) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: If3d89ab79bae6d8f1b6f2d89b7693a79dca02476 --- src/arch/arm/armv4/Makefile.inc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index b234fff..8557451 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -40,6 +40,17 @@ bootblock-S-ccopts += $(armv4_flags) endif # CONFIG_ARCH_BOOTBLOCK_ARMV4 +################################################################################ +## Verstage +################################################################################ + +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM_V4),y) +verstage-c-ccopts += $(armv4_flags) +verstage-S-ccopts += $(armv4_flags) + +verstage-y += cache.c +endif # CONFIG_ARCH_VERSTAGE_ARM_V4 + ############################################################################### # romstage ###############################################################################

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New patch to review for coreboot: 8f3a944 armv7: Add config option guard for verstage class
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9251 -gerrit commit 8f3a944697030c194bff11556a78c03328e69089 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 2 16:27:52 2014 -0700 armv7: Add config option guard for verstage class Add files to verstage class depending upon value of CONFIG_ARCH_VERSTAGE_ARM_V7. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I60fb8390abd9d378e38511d4f4ac323b43450232 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221321 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 4889cb73b0579155c083bb5fa2895b4d52ab0a56) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iea788ed72344343b2e7a3d91cd7f27ce20f4f177 --- src/arch/arm/armv7/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index c22c8c6..dac4276 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -50,6 +50,8 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 ## verification stage ################################################################################ +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM_V7),y) + verstage-c-ccopts += $(armv7_flags) verstage-S-ccopts += $(armv7_asm_flags) verstage-y += cache.c @@ -58,6 +60,8 @@ verstage-y += exception.c verstage-y += exception_asm.S verstage-y += mmu.c +endif # CONFIG_ARCH_VERSTAGE_ARMV7 + ############################################################################### # romstage ###############################################################################

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Patch set updated for coreboot: 249e650 tegra124: use known-good drive for fast-train only
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9248 -gerrit commit 249e650bba3f33265021b1d288f8836cdf7bef26 Author: Neil Chen <neilc(a)nvidia.com> Date: Wed Sep 24 10:41:08 2014 +0800 tegra124: use known-good drive for fast-train only A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 --- src/soc/nvidia/tegra124/dp.c | 3 +++ src/soc/nvidia/tegra124/sor.c | 48 ++++++++++++++++++++++--------------------- src/soc/nvidia/tegra124/sor.h | 1 + 3 files changed, 29 insertions(+), 23 deletions(-) diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 9ff50ea..35a5c73 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -1254,6 +1254,9 @@ static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp, printk(BIOS_ERR, "dp: full link training failed\n"); return ret; } + } else { + /* set to a known-good drive setting if fast link succeeded */ + tegra_dc_sor_set_voltage_swing(&dp->sor); } /* Everything goes well, double check the link config */ diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 1f9df6c..3eaae0e 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -832,11 +832,34 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, 0xf0, 0x0); } -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) { - u32 pad_ctrl = 0; u32 drive_current = 0; u32 pre_emphasis = 0; + + /* Set to a known-good pre-calibrated setting */ + switch (sor->link_cfg->link_bw) { + case SOR_LINK_SPEED_G1_62: + case SOR_LINK_SPEED_G2_7: + drive_current = 0x13131313; + pre_emphasis = 0; + break; + case SOR_LINK_SPEED_G5_4: + printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); + default: + printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", + sor->link_cfg->link_bw); + return; + } + + tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), + drive_current); + tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); +} + +void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) +{ + u32 pad_ctrl = 0; int err = 0; switch (sor->link_cfg->lane_count) { @@ -873,27 +896,6 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) "Wait for lane power down failed: %d\n", err); return; } - - /* Set to a known-good pre-calibrated setting */ - switch (sor->link_cfg->link_bw) { - case SOR_LINK_SPEED_G1_62: - case SOR_LINK_SPEED_G2_7: - drive_current = 0x13131313; - pre_emphasis = 0; - break; - case SOR_LINK_SPEED_G5_4: - drive_current = 0x19191919; - pre_emphasis = 0x09090909; - break; - default: - printk(BIOS_ERR, "Invalid sor link bandwidth: %d\n", - sor->link_cfg->link_bw); - return; - } - - tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), - drive_current); - tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); } void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h index 4e4211e..569cdb9 100644 --- a/src/soc/nvidia/tegra124/sor.h +++ b/src/soc/nvidia/tegra124/sor.h @@ -920,6 +920,7 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor); void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,

1 0

Patch set updated for coreboot: ab14a68 rk3288: Pass SPI bus speed in as parameter to init function
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9245 -gerrit commit ab14a6873ed3494076dd1a41cdef09dcb477a9e4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:48:40 2014 -0700 rk3288: Pass SPI bus speed in as parameter to init function This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c --- src/mainboard/google/veyron_pinky/bootblock.c | 4 ++-- src/soc/rockchip/rk3288/spi.c | 8 ++------ src/soc/rockchip/rk3288/spi.h | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 5e22d6e..d4f82de 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 844d692..3fb7291 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,7 +33,6 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int speed_hz; unsigned int fifo_size; }; @@ -47,13 +46,11 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .speed_hz = 9000000, .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, { @@ -62,7 +59,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, @@ -110,7 +106,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) writel(clk_div, &regs->baudr); } -void rockchip_spi_init(unsigned int bus) +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; struct rockchip_spi *regs = espi->regs; @@ -118,7 +114,7 @@ void rockchip_spi_init(unsigned int bus) rkclk_configure_spi(bus, SPI_SRCCLK_HZ); rockchip_spi_enable_chip(regs, 0); - rockchip_spi_set_clk(regs, espi->speed_hz); + rockchip_spi_set_clk(regs, speed_hz); /* Operation Mode */ ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h index c6880c2..bba38ef 100644 --- a/src/soc/rockchip/rk3288/spi.h +++ b/src/soc/rockchip/rk3288/spi.h @@ -199,6 +199,6 @@ check_member(rockchip_spi, rxdr, 0x800); int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, size_t buffer_size); -void rockchip_spi_init(unsigned int bus); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); #endif

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coreboot-gerrit April 2015