coreboot-gerrit April 2015

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New patch to review for coreboot: 1df689e nyan*: add support of full link training
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9247 -gerrit commit 1df689e0ac9353b30b97ee17fb5866ff5ac21d8d Author: Neil Chen <neilc(a)nvidia.com> Date: Tue Sep 23 17:41:59 2014 +0800 nyan*: add support of full link training The original dp driver supports only fast link training and a special drive setting is used for the link training sequence. This might not be accepted by all panels. The better way is to go through full link training sequence to negotiate for a best drive setting. With the change, dp driver will try fast link training first, this is same as before. If it fails in fast link training, will try full link training. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219543 Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 24966517d41252384af3c2784def36aebad42434) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c --- src/soc/nvidia/tegra/displayport.h | 160 +++++++++++++ src/soc/nvidia/tegra124/dp.c | 477 +++++++++++++++++++++++++++++++++---- src/soc/nvidia/tegra124/sor.c | 52 ++++ src/soc/nvidia/tegra124/sor.h | 7 + 4 files changed, 652 insertions(+), 44 deletions(-) diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index 338ab77..5bf8423 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -138,6 +138,146 @@ #define DP_AUX_TIMEOUT_MS 40 #define DP_DPCP_RETRY_SLEEP_NS 400 +static const u32 tegra_dp_vs_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ + {0x1e, 0x25, 0x2d}, /* L1 */ + {0x28, 0x32}, /* L2 */ + {0x3c}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x12, 0x17, 0x1b, 0x25}, + {0x1c, 0x23, 0x2a}, + {0x25, 0x2f}, + {0x39}, + }, + + /* postcursor2 L2 */ + { + {0x12, 0x16, 0x1a, 0x22}, + {0x1b, 0x20, 0x27}, + {0x24, 0x2d}, + {0x36}, + }, + + /* postcursor2 L3 */ + { + {0x11, 0x14, 0x17, 0x1f}, + {0x19, 0x1e, 0x24}, + {0x22, 0x2a}, + {0x32}, + }, +}; + +static const u32 tegra_dp_pe_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ + {0x00, 0x0f, 0x1e}, /* L1 */ + {0x00, 0x14}, /* L2 */ + {0x00}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, + + /* postcursor2 L2 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, + + /* postcursor2 L3 */ + { + {0x00, 0x0a, 0x14, 0x28}, + {0x00, 0x0f, 0x1e}, + {0x00, 0x14}, + {0x00}, + }, +}; + +static const u32 tegra_dp_pc_regs[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ + {0x00, 0x00, 0x00}, /* L1 */ + {0x00, 0x00}, /* L2 */ + {0x00}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x02, 0x02, 0x04, 0x05}, + {0x02, 0x04, 0x05}, + {0x04, 0x05}, + {0x05}, + }, + + /* postcursor2 L2 */ + { + {0x04, 0x05, 0x08, 0x0b}, + {0x05, 0x09, 0x0b}, + {0x08, 0x0a}, + {0x0b}, + }, + + /* postcursor2 L3 */ + { + {0x05, 0x09, 0x0b, 0x12}, + {0x09, 0x0d, 0x12}, + {0x0b, 0x0f}, + {0x12}, + }, +}; + +static const u32 tegra_dp_tx_pu[][4][4] = { + /* postcursor2 L0 */ + { + /* pre-emphasis: L0, L1, L2, L3 */ + {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ + {0x30, 0x40, 0x60}, /* L1 */ + {0x40, 0x60}, /* L2 */ + {0x60}, /* L3 */ + }, + + /* postcursor2 L1 */ + { + {0x20, 0x20, 0x30, 0x50}, + {0x30, 0x40, 0x50}, + {0x40, 0x50}, + {0x60}, + }, + + /* postcursor2 L2 */ + { + {0x20, 0x20, 0x30, 0x40}, + {0x30, 0x30, 0x40}, + {0x40, 0x50}, + {0x60}, + }, + + /* postcursor2 L3 */ + { + {0x20, 0x20, 0x20, 0x40}, + {0x30, 0x30, 0x40}, + {0x40, 0x40}, + {0x60}, + }, +}; + enum { driveCurrent_Level0 = 0, driveCurrent_Level1 = 1, @@ -160,6 +300,20 @@ enum { postCursor2_Supported }; +static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) +{ + return (vs < (driveCurrent_Level3 - pe)) ? 0 : 1; +} + +static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) +{ + return (pe < (preEmphasis_Level3 - vs)) ? 0 : 1; +} + +static inline int tegra_dp_is_max_pc(u32 pc) +{ + return (pc < postCursor2_Level3) ? 0 : 1; +} /* the +10ms is the time for power rail going up from 10-90% or 90%-10% on powerdown */ @@ -200,6 +354,7 @@ struct tegra_dc_dp_data { #define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001) #define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002) #define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004) +#define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001 << 6) #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7) #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7) #define NV_DPCD_MAX_DOWNSPREAD (0x00000003) @@ -212,6 +367,7 @@ struct tegra_dc_dp_data { #define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001) #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1) #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1) +#define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) #define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100) #define NV_DPCD_LANE_COUNT_SET (0x00000101) #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7) @@ -230,8 +386,10 @@ struct tegra_dc_dp_data { #define NV_DPCD_TRAINING_LANE3_SET (0x00000106) #define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) +#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) +#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) #define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4) #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4) @@ -246,8 +404,10 @@ struct tegra_dc_dp_data { #define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110) #define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2) +#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0x00000000 << 2) #define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6) +#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0x00000000 << 6) #define NV_DPCD_SINK_COUNT (0x00000200) #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201) #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1) diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 00474a8..9ff50ea 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -30,6 +30,11 @@ #include "sor.h" #include <soc/nvidia/tegra/displayport.h> +enum { + DP_LT_SUCCESS = 0, + DP_LT_FAILED = -1, +}; + struct tegra_dc_dp_data dp_data; static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) @@ -443,6 +448,34 @@ static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp, link_cfg->vblank_sym); } +static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, + struct tegra_dc_dp_link_config *cfg) +{ + + switch (cfg->link_bw){ + case SOR_LINK_SPEED_G1_62: + if (cfg->max_link_bw > SOR_LINK_SPEED_G1_62) + cfg->link_bw = SOR_LINK_SPEED_G2_7; + cfg->lane_count /= 2; + break; + case SOR_LINK_SPEED_G2_7: + cfg->link_bw = SOR_LINK_SPEED_G1_62; + break; + case SOR_LINK_SPEED_G5_4: + if (cfg->lane_count == 1) { + cfg->link_bw = SOR_LINK_SPEED_G2_7; + cfg->lane_count = cfg->max_lane_count; + } else + cfg->lane_count /= 2; + break; + default: + printk(BIOS_ERR,"dp: Error link rate %d\n", cfg->link_bw); + return DP_LT_FAILED; + } + + return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; +} + /* Calcuate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, @@ -624,6 +657,8 @@ static int tegra_dc_dp_init_max_link_cfg( CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT, &dpcd_data)); link_cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; + link_cfg->tps3_supported = (dpcd_data & + NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0; link_cfg->support_enhanced_framing = (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? @@ -634,6 +669,9 @@ static int tegra_dc_dp_init_max_link_cfg( link_cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT)? 1 : 0; + CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL, + &link_cfg->aux_rd_interval)); + CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, &link_cfg->max_link_bw)); @@ -732,6 +770,392 @@ static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp, return 0; } +static int tegra_dp_channel_eq_status(struct tegra_dc_dp_data *dp) +{ + u32 cnt; + u32 n_lanes = dp->link_cfg.lane_count; + u8 data; + u8 ce_done = 1; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt), &data); + + if (n_lanes == 1) { + ce_done = (data & + (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) && + (data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)); + break; + } else if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) || + !(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) || + !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) || + !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT))) + return 0; + } + + if (ce_done) { + tegra_dc_dp_dpcd_read(dp, NV_DPCD_LANE_ALIGN_STATUS_UPDATED, &data); + if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES)) + ce_done = 0; + } + + return ce_done; +} + +static u8 tegra_dp_clock_recovery_status(struct tegra_dc_dp_data *dp) +{ + u32 cnt; + u32 n_lanes = dp->link_cfg.lane_count; + u8 data_ptr; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + tegra_dc_dp_dpcd_read(dp, + (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr); + + if (n_lanes == 1) + return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0; + else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) || + !(data_ptr & + (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES))) + return 0; + } + + return 1; +} + +static void tegra_dp_lt_adjust(struct tegra_dc_dp_data *dp, + u32 pe[4], u32 vs[4], u32 pc[4], + u8 pc_supported) +{ + size_t cnt; + u8 data_ptr; + u32 n_lanes = dp->link_cfg.lane_count; + + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + tegra_dc_dp_dpcd_read(dp, + (NV_DPCD_LANE0_1_ADJUST_REQ + cnt), &data_ptr); + pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >> + NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT; + vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >> + NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT; + pe[1 + 2 * cnt] = + (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >> + NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT; + vs[1 + 2 * cnt] = + (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >> + NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT; + } + if (pc_supported) { + tegra_dc_dp_dpcd_read(dp, + NV_DPCD_ADJUST_REQ_POST_CURSOR2, &data_ptr); + for (cnt = 0; cnt < n_lanes; cnt++) { + pc[cnt] = (data_ptr >> + NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) & + NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK; + } + } +} + +static inline u32 tegra_dp_wait_aux_training(struct tegra_dc_dp_data *dp, + u8 is_clk_recovery) +{ + if (!dp->link_cfg.aux_rd_interval) + is_clk_recovery ? udelay(200) : + udelay(500); + else + mdelay(dp->link_cfg.aux_rd_interval * 4); + + return dp->link_cfg.aux_rd_interval; +} + +static void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes) +{ + u8 data = (tp == training_pattern_disabled) + ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F) + : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T); + + tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, tp, &dp->link_cfg); + tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, data); +} + +static int tegra_dp_link_config(struct tegra_dc_dp_data *dp, + const struct tegra_dc_dp_link_config *link_cfg) +{ + u8 dpcd_data; + u32 retry; + + if (link_cfg->lane_count == 0) { + printk(BIOS_ERR, "dp: error: lane count is 0. " + "Can not set link config.\n"); + return DP_LT_FAILED; + } + + /* Set power state if it is not in normal level */ + if(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data)) + return DP_LT_FAILED; + + if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) { + dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL; + + /* DP spec requires 3 retries */ + for (retry = 3; retry > 0; --retry){ + if (tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER, dpcd_data)) + break; + if (retry == 1){ + printk(BIOS_ERR, "dp: Failed to set DP panel power\n"); + return DP_LT_FAILED; + } + } + } + + /* Enable ASSR if possible */ + if (link_cfg->alt_scramber_reset_cap) + if(tegra_dc_dp_set_assr(dp, 1)) + return DP_LT_FAILED; + + if (tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw)) { + printk(BIOS_ERR, "dp: Failed to set link bandwidth\n"); + return DP_LT_FAILED; + } + if (tegra_dp_set_lane_count(dp, link_cfg)) { + printk(BIOS_ERR, "dp: Failed to set lane count\n"); + return DP_LT_FAILED; + } + tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none, + link_cfg); + return DP_LT_SUCCESS; +} + +static int tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, + struct tegra_dc_dp_link_config *cfg) +{ + struct tegra_dc_dp_link_config tmp_cfg; + + tmp_cfg = dp->link_cfg; + cfg->is_valid = 0; + + if (_tegra_dp_lower_link_config(dp, cfg)) + goto fail; + + if (tegra_dc_dp_calc_config(dp, dp->dc->config, cfg)) + goto fail; + tegra_dp_link_config(dp, cfg); + + return DP_LT_SUCCESS; +fail: + dp->link_cfg = tmp_cfg; + tegra_dp_link_config(dp, &tmp_cfg); + return DP_LT_FAILED; +} + +static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp, + u32 pe[4], u32 vs[4], u32 pc[4]) +{ + struct tegra_dc_sor_data *sor = &dp->sor; + u32 n_lanes = dp->link_cfg.lane_count; + u8 pc_supported = dp->link_cfg.tps3_supported; + u32 cnt; + u32 val; + + for (cnt = 0; cnt < n_lanes; cnt++) { + u32 mask = 0; + u32 pe_reg, vs_reg, pc_reg; + u32 shift = 0; + + switch (cnt) { + case 0: + mask = NV_SOR_PR_LANE2_DP_LANE0_MASK; + shift = NV_SOR_PR_LANE2_DP_LANE0_SHIFT; + break; + case 1: + mask = NV_SOR_PR_LANE1_DP_LANE1_MASK; + shift = NV_SOR_PR_LANE1_DP_LANE1_SHIFT; + break; + case 2: + mask = NV_SOR_PR_LANE0_DP_LANE2_MASK; + shift = NV_SOR_PR_LANE0_DP_LANE2_SHIFT; + break; + case 3: + mask = NV_SOR_PR_LANE3_DP_LANE3_MASK; + shift = NV_SOR_PR_LANE3_DP_LANE3_SHIFT; + break; + default: + printk(BIOS_ERR, + "dp: incorrect lane cnt\n"); + } + + pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]]; + + tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift, + vs_reg << shift, pc_reg << shift, pc_supported); + } + + tegra_dp_disable_tx_pu(&dp->sor); + udelay(20); + + for (cnt = 0; cnt < n_lanes; cnt++) { + u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]); + u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]); + + val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) | + (max_vs_flag ? + NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T : + NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) | + (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | + (max_pe_flag ? + NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T : + NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F); + tegra_dc_dp_dpcd_write(dp, + (NV_DPCD_TRAINING_LANE0_SET + cnt), val); + } + + if (pc_supported) { + for (cnt = 0; cnt < n_lanes / 2; cnt++) { + u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]); + u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]); + val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) | + (max_pc_flag0 ? + NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T : + NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) | + (pc[cnt + 1] << + NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) | + (max_pc_flag1 ? + NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T : + NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F); + tegra_dc_dp_dpcd_write(dp, + (NV_DPCD_TRAINING_LANE0_1_SET2 + cnt), val); + } + } +} + +static int _tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, u32 pe[4], + u32 vs[4], u32 pc[4], u8 pc_supported, + u32 n_lanes) +{ + u32 retry_cnt; + + for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) { + if (retry_cnt){ + tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported); + tegra_dp_lt_config(dp, pe, vs, pc); + } + + tegra_dp_wait_aux_training(dp, 0); + + if (!tegra_dp_clock_recovery_status(dp)) { + printk(BIOS_ERR,"dp: CR failed in channel EQ sequence!\n"); + break; + } + + if (tegra_dp_channel_eq_status(dp)) + return DP_LT_SUCCESS; + } + + return DP_LT_FAILED; +} + +static int tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, + u32 pe[4], u32 vs[4], u32 pc[4]) +{ + u32 n_lanes = dp->link_cfg.lane_count; + u8 pc_supported = dp->link_cfg.tps3_supported; + int err; + u32 tp_src = training_pattern_2; + + if (pc_supported) + tp_src = training_pattern_3; + + tegra_dp_tpg(dp, tp_src, n_lanes); + + err = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes); + + tegra_dp_tpg(dp, training_pattern_disabled, n_lanes); + + return err; +} + +static int _tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, u32 pe[4], + u32 vs[4], u32 pc[4], u8 pc_supported, + u32 n_lanes) +{ + u32 vs_temp[4]; + u32 retry_cnt = 0; + + do { + tegra_dp_lt_config(dp, pe, vs, pc); + tegra_dp_wait_aux_training(dp, 1); + + if (tegra_dp_clock_recovery_status(dp)) + return DP_LT_SUCCESS; + + memcpy(vs_temp, vs, sizeof(vs_temp)); + tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported); + + if (memcmp(vs_temp, vs, sizeof(vs_temp))) + retry_cnt = 0; + else + ++retry_cnt; + } while (retry_cnt < 5); + + return DP_LT_FAILED; +} + +static int tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, + u32 pe[4], u32 vs[4], u32 pc[4]) +{ + u32 n_lanes = dp->link_cfg.lane_count; + u8 pc_supported = dp->link_cfg.tps3_supported; + int err; + + tegra_dp_tpg(dp, training_pattern_1, n_lanes); + + err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes); + if (err < 0) + tegra_dp_tpg(dp, training_pattern_disabled, n_lanes); + + return err; +} + +static int tegra_dc_dp_full_link_training(struct tegra_dc_dp_data *dp) +{ + struct tegra_dc_sor_data *sor = &dp->sor; + int err; + u32 pe[4], vs[4], pc[4]; + + tegra_sor_precharge_lanes(sor); + +retry_cr: + memset(pe, preEmphasis_Disabled, sizeof(pe)); + memset(vs, driveCurrent_Level0, sizeof(vs)); + memset(pc, postCursor2_Level0, sizeof(pc)); + + err = tegra_dp_clk_recovery(dp, pe, vs, pc); + if (err != DP_LT_SUCCESS) { + if (!tegra_dp_lower_link_config(dp, &dp->link_cfg)) + goto retry_cr; + + printk(BIOS_ERR, "dp: clk recovery failed\n"); + goto fail; + } + + err = tegra_dp_channel_eq(dp, pe, vs, pc); + if (err != DP_LT_SUCCESS) { + if (!tegra_dp_lower_link_config(dp, &dp->link_cfg)) + goto retry_cr; + + printk(BIOS_ERR, + "dp: channel equalization failed\n"); + goto fail; + } + + tegra_dc_dp_dump_link_cfg(dp, &dp->link_cfg); + + return 0; + +fail: + return err; +} /* * All link training functions are ported from kernel dc driver. * See more details at drivers/video/tegra/dc/dp.c @@ -813,59 +1237,23 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp, return 0; } -static int tegra_dp_link_config(struct tegra_dc_dp_data *dp, +static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp, const struct tegra_dc_dp_link_config *link_cfg) { - u8 dpcd_data; u8 link_bw; u8 lane_count; - u32 retry; int ret; - if (link_cfg->lane_count == 0) { - printk(BIOS_ERR, "dp: error: lane count is 0. " - "Can not set link config.\n"); - return -1; - } - - /* Set power state if it is not in normal level */ - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data)); - if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) { - dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL; - retry = 3; /* DP spec requires 3 retries */ - do { - ret = tegra_dc_dp_dpcd_write(dp, - NV_DPCD_SET_POWER, dpcd_data); - } while ((--retry > 0) && ret); - if (ret) { - printk(BIOS_ERR, - "dp: Failed to set DP panel power\n"); - return ret; - } - } - - /* Enable ASSR if possible */ - if (link_cfg->alt_scramber_reset_cap) - CHECK_RET(tegra_dc_dp_set_assr(dp, 1)); - - ret = tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw); - if (ret) { - printk(BIOS_ERR, "dp: Failed to set link bandwidth\n"); - return ret; - } - ret = tegra_dp_set_lane_count(dp, link_cfg); - if (ret) { - printk(BIOS_ERR, "dp: Failed to set lane count\n"); - return ret; - } - tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none, - link_cfg); - /* Now do the fast link training for eDP */ ret = tegra_dc_dp_fast_link_training(dp, link_cfg); if (ret) { printk(BIOS_ERR, "dp: fast link training failed\n"); - return ret; + + /* Try full link training then */ + if (tegra_dc_dp_full_link_training(dp)){ + printk(BIOS_ERR, "dp: full link training failed\n"); + return ret; + } } /* Everything goes well, double check the link config */ @@ -907,7 +1295,8 @@ static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp, * set to max link config */ if ((!tegra_dc_dp_calc_config(dp, config, &temp_cfg)) && - (!(tegra_dp_link_config(dp, &temp_cfg)))) + (!tegra_dp_link_config(dp, &temp_cfg)) && + (!tegra_dp_do_link_training(dp, &temp_cfg))) /* the max link cfg is doable */ memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg)); diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 2c059bf..1f9df6c 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -79,6 +79,28 @@ static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, reg, reg_val); } +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor) +{ + tegra_sor_write_field(sor, + NV_SOR_DP_PADCTL(sor->portnum), + NV_SOR_DP_PADCTL_TX_PU_MASK, + NV_SOR_DP_PADCTL_TX_PU_DISABLE); +} + +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported) +{ + tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum), + mask, pe_reg); + tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum), + mask, vs_reg); + if (pc_supported) { + tegra_sor_write_field( + sor, NV_SOR_POSTCURSOR(sor->portnum), + mask, pc_reg); + } +} + static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) { @@ -873,3 +895,33 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) drive_current); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); } + +void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) +{ + const struct tegra_dc_dp_link_config *cfg = sor->link_cfg; + u32 val = 0; + + switch (cfg->lane_count) { + case 4: + val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | + NV_SOR_DP_PADCTL_PD_TXD_2_NO); + /* fall through */ + case 2: + val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; + /* fall through */ + case 1: + val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; + break; + default: + printk(BIOS_ERR, + "dp: invalid lane number %d\n", cfg->lane_count); + return; + } + + tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), + (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), + (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT)); + udelay(100); + tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), + (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0); +} diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h index bf62868..4e4211e 100644 --- a/src/soc/nvidia/tegra124/sor.h +++ b/src/soc/nvidia/tegra124/sor.h @@ -695,6 +695,7 @@ #define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22) #define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22) #define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define NV_SOR_DP_PADCTL_TX_PU_MASK (1 << 22) #define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20) #define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20) #define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16) @@ -878,6 +879,8 @@ struct tegra_dc_dp_link_config { u32 drive_current; u32 preemphasis; u32 postcursor; + u8 aux_rd_interval; + u8 tps3_supported; }; /* TODO: just pull these up into one struct? Need to see how this impacts @@ -917,4 +920,8 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); #endif /*__TEGRA124_SOR_H__ */

1 0

Patch set updated for coreboot: 5590a5b rk3288: remove duplicated #define
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9244 -gerrit commit 5590a5bd8ed3ba488358a006ff63904b42338341 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 2 14:39:25 2015 -0500 rk3288: remove duplicated #define I'm not sure how the build didn't fail before. In either case remove the duplication. Change-Id: I764774f2b8a5839512af3f054b844a1a86efdb45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 59a32db..8202ef2 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -159,7 +159,6 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); */ #define PERI_ACLK_DIV_SHIFT (0x0) #define PERI_ACLK_DIV_MSK (0x1F) -#define PERI_ACLK_DIV_SHIFT (0) /*******************CLKSEL37 BITS***************************/ #define L2_DIV_MSK (0x7)

1 0

Patch set updated for coreboot: d75d774 rk3288: Pass SPI bus speed in as parameter to init function
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9245 -gerrit commit d75d7748b3635001e0eda6860b3fadaf7af0d1f7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:48:40 2014 -0700 rk3288: Pass SPI bus speed in as parameter to init function This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c --- src/mainboard/google/veyron_pinky/bootblock.c | 4 ++-- src/soc/rockchip/rk3288/spi.c | 8 ++------ src/soc/rockchip/rk3288/spi.h | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 5e22d6e..d4f82de 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 844d692..3fb7291 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,7 +33,6 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int speed_hz; unsigned int fifo_size; }; @@ -47,13 +46,11 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .speed_hz = 9000000, .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, { @@ -62,7 +59,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, @@ -110,7 +106,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) writel(clk_div, &regs->baudr); } -void rockchip_spi_init(unsigned int bus) +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; struct rockchip_spi *regs = espi->regs; @@ -118,7 +114,7 @@ void rockchip_spi_init(unsigned int bus) rkclk_configure_spi(bus, SPI_SRCCLK_HZ); rockchip_spi_enable_chip(regs, 0); - rockchip_spi_set_clk(regs, espi->speed_hz); + rockchip_spi_set_clk(regs, speed_hz); /* Operation Mode */ ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h index c6880c2..bba38ef 100644 --- a/src/soc/rockchip/rk3288/spi.h +++ b/src/soc/rockchip/rk3288/spi.h @@ -199,6 +199,6 @@ check_member(rockchip_spi, rxdr, 0x800); int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, size_t buffer_size); -void rockchip_spi_init(unsigned int bus); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); #endif

1 0

Patch set updated for coreboot: b45b2c6 rk3288: Replace SPI fifo_size with constant
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9246 -gerrit commit b45b2c6664c3fb1ffcc3bbb8eba4a09bb1a42a7b Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 18:54:55 2014 -0700 rk3288: Replace SPI fifo_size with constant rockchip_spi_slave has a fifo_size member which doesn't change. This just replaces the struct member with a #define. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9 Original-Reviewed-on: https://chromium-review.googlesource.com/220471 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be --- src/soc/rockchip/rk3288/spi.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 3fb7291..431b2d3 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,11 +33,11 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int fifo_size; }; #define SPI_TIMEOUT_US 1000 #define SPI_SRCCLK_HZ 99000000 +#define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[3] = { { @@ -46,12 +46,10 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .fifo_size = 32, }, { .slave = { @@ -59,7 +57,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .fifo_size = 32, }, }; @@ -108,8 +105,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { - struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; - struct rockchip_spi *regs = espi->regs; + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int ctrlr0 = 0; rkclk_configure_spi(bus, SPI_SRCCLK_HZ); @@ -145,9 +141,9 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) writel(ctrlr0, &regs->ctrlr0); - /*fifo depth */ - writel(espi->fifo_size / 2 - 1, &regs->txftlr); - writel(espi->fifo_size / 2 - 1, &regs->rxftlr); + /* fifo depth */ + writel(SPI_FIFO_DEPTH / 2 - 1, &regs->txftlr); + writel(SPI_FIFO_DEPTH / 2 - 1, &regs->rxftlr); } int spi_claim_bus(struct spi_slave *slave) @@ -182,7 +178,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout, unsigned int bytes_remaining; uint8_t *p; struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - struct rockchip_spi_slave *espi = to_rockchip_spi(slave); if (dout) { len = sout; @@ -196,8 +191,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout, SPI_TMOD_TO << SPI_TMOD_OFFSET); writel(1, &regs->spienr);/*enable spi */ while (bytes_remaining) { - if ((readl(&regs->txflr) & 0x3f) - < espi->fifo_size) { + if ((readl(&regs->txflr) & 0x3f) < SPI_FIFO_DEPTH) { writel(*p++, &regs->txdr); bytes_remaining--; }

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Patch set updated for coreboot: 62613cf rk3288/pinky: Move uart address to mainboard Kconfig
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9242 -gerrit commit 62613cf0a0ad24f430f1caf9ca1c6f0f5e2f1310 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 2 15:37:46 2014 -0700 rk3288/pinky: Move uart address to mainboard Kconfig Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 --- src/mainboard/google/veyron_pinky/Kconfig | 5 +++++ src/soc/rockchip/rk3288/Kconfig | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 7f981b4..97a0097 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -81,4 +81,9 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + endif # BOARD_GOOGLE_VEYRON_PINKY diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index aa4ee34..05876f4 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -127,9 +127,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0xff700000 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL_UART - default 0xFF690000 - endif

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Patch set updated for coreboot: d1d4197 pinky: Move some init to mainboard bootblock
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9243 -gerrit commit d1d41970344ecc43c131cafe268e28c8686b3dcc Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:37:51 2014 -0700 pinky: Move some init to mainboard bootblock This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 --- src/mainboard/google/veyron_pinky/bootblock.c | 18 ++++++++++++++ src/soc/rockchip/rk3288/bootblock.c | 36 +++++++++++---------------- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d5bffea..5e22d6e 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2014 Rockchip Inc. * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify @@ -17,8 +18,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <bootblock_common.h> +#include <soc/rockchip/rk3288/grf.h> +#include <soc/rockchip/rk3288/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> void bootblock_mainboard_init(void) { + /* i2c1 for tpm*/ + writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + + /* spi2 for firmware ROM */ + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + + /* spi0 for chrome ec */ + writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + + setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d7bc67a..eec3456 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,34 +17,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> +#include <console/console.h> +#include <soc/rockchip/rk3288/grf.h> +#include "addressmap.h" #include "timer.h" #include "clock.h" -#include "grf.h" -#include "spi.h" -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/i2c.h> static void bootblock_cpu_init(void) { - writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); - writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); - writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - /*i2c1 for tpm*/ - writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); - - /* spi0 for chrome ec */ - writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); rk3288_init_timer(); - console_init(); - rkclk_init(); - /*i2c1 for tpm 400khz*/ - i2c_init(1, 400000); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); - setup_chromeos_gpios(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) { + case UART2_BASE: + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + break; + default: + die("TODO: Handle setup for console UART if needed"); + } + console_init(); + } + + rkclk_init(); }

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Patch set updated for coreboot: 7f867d8 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9223 -gerrit commit 7f867d8508ad7f788aa79a0ecb44f4bccea7760c Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Oct 10 03:08:15 2014 +0800 Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-BUG=chrome-os-partner:31424 Original-TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/pcie.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index c147663..2e70f45 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd1c55a..be17874 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -611,8 +611,15 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) pci_write_config32(dev, 0x94, (device << 16) | vendor); } +static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) +{ + /* Set max snoop and non-snoop latency for Broadwell */ + pci_mmio_write_config32(dev, off, 0x10031003); +} + static struct pci_operations pcie_ops = { .set_subsystem = pcie_set_subsystem, + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; static struct device_operations device_ops = {

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Patch merged into coreboot/master: 33c10f8 urara: Configure UART line control to 8N1
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 33c10f8c32a16701ad601d491322fb2468111b9b Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Oct 30 14:49:53 2014 +0000 urara: Configure UART line control to 8N1 8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: http://review.coreboot.org/9185 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/9185 for details. -gerrit

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Patch set updated for coreboot: 5d0ab27 urara: Configure UART line control to 8N1
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9185 -gerrit commit 5d0ab2793bba2462a0eeee82d23919f8dd00e4a1 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Oct 30 14:49:53 2014 +0000 urara: Configure UART line control to 8N1 8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/urara/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 231c97e..bde26d6 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -46,4 +46,8 @@ config DRAM_SIZE_MB int default 256 +config TTYS0_LCS + int + default 3 + endif

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Patch merged into coreboot/master: b92e543 mips: do not place branch instructions in branch delay slot
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit b92e54333f75baa86bcda67b1beeb19669250f03 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 3 09:47:13 2014 -0700 mips: do not place branch instructions in branch delay slot A branch instruction in a branch delay slot confuses the execution pipeline and causes an exception. bootblock.S was written 'by hand', has a branch instruction in branch delay slot and includes '.set noreorder' directive, which causes it to crash when trying to branch to main(). Adding a nop instruction fixes the problem. Also adding a nop after the last branch in the file just in case main() returns and the object linked next starts with a branch. BUG=chrome-os-partner:31438 TEST=Running on the simulator can reach main() now Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221421 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9183 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/9183 for details. -gerrit

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