coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

New patch to review for coreboot: e71d94e rk3288: Replace SPI fifo_size with constant
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9246 -gerrit commit e71d94e83d5b01a76f1ffe953fc75604fb24714e Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 18:54:55 2014 -0700 rk3288: Replace SPI fifo_size with constant rockchip_spi_slave has a fifo_size member which doesn't change. This just replaces the struct member with a #define. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9 Original-Reviewed-on: https://chromium-review.googlesource.com/220471 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be --- src/soc/rockchip/rk3288/spi.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 3fb7291..431b2d3 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,11 +33,11 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int fifo_size; }; #define SPI_TIMEOUT_US 1000 #define SPI_SRCCLK_HZ 99000000 +#define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[3] = { { @@ -46,12 +46,10 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .fifo_size = 32, }, { .slave = { @@ -59,7 +57,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .fifo_size = 32, }, }; @@ -108,8 +105,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { - struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; - struct rockchip_spi *regs = espi->regs; + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int ctrlr0 = 0; rkclk_configure_spi(bus, SPI_SRCCLK_HZ); @@ -145,9 +141,9 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) writel(ctrlr0, &regs->ctrlr0); - /*fifo depth */ - writel(espi->fifo_size / 2 - 1, &regs->txftlr); - writel(espi->fifo_size / 2 - 1, &regs->rxftlr); + /* fifo depth */ + writel(SPI_FIFO_DEPTH / 2 - 1, &regs->txftlr); + writel(SPI_FIFO_DEPTH / 2 - 1, &regs->rxftlr); } int spi_claim_bus(struct spi_slave *slave) @@ -182,7 +178,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout, unsigned int bytes_remaining; uint8_t *p; struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - struct rockchip_spi_slave *espi = to_rockchip_spi(slave); if (dout) { len = sout; @@ -196,8 +191,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int sout, SPI_TMOD_TO << SPI_TMOD_OFFSET); writel(1, &regs->spienr);/*enable spi */ while (bytes_remaining) { - if ((readl(&regs->txflr) & 0x3f) - < espi->fifo_size) { + if ((readl(&regs->txflr) & 0x3f) < SPI_FIFO_DEPTH) { writel(*p++, &regs->txdr); bytes_remaining--; }

1 0

New patch to review for coreboot: 89ec4ba rk3288: Pass SPI bus speed in as parameter to init function
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9245 -gerrit commit 89ec4ba69ff0504f4525e9fad82e975ad993f141 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:48:40 2014 -0700 rk3288: Pass SPI bus speed in as parameter to init function This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c --- src/mainboard/google/veyron_pinky/bootblock.c | 4 ++-- src/soc/rockchip/rk3288/spi.c | 8 ++------ src/soc/rockchip/rk3288/spi.h | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 5e22d6e..d4f82de 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 844d692..3fb7291 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,7 +33,6 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int speed_hz; unsigned int fifo_size; }; @@ -47,13 +46,11 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .speed_hz = 9000000, .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, { @@ -62,7 +59,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, @@ -110,7 +106,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) writel(clk_div, &regs->baudr); } -void rockchip_spi_init(unsigned int bus) +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; struct rockchip_spi *regs = espi->regs; @@ -118,7 +114,7 @@ void rockchip_spi_init(unsigned int bus) rkclk_configure_spi(bus, SPI_SRCCLK_HZ); rockchip_spi_enable_chip(regs, 0); - rockchip_spi_set_clk(regs, espi->speed_hz); + rockchip_spi_set_clk(regs, speed_hz); /* Operation Mode */ ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h index c6880c2..bba38ef 100644 --- a/src/soc/rockchip/rk3288/spi.h +++ b/src/soc/rockchip/rk3288/spi.h @@ -199,6 +199,6 @@ check_member(rockchip_spi, rxdr, 0x800); int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, size_t buffer_size); -void rockchip_spi_init(unsigned int bus); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); #endif

1 0

New patch to review for coreboot: 8003514 rk3288: remove duplicted #define
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9244 -gerrit commit 800351461d4992e290c4a39bb003bec6a8c88071 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 2 14:39:25 2015 -0500 rk3288: remove duplicted #define I'm not sure how the build didn't fail before. In either case remove the duplication. Change-Id: I764774f2b8a5839512af3f054b844a1a86efdb45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 59a32db..8202ef2 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -159,7 +159,6 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4); */ #define PERI_ACLK_DIV_SHIFT (0x0) #define PERI_ACLK_DIV_MSK (0x1F) -#define PERI_ACLK_DIV_SHIFT (0) /*******************CLKSEL37 BITS***************************/ #define L2_DIV_MSK (0x7)

1 0

Patch set updated for coreboot: 7d0dbca rk3288/pinky: Move uart address to mainboard Kconfig
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9242 -gerrit commit 7d0dbca52dba0bdfa255fe5ab817e5c4d037abc5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 2 15:37:46 2014 -0700 rk3288/pinky: Move uart address to mainboard Kconfig Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 --- src/mainboard/google/veyron_pinky/Kconfig | 5 +++++ src/soc/rockchip/rk3288/Kconfig | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 7f981b4..97a0097 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -81,4 +81,9 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + endif # BOARD_GOOGLE_VEYRON_PINKY diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index aa4ee34..05876f4 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -127,9 +127,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0xff700000 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL_UART - default 0xFF690000 - endif

1 0

Patch set updated for coreboot: e8d1f11 pinky: Move some init to mainboard bootblock
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9243 -gerrit commit e8d1f1146f089e95603819ba3cd7b3885e6d9fce Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:37:51 2014 -0700 pinky: Move some init to mainboard bootblock This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 --- src/mainboard/google/veyron_pinky/bootblock.c | 18 ++++++++++++++ src/soc/rockchip/rk3288/bootblock.c | 36 +++++++++++---------------- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d5bffea..5e22d6e 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2014 Rockchip Inc. * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify @@ -17,8 +18,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <bootblock_common.h> +#include <soc/rockchip/rk3288/grf.h> +#include <soc/rockchip/rk3288/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> void bootblock_mainboard_init(void) { + /* i2c1 for tpm*/ + writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + + /* spi2 for firmware ROM */ + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + + /* spi0 for chrome ec */ + writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + + setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d7bc67a..eec3456 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,34 +17,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> +#include <console/console.h> +#include <soc/rockchip/rk3288/grf.h> +#include "addressmap.h" #include "timer.h" #include "clock.h" -#include "grf.h" -#include "spi.h" -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/i2c.h> static void bootblock_cpu_init(void) { - writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); - writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); - writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - /*i2c1 for tpm*/ - writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); - - /* spi0 for chrome ec */ - writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); rk3288_init_timer(); - console_init(); - rkclk_init(); - /*i2c1 for tpm 400khz*/ - i2c_init(1, 400000); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); - setup_chromeos_gpios(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) { + case UART2_BASE: + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + break; + default: + die("TODO: Handle setup for console UART if needed"); + } + console_init(); + } + + rkclk_init(); }

1 0

New patch to review for coreboot: deeae24 pinky: Move some init to mainboard bootblock
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9243 -gerrit commit deeae24ff1f7c6bd7cecf9989ca116084624e1a8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Sep 29 13:37:51 2014 -0700 pinky: Move some init to mainboard bootblock This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 --- src/mainboard/google/veyron_pinky/bootblock.c | 18 ++++++++++++++ src/soc/rockchip/rk3288/bootblock.c | 36 +++++++++++---------------- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d5bffea..5e22d6e 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright 2014 Rockchip Inc. * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify @@ -17,8 +18,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <bootblock_common.h> +#include <soc/rockchip/rk3288/grf.h> +#include <soc/rockchip/rk3288/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> void bootblock_mainboard_init(void) { + /* i2c1 for tpm*/ + writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); + + /* spi2 for firmware ROM */ + writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); + writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + + /* spi0 for chrome ec */ + writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + + setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d7bc67a..eec3456 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,34 +17,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> +#include <console/console.h> +#include <soc/rockchip/rk3288/grf.h> +#include "addressmap.h" #include "timer.h" #include "clock.h" -#include "grf.h" -#include "spi.h" -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/i2c.h> static void bootblock_cpu_init(void) { - writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); - writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); - writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - /*i2c1 for tpm*/ - writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); - - /* spi0 for chrome ec */ - writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); rk3288_init_timer(); - console_init(); - rkclk_init(); - /*i2c1 for tpm 400khz*/ - i2c_init(1, 400000); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); - setup_chromeos_gpios(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) { + case UART2_BASE: + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + break; + default: + die("TODO: Handle setup for console UART if needed"); + } + console_init(); + } + + rkclk_init(); }

1 0

New patch to review for coreboot: 6786bb4 rk3288/pinky: Move uart address to mainboard Kconfig
by Aaron Durbin 02 Apr '15

02 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9242 -gerrit commit 6786bb4f1cea8c677b32f8cf965bc4b9a7b0bf40 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 2 15:37:46 2014 -0700 rk3288/pinky: Move uart address to mainboard Kconfig Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 --- src/mainboard/google/veyron_pinky/Kconfig | 5 +++++ src/soc/rockchip/rk3288/Kconfig | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 7f981b4..97a0097 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -81,4 +81,9 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + endif # BOARD_GOOGLE_VEYRON_PINKY diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index aa4ee34..05876f4 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -127,9 +127,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0xff700000 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL_UART - default 0xFF690000 - endif

1 0

Patch merged into coreboot/master: 3e9ea16 coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit 3e9ea16c54dfe9ac593f772e5ba2f020b2e27c99 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Sep 25 20:27:26 2014 -0700 coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhz Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9239 for details. -gerrit

1 0

Patch merged into coreboot/master: bfdd732 rockchip: support pwm regulator
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit bfdd732b80a56e31d3bbe59de76a6a91b0f5b9e4 Author: huang lin <hl(a)rock-chips.com> Date: Thu Sep 25 16:33:38 2014 +0800 rockchip: support pwm regulator BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/9240 for details. -gerrit

1 0

Patch merged into coreboot/master: bbcffd9 rockchip: support i2c clock setting
by gerrit＠coreboot.org 02 Apr '15

02 Apr '15

the following patch was just integrated into master: commit bbcffd9e25e12a8ee5858ac580aa7e86ecf32ee5 Author: huang lin <hl(a)rock-chips.com> Date: Sat Sep 27 12:02:27 2014 +0800 rockchip: support i2c clock setting BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/9241 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2015