coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 76de677 samus: Enable update screen for software sync
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9264 -gerrit commit 76de67710231a49f954eaa82dfbfb987faf996ce Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 16 17:06:32 2014 -0700 samus: Enable update screen for software sync Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index c92f76d..d3623bb 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC + select VBOOT_EC_SLOW_UPDATE + select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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Patch set updated for coreboot: 6f49d20 samus: Add smbios_mainboard_version to define board version
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9263 -gerrit commit 6f49d203d751b487a2410a95a8dece7b1257500b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 13 13:12:38 2014 -0700 samus: Add smbios_mainboard_version to define board version Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/ec.h | 4 ++++ src/mainboard/google/samus/mainboard.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h index 1ba1677..295d040 100644 --- a/src/mainboard/google/samus/ec.h +++ b/src/mainboard/google/samus/ec.h @@ -22,6 +22,10 @@ #include <ec/google/chromeec/ec_commands.h> +#define SAMUS_EC_BOARD_VERSION_EVT 3 +#define SAMUS_EC_BOARD_VERSION_EVT2 4 +#define SAMUS_EC_BOARD_VERSION_EVT3 5 + #define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ #define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 89303b9..85e9dfb 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -32,12 +32,26 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> #include "ec.h" void mainboard_suspend_resume(void) { } +const char *smbios_mainboard_version(void) +{ + switch (google_chromeec_get_board_version()) { + case SAMUS_EC_BOARD_VERSION_EVT: + return "EVT"; + case SAMUS_EC_BOARD_VERSION_EVT2: + return "EVT2"; + case SAMUS_EC_BOARD_VERSION_EVT3: + return "EVT3"; + } + return "Unknown"; +} + static void mainboard_init(device_t dev) { mainboard_ec_init();

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Patch set updated for coreboot: bc33b49 broadwell: Fix building with USE=quiet-cb
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9262 -gerrit commit bc33b499114dd33da87384fa47303cb74abe0cd6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 3 15:34:09 2014 -0700 broadwell: Fix building with USE=quiet-cb This function needs to be available in different LOGLEVELs. BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/me_status.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 31eff3c..033e4e2 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -27,6 +27,12 @@ #include <broadwell/me.h> #include <delay.h> +static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ @@ -201,12 +207,6 @@ static const char *me_progress_policy_values[] = { "Required VSCC values for flash parts do not match", }; -static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - void intel_me_status(void) { struct me_hfs _hfs, *hfs = &_hfs;

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Patch set updated for coreboot: b6a6aa8 samus: Add codec platform info in ACPI
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9261 -gerrit commit b6a6aa89e746c8b157660bffe4178b08c870d543 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 3 15:33:10 2014 -0700 samus: Add codec platform info in ACPI This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 2bb34fd..ec3cfe0 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -171,6 +171,14 @@ Scope (\_SB.PCI0.I2C0) Name (_UID, 1) Name (WAKE, 45) /* DSP_INT (use as codec wake) */ + Name (DCLK, 0) /* RT5677_DMIC_CLK1 */ + Name (IN1, 1) /* IN1 differential */ + Name (IN2, 0) /* IN2 not differential */ + Name (OUT1, 1) /* LOUT1 differential */ + Name (OUT2, 1) /* LOUT2 differential */ + Name (OUT3, 0) /* LOUT3 differential */ + Name (ASRC, 1) /* Enable I2S1 ASRC */ + Name (_CRS, ResourceTemplate() { I2cSerialBus (

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New patch to review for coreboot: 0824287 samus: Disable USB Port 5
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9282 -gerrit commit 0824287e465982c7600766d880f9be34cf4a5891 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 10 08:11:56 2014 -0800 samus: Disable USB Port 5 This device is not used in current builds and should be disabled to help EMI. BUG=chrome-os-partner:34117 BRANCH=samus TEST=build and boot on samus Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2 Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234403 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/samus/pei_data.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c index 04b86e0..05a3ded 100644 --- a/src/mainboard/google/samus/pei_data.c +++ b/src/mainboard/google/samus/pei_data.c @@ -60,9 +60,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P4: RAIDEN */ pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); - /* P5: WWAN */ - pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, - USB_PORT_INTERNAL); + /* P5: WWAN (Disabled) */ + pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, + USB_PORT_SKIP); /* P6: CAMERA */ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);

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New patch to review for coreboot: 05c7648 broadwell: Enable turbo ratio if available
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9281 -gerrit commit 05c76486bebe400aacd1cf807da66750a16ecc2a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 10 08:16:43 2014 -0800 broadwell: Enable turbo ratio if available When turning up the CPU frequency set it to turbo if that is a possibility. Also only set the frequency on the boot CPU since that is all we need it on, this will allow the 1-core turbo ratio. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183 Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234401 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/broadwell/cpu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1f2ee0d..912f8ae 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -485,7 +485,10 @@ static void set_max_ratio(void) perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; @@ -587,9 +590,6 @@ static void cpu_core_init(device_t cpu) /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -692,6 +692,9 @@ void broadwell_init_cpus(device_t dev) printk(BIOS_ERR, "MP initialization failure.\n"); } + /* Set Max Ratio */ + set_max_ratio(); + /* Restore the default SMM region. */ restore_default_smm_area(smm_save_area); }

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New patch to review for coreboot: 36777b6 Broadwell: Pass TSC value to romstage_main
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9280 -gerrit commit 36777b6d14f89856e3930746a5e20a5adb368b3e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Nov 20 16:56:44 2014 -0800 Broadwell: Pass TSC value to romstage_main The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 4e6cf09..a10ca4c 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -180,7 +180,13 @@ clear_mtrrs: /* Restore the BIST result. */ movl %ebp, %eax + + /* Build the call frame. */ movl %esp, %ebp + movd %mm1, %ebx + pushl %ebx + movd %mm0, %ebx + pushl %ebx pushl %eax before_romstage:

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New patch to review for coreboot: 62d3d39 Add table driven way to add platform specific reg_script routines
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9279 -gerrit commit 62d3d39494d82848911011d6f37a3714f03d4166 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Aug 29 13:38:59 2014 -0700 Add table driven way to add platform specific reg_script routines Extend lib/reg_script.c to use a platform table to declare additional platform specific register access routine functions. REG_SCRIPT_TYPE_PLATFORM_BASE is the starting value for platform specific register types. Additional register access types may be defined above this value. The type and access routines are placed into reg_script_type_table. The Baytrail type value for IOSF was left the enumeration since it was already defined and is being used for Braswell. BRANCH=none BUG=None TEST=Use the following steps to test: 1. Build for a Baytrail platform 2. Build for the Samus platform 3. Add a platform_bus_table routine to a platform which returns the address of an array of reg_script_bus_entry structures and the number of entries in the array. Change-Id: Ic99d345c4b067c52b4e9c47e59ed4472a05bc1a5 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 2d9fecf4287dff6311a81d818603212248f1a248 Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215645 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Change-Id: I7cd37abc5a08cadb3166d4048f65b919b86ab5db Original-Reviewed-on: https://chromium-review.googlesource.com/229612 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/reg_script.h | 25 ++++++++++++++ src/lib/reg_script.c | 87 ++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 98 insertions(+), 14 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 97b4fb0..0c0ea01 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -60,6 +60,10 @@ enum { REG_SCRIPT_TYPE_RES, REG_SCRIPT_TYPE_IOSF, REG_SCRIPT_TYPE_MSR, + + /* Insert other platform independent values above this comment */ + + REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000 }; enum { @@ -85,6 +89,24 @@ struct reg_script { }; }; +struct reg_script_context { + device_t dev; + struct resource *res; + const struct reg_script *step; +}; + +#ifndef __PRE_RAM__ +struct reg_script_bus_entry { + int type; + uint64_t (*reg_script_read)(struct reg_script_context *ctx); + void (*reg_script_write)(struct reg_script_context *ctx); +}; + +/* Get the address and length of the platform bus table */ +const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries); + +#endif /* __PRE_RAM */ + /* Internal helper Macros. */ #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ @@ -271,6 +293,8 @@ struct reg_script { #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) + +#if CONFIG_SOC_INTEL_BAYTRAIL /* * IO Sideband Function */ @@ -290,6 +314,7 @@ struct reg_script { REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) +#endif /* CONFIG_SOC_INTEL_BAYTRAIL */ /* * CPU Model Specific Register diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 2fd943e..3f7ddaf 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -41,12 +41,6 @@ #define EMPTY_DEV NULL #endif -struct reg_script_context { - device_t dev; - struct resource *res; - const struct reg_script *step; -}; - static inline void reg_script_set_dev(struct reg_script_context *ctx, device_t dev) { @@ -243,9 +237,9 @@ static void reg_script_write_res(struct reg_script_context *ctx) reg_script_set_step(ctx, step); } +#if CONFIG_SOC_INTEL_BAYTRAIL static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) { -#if CONFIG_SOC_INTEL_BAYTRAIL const struct reg_script *step = reg_script_get_step(ctx); switch (step->id) { @@ -296,13 +290,11 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) step->id); break; } -#endif return 0; } static void reg_script_write_iosf(struct reg_script_context *ctx) { -#if CONFIG_SOC_INTEL_BAYTRAIL const struct reg_script *step = reg_script_get_step(ctx); switch (step->id) { @@ -374,8 +366,9 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) step->id); break; } -#endif } +#endif + static uint64_t reg_script_read_msr(struct reg_script_context *ctx) { @@ -401,6 +394,36 @@ static void reg_script_write_msr(struct reg_script_context *ctx) #endif } +#ifndef __PRE_RAM__ +/* Default routine provided for systems without platform specific busses */ +const struct reg_script_bus_entry *__attribute__((weak)) + platform_bus_table(size_t *table_entries) +{ + /* No platform bus type table supplied */ + *table_entries = 0; + return NULL; +} + +/* Locate the structure containing the platform specific bus access routines */ +static const struct reg_script_bus_entry + *find_bus(const struct reg_script *step) +{ + const struct reg_script_bus_entry *bus; + size_t table_entries; + size_t i; + + /* Locate the platform specific bus */ + bus = platform_bus_table(&table_entries); + for (i = 0; i < table_entries; i++) { + if (bus[i].type == step->type) + return &bus[i]; + } + + /* Bus not found */ + return NULL; +} +#endif + static uint64_t reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); @@ -414,10 +437,27 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_mmio(ctx); case REG_SCRIPT_TYPE_RES: return reg_script_read_res(ctx); - case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); case REG_SCRIPT_TYPE_MSR: return reg_script_read_msr(ctx); +#if CONFIG_SOC_INTEL_BAYTRAIL + case REG_SCRIPT_TYPE_IOSF: + return reg_script_read_iosf(ctx); +#endif + default: +#ifndef __PRE_RAM__ + { + const struct reg_script_bus_entry *bus; + + /* Read from the platform specific bus */ + bus = find_bus(step); + if (NULL != bus) + return bus->reg_script_read(ctx); + } +#endif + printk(BIOS_ERR, + "Unsupported read type (0x%x) for this device!\n", + step->type); + break; } return 0; } @@ -439,11 +479,30 @@ static void reg_script_write(struct reg_script_context *ctx) case REG_SCRIPT_TYPE_RES: reg_script_write_res(ctx); break; + case REG_SCRIPT_TYPE_MSR: + reg_script_write_msr(ctx); + break; +#if CONFIG_SOC_INTEL_BAYTRAIL case REG_SCRIPT_TYPE_IOSF: reg_script_write_iosf(ctx); break; - case REG_SCRIPT_TYPE_MSR: - reg_script_write_msr(ctx); +#endif + default: +#ifndef __PRE_RAM__ + { + const struct reg_script_bus_entry *bus; + + /* Write to the platform specific bus */ + bus = find_bus(step); + if (NULL != bus) { + bus->reg_script_write(ctx); + return; + } + } +#endif + printk(BIOS_ERR, + "Unsupported write type (0x%x) for this device!\n", + step->type); break; } }

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New patch to review for coreboot: 2b58c0b samus: Add new memory type
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9278 -gerrit commit 2b58c0b492728b7ec695260d587063321d318a89 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 19 12:12:18 2014 -0800 samus: Add new memory type Add a new memory type for the next build, and rename the existing ones to drop the Gb suffix. BUG=chrome-os-partner:33924 BRANCH=samus TEST=build and boot on samus Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7 Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230769 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/spd/Makefile.inc | 12 ++++++------ src/mainboard/google/samus/spd/elpida_16.spd.hex | 18 ++++++++++++++++++ src/mainboard/google/samus/spd/elpida_4.spd.hex | 16 ++++++++++++++++ src/mainboard/google/samus/spd/elpida_4Gb.spd.hex | 16 ---------------- src/mainboard/google/samus/spd/elpida_8.spd.hex | 16 ++++++++++++++++ src/mainboard/google/samus/spd/elpida_8Gb.spd.hex | 16 ---------------- src/mainboard/google/samus/spd/hynix_16.spd.hex | 18 ++++++++++++++++++ src/mainboard/google/samus/spd/hynix_16Gb.spd.hex | 18 ------------------ src/mainboard/google/samus/spd/hynix_4.spd.hex | 18 ++++++++++++++++++ src/mainboard/google/samus/spd/hynix_4Gb.spd.hex | 18 ------------------ src/mainboard/google/samus/spd/hynix_8.spd.hex | 18 ++++++++++++++++++ src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 18 ------------------ src/mainboard/google/samus/spd/samsung_4.spd.hex | 16 ++++++++++++++++ src/mainboard/google/samus/spd/samsung_4Gb.spd.hex | 16 ---------------- src/mainboard/google/samus/spd/samsung_8.spd.hex | 16 ++++++++++++++++ src/mainboard/google/samus/spd/samsung_8Gb.spd.hex | 16 ---------------- 16 files changed, 142 insertions(+), 124 deletions(-) diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index be6740d..79d5aed 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -28,16 +28,16 @@ SPD_SOURCES += empty # 0b0010 SPD_SOURCES += empty # 0b0011 SPD_SOURCES += empty # 0b0100 SPD_SOURCES += empty # 0b0101 -SPD_SOURCES += samsung_4Gb # 0b0110 +SPD_SOURCES += samsung_4 # 0b0110 SPD_SOURCES += empty # 0b0111 -SPD_SOURCES += hynix_4Gb # 0b1000 +SPD_SOURCES += hynix_4 # 0b1000 SPD_SOURCES += empty # 0b1001 -SPD_SOURCES += samsung_8Gb # 0b1010 +SPD_SOURCES += samsung_8 # 0b1010 SPD_SOURCES += empty # 0b1011 -SPD_SOURCES += hynix_8Gb # 0b1100 -SPD_SOURCES += hynix_16Gb # 0b1101 +SPD_SOURCES += hynix_8 # 0b1100 +SPD_SOURCES += hynix_16 # 0b1101 SPD_SOURCES += empty # 0b1110 -SPD_SOURCES += empty # 0b1111 +SPD_SOURCES += elpida_16 # 0b1111 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/samus/spd/elpida_16.spd.hex b/src/mainboard/google/samus/spd/elpida_16.spd.hex new file mode 100644 index 0000000..5594164 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_16.spd.hex @@ -0,0 +1,18 @@ +# Elpida EDFB232A1MA +# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 +91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 42 32 33 32 41 31 4D 41 2D 47 44 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_4.spd.hex b/src/mainboard/google/samus/spd/elpida_4.spd.hex new file mode 100644 index 0000000..e73ba62 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_4.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex deleted file mode 100644 index e73ba62..0000000 --- a/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_8.spd.hex b/src/mainboard/google/samus/spd/elpida_8.spd.hex new file mode 100644 index 0000000..b790943 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_8.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex deleted file mode 100644 index b790943..0000000 --- a/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_16.spd.hex b/src/mainboard/google/samus/spd/hynix_16.spd.hex new file mode 100644 index 0000000..a03d4ed --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_16.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNCLTMLAR LPDDR3 +# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 +91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00 +00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex deleted file mode 100644 index a03d4ed..0000000 --- a/src/mainboard/google/samus/spd/hynix_16Gb.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNCLTMLAR LPDDR3 -# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 -91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00 -00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_4.spd.hex b/src/mainboard/google/samus/spd/hynix_4.spd.hex new file mode 100644 index 0000000..93e65a7 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_4.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex deleted file mode 100644 index 93e65a7..0000000 --- a/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 -# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E -54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8.spd.hex b/src/mainboard/google/samus/spd/hynix_8.spd.hex new file mode 100644 index 0000000..15737e4 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_8.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 +91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex deleted file mode 100644 index 15737e4..0000000 --- a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex +++ /dev/null @@ -1,18 +0,0 @@ -# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 -# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 -91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E -54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_4.spd.hex b/src/mainboard/google/samus/spd/samsung_4.spd.hex new file mode 100644 index 0000000..4b82a3a --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_4.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex deleted file mode 100644 index 4b82a3a..0000000 --- a/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 -4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_8.spd.hex b/src/mainboard/google/samus/spd/samsung_8.spd.hex new file mode 100644 index 0000000..c0a8fca --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_8.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex deleted file mode 100644 index c0a8fca..0000000 --- a/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 -4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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New patch to review for coreboot: 8d7f451 samus: Set codec PDM clock output to 3MHz
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9277 -gerrit commit 8d7f451e5f44173f35764445ea0f5c1666a15d2d Author: Ben Zhang <benzh(a)chromium.org> Date: Mon Nov 17 17:21:09 2014 -0800 samus: Set codec PDM clock output to 3MHz Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 39797e5..2b6cea0 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -170,6 +170,7 @@ Scope (\_SB.PCI0.I2C0) Name (WAKE, 45) /* DSP_INT (use as codec wake) */ Name (DCLK, 0) /* RT5677_DMIC_CLK1 */ + Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */ Name (IN1, 1) /* IN1 differential */ Name (IN2, 0) /* IN2 not differential */ Name (OUT1, 1) /* LOUT1 differential */

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coreboot-gerrit April 2015