coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

Patch set updated for coreboot: 615484e samus: Change touchscreen bootloader mode i2c address
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9274 -gerrit commit 615484ecf05636f02ca2b178ebb9cc9c76332a99 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 17 13:06:52 2014 -0800 samus: Change touchscreen bootloader mode i2c address This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index feecac3..39797e5 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -258,7 +258,7 @@ Scope (\_SB.PCI0.I2C1) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x25, // SlaveAddress + 0x27, // SlaveAddress ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode

1 0

Patch set updated for coreboot: cd1317c samus: Enable GSPI0 interface
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9273 -gerrit commit cd1317c30fce4a381ff89ccdcdeaf1dd33940516 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 15:46:59 2014 -0800 samus: Enable GSPI0 interface This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/devicetree.cb | 2 +- src/mainboard/google/samus/gpio.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 4bbc3af..93ae51b 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -70,7 +70,7 @@ chip soc/intel/broadwell device pci 15.0 on end # Serial I/O DMA device pci 15.1 on end # I2C0 device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 + device pci 15.3 on end # GSPI0 device pci 15.4 off end # GSPI1 device pci 15.5 off end # UART0 device pci 15.6 off end # UART1 diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index 9f4031f..99bdee6 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -111,10 +111,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 80: UNUSED */ PCH_GPIO_UNUSED, /* 81: UNUSED */ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_NATIVE, /* 83: GSPI0_CS */ + PCH_GPIO_NATIVE, /* 84: GSPI0_CLK */ + PCH_GPIO_NATIVE, /* 85: GSPI0_MISO */ + PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI (STRAP) */ PCH_GPIO_UNUSED, /* 87: UNUSED */ PCH_GPIO_UNUSED, /* 88: UNUSED */ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */

1 0

Patch set updated for coreboot: b5bf221 Baytrail: Fixed no_dev_behind_port not executed for RP1/2/3.
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9272 -gerrit commit b5bf221afbbf4dc9ee053fdf76666f55807c825f Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Oct 31 00:32:09 2014 -0700 Baytrail: Fixed no_dev_behind_port not executed for RP1/2/3. BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> --- src/soc/intel/baytrail/pcie.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index f80a494..c477e22 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -198,6 +198,7 @@ static void check_device_present(device_t dev) dev->enabled = 0; } } else { + reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } } else if(!dev->enabled) {

1 0

Patch set updated for coreboot: 19ba6ba samus: Enable GPIO9 as touchpad wake
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9271 -gerrit commit 19ba6bad8d69b3e12819e3b359156c71567884e5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 12:48:11 2014 -0800 samus: Enable GPIO9 as touchpad wake With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 6 ++---- src/mainboard/google/samus/gpio.h | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index c6ad278..feecac3 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -122,7 +122,7 @@ Scope (\_SB.PCI0.I2C0) Name (_UID, 2) Name (_S0W, 4) Name (ISTP, 1) /* Touchpad */ - Name (GPIO, 13) /* TRACKPAD_INT_L */ + Name (GPIO, 9) /* TRACKPAD_INT_L (WAKE) */ Name (_CRS, ResourceTemplate() { @@ -140,7 +140,6 @@ Scope (\_SB.PCI0.I2C0) Name (_PRW, Package() { GPIO, 3 }) -#ifdef ENABLE_TOUCH_WAKE Method (_DSW, 3, NotSerialized) { If (LEqual (Arg0, 1)) { @@ -148,7 +147,6 @@ Scope (\_SB.PCI0.I2C0) \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) } } -#endif Method (_STA) { @@ -304,9 +302,9 @@ Scope (\_SB.PCI0.I2C1) Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } }) +#ifdef ENABLE_TOUCH_WAKE Name (_PRW, Package() { GPIO, 3 }) -#ifdef ENABLE_TOUCH_WAKE Method (_DSW, 3, NotSerialized) { If (LEqual (Arg0, 1)) { diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index 393a14f..9f4031f 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -37,7 +37,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ - PCH_GPIO_UNUSED, /* 9: UNUSED */ + PCH_GPIO_INPUT_INVERT, /* 9: TRACKPAD_INT_L (WAKE) */ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ PCH_GPIO_UNUSED, /* 11: UNUSED */ PCH_GPIO_UNUSED, /* 12: UNUSED */

1 0

Patch set updated for coreboot: 70d4fcf samus: Update thermal max for broadwell
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9270 -gerrit commit 70d4fcf01f85da442d2bfec074921fb7d9dcf27f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 08:53:21 2014 -0800 samus: Update thermal max for broadwell Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/thermal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/samus/thermal.h b/src/mainboard/google/samus/thermal.h index 9bea3f0..2e3f450 100644 --- a/src/mainboard/google/samus/thermal.h +++ b/src/mainboard/google/samus/thermal.h @@ -23,12 +23,12 @@ #define TEMPERATURE_SENSOR_ID 0 /* PECI */ /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 99 +#define CRITICAL_TEMPERATURE 104 /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 95 /* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 +#define MAX_TEMPERATURE 105 #endif

1 0

Patch set updated for coreboot: b526782 samus: Assign GPIO2 to HP_AMP_SHDN_L
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9269 -gerrit commit b526782ab1a1bb951d707fc0baa251783b905617 Author: Ben Zhang <benzh(a)chromium.org> Date: Tue Sep 30 17:00:05 2014 -0700 samus: Assign GPIO2 to HP_AMP_SHDN_L BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 128f266..c6ad278 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -202,6 +202,7 @@ Scope (\_SB.PCI0.I2C0) * [1] = Mic Present (INPUT) * [2] = Interrupt to the host (OUTPUT) * [3] = Interrupt to the host (OUTPUT) + * [4] = Headphone amp control (OUTPUT) */ /* Index 0: Jack Detect - PLUG_DET is GPIO5 */ @@ -219,6 +220,10 @@ Scope (\_SB.PCI0.I2C0) /* Index 3: Codec Wake - DSP_INT is GPIO4 */ GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, "\\_SB.PCI0.I2C0.CODC") { 3 } + + /* Index 4: Headphone amp - HP_AMP_SHDN_L is GPIO2 */ + GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 1 } }) Name (_PRW, Package() { WAKE, 3 })

1 0

Patch set updated for coreboot: ca83d75 samus: Make codec interrupt active high
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9268 -gerrit commit ca83d75248a488f831c5c65791793c0134e9e779 Author: Ben Zhang <benzh(a)chromium.org> Date: Tue Sep 30 12:55:04 2014 -0700 samus: Make codec interrupt active high The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index b4b4723..128f266 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -193,7 +193,7 @@ Scope (\_SB.PCI0.I2C0) ) /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */ - Interrupt (ResourceConsumer, Edge, ActiveLow) { 30 } + Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 } /* * Codec GPIOs are 1-based in the schematic

1 0

Patch set updated for coreboot: 889f0ce Broadwell: Fix PCIe L1 Sub-State capability ID not filled.
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9267 -gerrit commit 889f0ced93da98587915d95e928e372f7dbb37b4 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Tue Sep 30 14:17:35 2014 +0800 Broadwell: Fix PCIe L1 Sub-State capability ID not filled. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 --- src/soc/intel/broadwell/pcie.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 4e5bbfa..10b6230 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -558,9 +558,12 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg8(dev, 0xf5, 0x0f, 0); - /* Set Extended Capability to offset 200h and Advanced Error Report. */ + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e); + pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); /* Enable Relaxed Order from Root Port. */

1 0

Patch set updated for coreboot: f4caa0a samus: Add codec platform data for jack detect
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9266 -gerrit commit f4caa0ad5dafb321d420d6d07b91dc5296142a83 Author: Ben Zhang <benzh(a)chromium.org> Date: Mon Oct 20 17:27:42 2014 -0700 samus: Add codec platform data for jack detect GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/samus/acpi/mainboard.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index ec3cfe0..b4b4723 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -178,6 +178,9 @@ Scope (\_SB.PCI0.I2C0) Name (OUT2, 1) /* LOUT2 differential */ Name (OUT3, 0) /* LOUT3 differential */ Name (ASRC, 1) /* Enable I2S1 ASRC */ + Name (JD1, 0) /* JackDetect1 is not used */ + Name (JD2, 2) /* Use GPIO5 as JackDetect2 */ + Name (JD3, 3) /* Use GPIO6 as JackDetect3 */ Name (_CRS, ResourceTemplate() {

1 0

Patch set updated for coreboot: 1b6a0f9 samus: Change GPIO controller label to INT3437:00
by Stefan Reinauer 02 Apr '15

02 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9265 -gerrit commit 1b6a0f9fd394b85f827edf6bc678e2da0d4ad3e1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 17 13:49:22 2014 -0700 samus: Change GPIO controller label to INT3437:00 This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/samus/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/samus/acpi/chromeos.asl b/src/mainboard/google/samus/acpi/chromeos.asl index 132f65d..d490f60 100644 --- a/src/mainboard/google/samus/acpi/chromeos.asl +++ b/src/mainboard/google/samus/acpi/chromeos.asl @@ -18,6 +18,6 @@ */ Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button - Package () { 0x0003, 1, 16, "PCH-LP" }, // firmware write protect + Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button + Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect })

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2015