coreboot-gerrit April 2015

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Patch set updated for coreboot: 867ebec cosmos: rearrange configuration and makefile definitions
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9353 -gerrit commit 867ebece12db7711bd49fd8e4bc4fd58e50a3262 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Oct 15 18:19:03 2014 -0700 cosmos: rearrange configuration and makefile definitions This is a no-op aesthetic change, arranging configurarion and makefile lines alphanumerically. BRANCH=none BUG=none TEST=cosmos still builds Change-Id: I72b7defca722380dda3ef8453e625f28bdebfa2c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c55a7e9d5064edf5cac9498c8c6c377cbf705bb1 Original-Change-Id: I4498eef59fc20ea04b6ebadb451d0fe346824c05 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223597 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/Kconfig | 14 +++++++------- src/soc/marvell/bg4cd/Makefile.inc | 10 +++++----- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 0a9778d..f8bf0b9 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -20,16 +20,16 @@ config SOC_MARVELL_BG4CD bool default n - select CPU_HAS_BOOTBLOCK_INIT - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY - select EARLY_CONSOLE - select DYNAMIC_CBMEM select ARCH_BOOTBLOCK_ARMV7 - select ARCH_VERSTAGE_ARMV7 - select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_VERSTAGE_ARMV7 select BOOTBLOCK_CONSOLE + select CPU_HAS_BOOTBLOCK_INIT + select DYNAMIC_CBMEM + select EARLY_CONSOLE + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER if SOC_MARVELL_BG4CD diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 7d114dd..7d49486 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -18,24 +18,24 @@ ## bootblock-y += cbmem.c -bootblock-y += monotonic_timer.c -bootblock-y += media.c bootblock-y += i2c.c +bootblock-y += media.c +bootblock-y += monotonic_timer.c -verstage-y += monotonic_timer.c verstage-y += i2c.c verstage-y += media.c +verstage-y += monotonic_timer.c romstage-y += cbmem.c -romstage-y += monotonic_timer.c romstage-y += i2c.c romstage-y += media.c +romstage-y += monotonic_timer.c romstage-y += sdram.c ramstage-y += cbmem.c -ramstage-y += monotonic_timer.c ramstage-y += i2c.c ramstage-y += media.c +ramstage-y += monotonic_timer.c $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@

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Patch set updated for coreboot: e686985 bg4cd: add SPI controller driver skeleton
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9355 -gerrit commit e68698579407017343706e4d5991c72632522b09 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:07:41 2014 -0700 bg4cd: add SPI controller driver skeleton This file provides the SOC specific SPI driver API, it needs to be filled up with code. Function descriptions can be found in src/include/spi-generic.h. BRANCH=none BUG=chrome-os-partner:32631 TEST=compiles with the upcoming patches applied. Change-Id: I3546d5f9fb2971f4ccb7a57ce8164fd77686af72 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0583f17fe3f6a258321765b91eae608e33577afe Original-Change-Id: I0ee04ca17874a13403007bba80d5e8a7708bc625 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223719 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/spi.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c new file mode 100644 index 0000000..8ae22d1 --- /dev/null +++ b/src/soc/marvell/bg4cd/spi.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <spi-generic.h> + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + return NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned out_bytes, void *din, unsigned in_bytes) +{ + return 0; +}

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Patch set updated for coreboot: dca36ee cosmos: add template for soc and board files
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9351 -gerrit commit dca36eec5585f07fed333439c69c9af71dd1640f Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Oct 8 11:38:52 2014 -0700 cosmos: add template for soc and board files This adds board and soc files as a template for cosmos. BUG=chrome-os-partner:32772 BRANCH=none TEST=Built coreboot for cosmos and veyron_pinky. Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I6e17058afaa629c6aa70c2d195230dba782af526 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd9dbcf1023a79921c8501bbe09969d65ca9e742 Original-Change-Id: I676bdf460f5dd996dcce1fc422a69882798bc112 Original-Reviewed-on: https://chromium-review.googlesource.com/222050 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/mainboard/google/Kconfig | 3 ++ src/mainboard/google/cosmos/Kconfig | 57 ++++++++++++++++++++++++ src/mainboard/google/cosmos/Makefile.inc | 40 +++++++++++++++++ src/mainboard/google/cosmos/boardid.c | 25 +++++++++++ src/mainboard/google/cosmos/bootblock.c | 24 +++++++++++ src/mainboard/google/cosmos/chromeos.c | 41 ++++++++++++++++++ src/mainboard/google/cosmos/devicetree.cb | 23 ++++++++++ src/mainboard/google/cosmos/mainboard.c | 38 ++++++++++++++++ src/mainboard/google/cosmos/memlayout.ld | 1 + src/mainboard/google/cosmos/reset.c | 26 +++++++++++ src/mainboard/google/cosmos/romstage.c | 72 +++++++++++++++++++++++++++++++ src/soc/Makefile.inc | 1 + src/soc/marvell/Kconfig | 20 +++++++++ src/soc/marvell/Makefile.inc | 20 +++++++++ src/soc/marvell/bg4cd/Kconfig | 52 ++++++++++++++++++++++ src/soc/marvell/bg4cd/Makefile.inc | 46 ++++++++++++++++++++ src/soc/marvell/bg4cd/cbmem.c | 26 +++++++++++ src/soc/marvell/bg4cd/i2c.c | 30 +++++++++++++ src/soc/marvell/bg4cd/i2c.h | 26 +++++++++++ src/soc/marvell/bg4cd/media.c | 25 +++++++++++ src/soc/marvell/bg4cd/memlayout.ld | 39 +++++++++++++++++ src/soc/marvell/bg4cd/monotonic_timer.c | 29 +++++++++++++ src/soc/marvell/bg4cd/sdram.c | 26 +++++++++++ src/soc/marvell/bg4cd/sdram.h | 24 +++++++++++ 24 files changed, 714 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index c193d81..22e8618 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -25,6 +25,8 @@ config BOARD_GOOGLE_BOLT bool "Bolt" config BOARD_GOOGLE_BUTTERFLY bool "Butterfly" +config BOARD_GOOGLE_COSMOS + bool "Cosmos" config BOARD_GOOGLE_DAISY bool "Daisy" config BOARD_GOOGLE_FALCO @@ -68,6 +70,7 @@ endchoice source "src/mainboard/google/bolt/Kconfig" source "src/mainboard/google/butterfly/Kconfig" +source "src/mainboard/google/cosmos/Kconfig" source "src/mainboard/google/daisy/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig new file mode 100644 index 0000000..4af9986 --- /dev/null +++ b/src/mainboard/google/cosmos/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_COSMOS + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_1024 + select BOARD_ID_SUPPORT + select CHROMEOS + select CHROMEOS_VBNV_FLASH + select SOC_MARVELL_BG4CD + select MAINBOARD_HAS_BOOTBLOCK_INIT + select HAVE_HARD_RESET + select RETURN_FROM_VERSTAGE + +config MAINBOARD_DIR + string + default google/cosmos + +config MAINBOARD_PART_NUMBER + string + default "Cosmos" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_GOOGLE_COSMOS diff --git a/src/mainboard/google/cosmos/Makefile.inc b/src/mainboard/google/cosmos/Makefile.inc new file mode 100644 index 0000000..3e970fb --- /dev/null +++ b/src/mainboard/google/cosmos/Makefile.inc @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/cosmos/boardid.c b/src/mainboard/google/cosmos/boardid.c new file mode 100644 index 0000000..8b61891 --- /dev/null +++ b/src/mainboard/google/cosmos/boardid.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boardid.h> + +uint8_t board_id(void) +{ + return -1; +} diff --git a/src/mainboard/google/cosmos/bootblock.c b/src/mainboard/google/cosmos/bootblock.c new file mode 100644 index 0000000..d5bffea --- /dev/null +++ b/src/mainboard/google/cosmos/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c new file mode 100644 index 0000000..0ad05c8 --- /dev/null +++ b/src/mainboard/google/cosmos/chromeos.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/google/cosmos/devicetree.cb b/src/mainboard/google/cosmos/devicetree.cb new file mode 100644 index 0000000..b82d57c --- /dev/null +++ b/src/mainboard/google/cosmos/devicetree.cb @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/marvell/bg4cd + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/cosmos/mainboard.c b/src/mainboard/google/cosmos/mainboard.c new file mode 100644 index 0000000..5866fea --- /dev/null +++ b/src/mainboard/google/cosmos/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ +} diff --git a/src/mainboard/google/cosmos/memlayout.ld b/src/mainboard/google/cosmos/memlayout.ld new file mode 100644 index 0000000..d788b78 --- /dev/null +++ b/src/mainboard/google/cosmos/memlayout.ld @@ -0,0 +1 @@ +#include <soc/marvell/bg4cd/memlayout.ld> diff --git a/src/mainboard/google/cosmos/reset.c b/src/mainboard/google/cosmos/reset.c new file mode 100644 index 0000000..8020fbf --- /dev/null +++ b/src/mainboard/google/cosmos/reset.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <reset.h> + +void hard_reset(void) +{ + while (1) + ; +} diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c new file mode 100644 index 0000000..f3e98e0 --- /dev/null +++ b/src/mainboard/google/cosmos/romstage.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <armv7.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/cache.h> +#include <arch/exception.h> +#include <stdlib.h> +#include <program_loading.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/marvell/bg4cd/sdram.h> +#include <symbols.h> +#include "timer.h" + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif + + console_init(); + +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif + sdram_init(); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif + mmu_init(); + mmu_config_range(0, 4096, DCACHE_OFF); + dcache_mmu_enable(); + + cbmem_initialize_empty(); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); +#endif + run_ramstage(); +} diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index 543e155..b722323 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -3,6 +3,7 @@ ################################################################################ subdirs-y += imgtec subdirs-y += intel +subdirs-y += marvell subdirs-y += nvidia subdirs-y += qualcomm subdirs-y += rockchip diff --git a/src/soc/marvell/Kconfig b/src/soc/marvell/Kconfig new file mode 100644 index 0000000..95b8c50 --- /dev/null +++ b/src/soc/marvell/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/soc/marvell/bg4cd/Kconfig diff --git a/src/soc/marvell/Makefile.inc b/src/soc/marvell/Makefile.inc new file mode 100644 index 0000000..ef7bcd9 --- /dev/null +++ b/src/soc/marvell/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_SOC_MARVELL_BG4CD) += bg4cd diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig new file mode 100644 index 0000000..0a9778d --- /dev/null +++ b/src/soc/marvell/bg4cd/Kconfig @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_MARVELL_BG4CD + bool + default n + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY + select EARLY_CONSOLE + select DYNAMIC_CBMEM + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + select BOOTBLOCK_CONSOLE + +if SOC_MARVELL_BG4CD + +config BOOTBLOCK_CPU_INIT + string + default "soc/marvell/bg4cd/bootblock.c" + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0008000 + +config CBFS_ROM_OFFSET + hex + default 0x0018000 + +endif diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc new file mode 100644 index 0000000..7d114dd --- /dev/null +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += cbmem.c +bootblock-y += monotonic_timer.c +bootblock-y += media.c +bootblock-y += i2c.c + +verstage-y += monotonic_timer.c +verstage-y += i2c.c +verstage-y += media.c + +romstage-y += cbmem.c +romstage-y += monotonic_timer.c +romstage-y += i2c.c +romstage-y += media.c +romstage-y += sdram.c + +ramstage-y += cbmem.c +ramstage-y += monotonic_timer.c +ramstage-y += i2c.c +ramstage-y += media.c + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + @mkdir -p $(dir $@) + @mv $< $@ diff --git a/src/soc/marvell/bg4cd/cbmem.c b/src/soc/marvell/bg4cd/cbmem.c new file mode 100644 index 0000000..168673d --- /dev/null +++ b/src/soc/marvell/bg4cd/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <stddef.h> + +void *cbmem_top(void) +{ + return NULL; +} diff --git a/src/soc/marvell/bg4cd/i2c.c b/src/soc/marvell/bg4cd/i2c.c new file mode 100644 index 0000000..1aa02d0 --- /dev/null +++ b/src/soc/marvell/bg4cd/i2c.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/i2c.h> +#include "i2c.h" + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) +{ + return 0; +} + +void i2c_init(unsigned int bus, unsigned int hz) +{ +} diff --git a/src/soc/marvell/bg4cd/i2c.h b/src/soc/marvell/bg4cd/i2c.h new file mode 100644 index 0000000..40db31a --- /dev/null +++ b/src/soc/marvell/bg4cd/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_I2C_H__ +#define __SOC_MARVELL_BG4CD_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/marvell/bg4cd/media.c b/src/soc/marvell/bg4cd/media.c new file mode 100644 index 0000000..5a4dc5f --- /dev/null +++ b/src/soc/marvell/bg4cd/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/marvell/bg4cd/memlayout.ld b/src/soc/marvell/bg4cd/memlayout.ld new file mode 100644 index 0000000..45cf395 --- /dev/null +++ b/src/soc/marvell/bg4cd/memlayout.ld @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + + SRAM_START(0x80000000) + TTB(0x80000000, 16K) + BOOTBLOCK(0x80004004, 16K - 4) + VBOOT2_WORK(0x80008000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) + PRERAM_CBFS_CACHE(0x80016000, 4K) + STACK(0x80017000, 4K) + SRAM_END(0x80018000) +} diff --git a/src/soc/marvell/bg4cd/monotonic_timer.c b/src/soc/marvell/bg4cd/monotonic_timer.c new file mode 100644 index 0000000..a84b036 --- /dev/null +++ b/src/soc/marvell/bg4cd/monotonic_timer.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ +} + +void init_timer(void) +{ +} diff --git a/src/soc/marvell/bg4cd/sdram.c b/src/soc/marvell/bg4cd/sdram.c new file mode 100644 index 0000000..1b5575b --- /dev/null +++ b/src/soc/marvell/bg4cd/sdram.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include "sdram.h" + +void sdram_init(void) +{ + printk(BIOS_INFO, "Starting SDRAM initialization...\n"); + printk(BIOS_INFO, "Finish SDRAM initialization...\n"); +} diff --git a/src/soc/marvell/bg4cd/sdram.h b/src/soc/marvell/bg4cd/sdram.h new file mode 100644 index 0000000..6850d27 --- /dev/null +++ b/src/soc/marvell/bg4cd/sdram.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ +#define __SOC_MARVELL_BG4CD_SDRAM_H__ + +void sdram_init(void); +#endif

1 0

Patch merged into coreboot/master: dbe5756 arm64: Add timestamp.c to bootblock and verstage
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit dbe5756bb3530e14e95a86cabbaa9e7a77144fec Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:25:39 2014 -0700 arm64: Add timestamp.c to bootblock and verstage BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully Change-Id: Ia4715fd7a852b82c66d436eb12988f8e3290b9b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0d88dd324a8ee0ace51e9ad2343d81cc828a4f34 Original-Change-Id: I662163848a772018f1e8eb003aa3d3bc06e80e98 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223347 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9359 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/9359 for details. -gerrit

1 0

Patch set updated for coreboot: aaef1be timer: Add generic udelay() implementation
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9334 -gerrit commit aaef1beb12617e5d3aba68f0a7537f41f219c06d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 25 10:05:15 2014 -0500 timer: Add generic udelay() implementation Add GENERIC_UDELAY Kconfig option so that a generic udelay() implementation is provided utilizing the monotonic timer. That way each board/chipset doesn't need to duplicate the same udelay(). Additionally, assume that GENERIC_UDELAY implies init_timer() is not required. BUG=None BRANCH=None TEST=Built nyan, ryu, and rambi. May need help testing. Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219719 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/Kconfig | 7 +++++ src/arch/mips/Makefile.inc | 3 -- src/arch/mips/timer.c | 31 ------------------ src/include/delay.h | 4 +++ src/lib/Makefile.inc | 5 +++ src/lib/timer.c | 42 +++++++++++++++++++++++++ src/soc/nvidia/tegra124/Kconfig | 2 ++ src/soc/nvidia/tegra124/Makefile.inc | 4 --- src/soc/nvidia/tegra124/timer.c | 53 ------------------------------- src/soc/nvidia/tegra132/Kconfig | 1 + src/soc/nvidia/tegra132/Makefile.inc | 3 -- src/soc/nvidia/tegra132/timer.c | 45 -------------------------- src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/timer.c | 27 ---------------- src/soc/samsung/exynos5250/Kconfig | 1 + src/soc/samsung/exynos5250/Makefile.inc | 3 -- src/soc/samsung/exynos5250/timer.c | 52 ------------------------------ src/soc/samsung/exynos5420/Kconfig | 1 + src/soc/samsung/exynos5420/Makefile.inc | 3 -- src/soc/samsung/exynos5420/timer.c | 56 --------------------------------- 20 files changed, 64 insertions(+), 280 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cc87aec..f94fad4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -360,6 +360,13 @@ config HAVE_MONOTONIC_TIMER help The board/chipset provides a monotonic timer. +config GENERIC_UDELAY + def_bool n + depends on HAVE_MONOTONIC_TIMER + help + The board/chipset uses a generic udelay function utilizing the + monotonic timer. + config TIMER_QUEUE def_bool n depends on HAVE_MONOTONIC_TIMER diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 9e88ba8..1929140 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -38,7 +38,6 @@ bootblock-y += boot.c bootblock-y += bootblock.S bootblock-y += bootblock_simple.c bootblock-y += stages.c -bootblock-y += timer.c bootblock-y += ../../lib/memcpy.c bootblock-y += ../../lib/memmove.c bootblock-y += ../../lib/memset.c @@ -64,7 +63,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) romstage-y += boot.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c romstage-y += stages.c -romstage-y += timer.c romstage-y += ../../lib/memcpy.c romstage-y += ../../lib/memmove.c romstage-y += ../../lib/memset.c @@ -85,7 +83,6 @@ ramstage-y += ashldi3.c ramstage-y += boot.c ramstage-y += stages.c ramstage-y += tables.c -ramstage-y += timer.c ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += ../../lib/memset.c diff --git a/src/arch/mips/timer.c b/src/arch/mips/timer.c deleted file mode 100644 index c38601d..0000000 --- a/src/arch/mips/timer.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <timer.h> - -void init_timer(void) -{ - /* TODO */ -} - -void udelay(unsigned usec) -{ - /* TODO */ -} diff --git a/src/include/delay.h b/src/include/delay.h index b3d8ed9..ab1f4f9 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,7 +1,11 @@ #ifndef DELAY_H #define DELAY_H +#if IS_ENABLED(CONFIG_GENERIC_UDELAY) +static inline void init_timer(void) {} +#else void init_timer(void); +#endif void udelay(unsigned usecs); void mdelay(unsigned msecs); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e01d347..079c855 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -22,6 +22,8 @@ bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c + bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c @@ -61,6 +63,8 @@ romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif +romstage-$(CONFIG_GENERIC_UDELAY) += timer.c + ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c @@ -89,6 +93,7 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c +ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/lib/timer.c b/src/lib/timer.c new file mode 100644 index 0000000..a2edc5c --- /dev/null +++ b/src/lib/timer.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void udelay(unsigned usec) +{ + struct stopwatch sw; + + /* + * As the timer granularity is in microseconds pad the + * requested delay by one to get at least >= requested usec delay. + */ + usec += 1; + + if (!thread_yield_microseconds(usec)) + return; + + stopwatch_init_usecs_expire(&sw, usec); + + while (!stopwatch_expired(&sw)) + ; +} diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 1680f45..3ce368b 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -7,6 +7,8 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select HAVE_HARD_RESET + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select BOOTBLOCK_CONSOLE select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 6de142d..49669eb 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -15,7 +15,6 @@ bootblock-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c bootblock-y += ../tegra/pingroup.c bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c -bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -25,7 +24,6 @@ verstage-y += cbfs.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c -verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c @@ -48,7 +46,6 @@ romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-y += ../tegra/pinmux.c -romstage-y += timer.c romstage-y += cache.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -70,7 +67,6 @@ ramstage-y += ../tegra/i2c.c ramstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c ramstage-y += ../tegra/pinmux.c ramstage-y += ../tegra/usb.c -ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c rmodules_$(ARCH-romstage-y)-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra124/timer.c b/src/soc/nvidia/tegra124/timer.c deleted file mode 100644 index 83f499c..0000000 --- a/src/soc/nvidia/tegra124/timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> - -void init_timer(void) -{ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - if (!thread_yield_microseconds(usec)) - return; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} - diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index c87698a..0a1b28b 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -8,6 +8,7 @@ config SOC_NVIDIA_TEGRA132 select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL select HAVE_UART_MEMORY_MAPPED diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 81d08f5..8ad9b83 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -1,7 +1,6 @@ bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c -bootblock-y += timer.c bootblock-y += clock.c bootblock-y += spi.c bootblock-y += i2c.c @@ -26,7 +25,6 @@ romstage-y += romstage_asm.S romstage-y += addressmap.c romstage-y += cbfs.c romstage-y += cbmem.c -romstage-y += timer.c romstage-y += ccplex.c romstage-y += clock.c romstage-y += cpu.c @@ -53,7 +51,6 @@ ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += cpu.c ramstage-y += cpu_lib.S -ramstage-y += timer.c ramstage-y += clock.c ramstage-y += soc.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c deleted file mode 100644 index ed10340..0000000 --- a/src/soc/nvidia/tegra132/timer.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <timer.h> -#include <delay.h> -#include <thread.h> - -void init_timer(void) -{ -} - -void udelay(unsigned usec) -{ - struct stopwatch sw; - - /* - * As the hardware clock granularity is in microseconds pad the - * requested delay by one to get at least >= requested usec delay. - */ - usec += 1; - - if (!thread_yield_microseconds(usec)) - return; - - stopwatch_init_usecs_expire(&sw, usec); - while (!stopwatch_expired(&sw)) - ; -} diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0865fe8..70951a5 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -26,6 +26,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 7162482..658f4d7 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -23,36 +23,9 @@ #include <soc/timer.h> #include <timer.h> -void init_timer(void) -{ -} - void rk3288_init_timer(void) { write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0); write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1); write32(1, &timer7_ptr->timer_ctrl_reg); } - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} - diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 4126ec1..7034e96 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS5250 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_SPECIAL bool default n diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 4483f82..4cf2d96 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -10,7 +10,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c alternate_cbfs.c romstage-y += clock.c @@ -24,7 +23,6 @@ romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += wakeup.c romstage-y += gpio.c -romstage-y += timer.c romstage-y += trustzone.c romstage-y += i2c.c #romstage-y += wdt.c @@ -40,7 +38,6 @@ ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c ramstage-y += monotonic_timer.c -ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp-reg.c diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c deleted file mode 100644 index 891c3d7..0000000 --- a/src/soc/samsung/exynos5250/timer.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <delay.h> -#include <soc/clk.h> -#include <timer.h> - -void init_timer(void) -{ - /* Nothing to do because we manually - * call mct_start() in the bootblock - */ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -} diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index ed9d2f8..072976a 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS5420 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY select HAVE_UART_SPECIAL select RELOCATABLE_MODULES bool diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index eab4fb3..4e92864 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -10,7 +10,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c bootblock-y += gpio.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c alternate_cbfs.c romstage-y += smp.c @@ -25,7 +24,6 @@ romstage-y += monotonic_timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += wakeup.c romstage-y += gpio.c -romstage-y += timer.c romstage-y += i2c.c #romstage-y += wdt.c romstage-y += cbmem.c @@ -41,7 +39,6 @@ ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c ramstage-y += monotonic_timer.c -ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += dp.c dp_lowlevel.c fimd.c diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c deleted file mode 100644 index 7156a01..0000000 --- a/src/soc/samsung/exynos5420/timer.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <delay.h> -#include <soc/clk.h> -#include <thread.h> -#include <timer.h> - -void init_timer(void) -{ - /* Nothing to do because we manually - * call mct_start() in the bootblock - */ -} - -/* delay x useconds */ -void udelay(unsigned usec) -{ - struct mono_time current, end; - - if (!thread_yield_microseconds(usec)) - return; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, usec); - - if (mono_time_after(&current, &end)) { - printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", - usec); - /* There's not much we can do if usec is too big. Use a long, - * paranoid delay value and hope for the best... */ - end = current; - mono_time_add_usecs(&end, USECS_PER_SEC); - } - - while (mono_time_before(&current, &end)) - timer_monotonic_get(&current); -}

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Patch merged into coreboot/master: f0d21ff tegra124: Change all SoC headers to <soc/headername.h> system
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit f0d21ff3dab80b1583fd6432f152111de2c6df02 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:24:14 2014 -0700 tegra124: Change all SoC headers to <soc/headername.h> system This patch aligns tegra124 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze. Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88 Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224504 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9326 for details. -gerrit

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Patch merged into coreboot/master: 73d1ed6 ipq806x: Change all SoC headers to <soc/headername.h> system
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 73d1ed66d316489d8dfd7f1b61dd0c4fceb0e24b Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:20:49 2014 -0700 ipq806x: Change all SoC headers to <soc/headername.h> system This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Storm. Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9368 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9368 for details. -gerrit

1 0

Patch merged into coreboot/master: f8c8703 libpayload: Add drivers for bg4cd
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit f8c8703be0a828366a3921062c40ffa4dd827365 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 9 09:56:43 2014 -0700 libpayload: Add drivers for bg4cd BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9360 for details. -gerrit

1 0

Patch merged into coreboot/master: 94e4d81 console: fix Kconfig uses
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 94e4d81d073caeb3ac4b8fd0bbe20df9f98a2161 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Apr 7 13:49:32 2015 +0200 console: fix Kconfig uses While upstreaming, some old (or downstream) names sneaked in. Change-Id: I148fd8f46bc88c38ce1f62efe5771555bd5dcc5c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9350 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9350 for details. -gerrit

1 0

Patch merged into coreboot/master: 7a453eb rk3288: Change all SoC headers to <soc/headername.h> system
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 7a453ebed2b87780100391b7ab78d41337890a66 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:14:55 2014 -0700 rk3288: Change all SoC headers to <soc/headername.h> system This patch is the start of a series to change all non-x86 SoC-specific headers to be included as <soc/header.h> instead of the old <soc/vendor/chip/header.h> or "header.h". It will add an include/soc/ directory under every src/soc/vendor/chip/ and append the .../include/ part of that to the global include path. This matches the usage of <arch/header.h> for architecture-specific headers and had already been done for some headers on Tegra. It has the advantage that a source file which does not know the specific SoC used (e.g. Tegra files common for multiple chips, or a global include file) can still include SoC-specific headers and access macros/types defined there. It also makes the includes for mainboard files more readable, and reduces the chance to pull in a wrong header when copying mainboard sources to use a different-related SoC (e.g. using a Tegra124 mainboard as template for a Tegra132 one). For easier maintainability, every SoC family is modified individually. This patch starts out by changing Rk3288. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Whole series: compared binary images for Daisy, Nyan_Blaze, Rush_Ryu, Storm, Urara and Veyron_Pinky. Confirmed that they are byte-for-byte identical except for timestamps, hashes, and __LINE__ macro replacements. Compile-tested individual patches. Change-Id: I4d74a0c56be278e591a9cf43f93e9900e41f4319 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4ad8b6d2e0280428aa9742f0f7b723c00857334a Original-Change-Id: I415b8dbe735e572d4ae2cb1df62d66bcce386fff Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222025 Reviewed-on: http://review.coreboot.org/9349 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9349 for details. -gerrit

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coreboot-gerrit April 2015