coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 01f5003 build system: Fix SeaBIOS integration with multilib compilers
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9378 -gerrit commit 01f50036abe2bc8d70fa49eba20e5a0ff0085b42 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 8 11:05:37 2015 +0200 build system: Fix SeaBIOS integration with multilib compilers SeaBIOS doesn't like CC and LD to contain arguments, so split those out. Change-Id: Id651719d529adfa8602a3e4f6685228330f36432 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/x86/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e48913c..3b3d26a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -318,7 +318,9 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ - CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ + CC=$(word 1,$(CC_x86_32)) CFLAGS="$(patsubst $(word 1,$(CC_x86_32))%,,$(CC_x86_32))" \ + LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \ + OBJDUMP="$(OBJDUMP_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \ AS="$(AS_x86_32)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \

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New patch to review for coreboot: 2d65612 Makefile.inc: Only add `-Wno-unused-but-set-variable` for GCC
by Paul Menzel 08 Apr '15

08 Apr '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9377 -gerrit commit 2d656121bc72566e2ddd1bcf698449a1abaab2e3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Apr 8 10:53:39 2015 +0200 Makefile.inc: Only add `-Wno-unused-but-set-variable` for GCC Clang (3.5) does not know that option. error: unknown warning option '-Wno-unused-but-set-variable'; did you mean '-Wno-unused-const-variable'? [-Werror,-Wunknown-warning-option] Fix up commit f69a99db (coreboot: x86: enable gc-sections) to only add that option, when GCC is used. Change-Id: I65b41133a806df1803ccc445e27184c579a718a0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- Makefile.inc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 2d3ae2b..10759f5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -237,7 +237,13 @@ CPPFLAGS_common += -include $(src)/include/kconfig.h CFLAGS_common += -pipe -g -nostdinc CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wno-unused-but-set-variable +CFLAGS_common += -Wstrict-aliasing -Wshadow + +ifeq ($(CONFIG_COMPILER_GCC),y) +# cf. commit f69a99db (coreboot: x86: enable gc-sections) +CFLAGS_common += -Wno-unused-but-set-variable +endif + ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror endif

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Patch set updated for coreboot: 3332677 pistachio: implement timer support
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9188 -gerrit commit 33326778526467757274d993e3511b98a08d236e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 5 17:50:09 2014 -0800 pistachio: implement timer support C0_COUNT register is a free running counter clocked by the CPU frequency divided by two. On the FPGA board it results in 25 MHz, on real SOCs it will have to be figured out later. Some magic addresses and numbers are used to find out if the code is running on the FPGA board. timestamp_get() and timer_monotonic_get() are kept in the same file. The CPU initialization makes sure that CO COUNT is in fact enabled and starts from zero. BRANCH=none BUG=chrome-os-partner:33595,chrome-os-partner:31438 TEST=with timer enabled, the startup code properly initializes UART and prints the coreboot bootblock banner message on the serial console. Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05 Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227888 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Makefile.inc | 3 --- src/soc/imgtec/pistachio/bootblock.c | 15 +++++++++++++++ src/soc/imgtec/pistachio/include/soc/cpu.h | 7 +++++++ src/soc/imgtec/pistachio/monotonic_timer.c | 26 +++++++++++++++++++++++++- src/soc/imgtec/pistachio/timestamp.c | 19 ------------------- 5 files changed, 47 insertions(+), 23 deletions(-) diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index e955968..f7a0848 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -31,16 +31,13 @@ ramstage-y += uart.c endif bootblock-y += monotonic_timer.c -bootblock-y += timestamp.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c -ramstage-y += timestamp.c romstage-y += cbmem.c romstage-y += romstage.c romstage-y += monotonic_timer.c -romstage-y += timestamp.c CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index f6cc76b..9011264 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -19,6 +19,21 @@ * MA 02110-1301 USA */ +#include <stdint.h> +#include <arch/cpu.h> + static void bootblock_cpu_init(void) { + uint32_t cause; + + /* + * Make sure the count register is counting by clearing the "Disable + * Counter" bit, in case it is set. + */ + cause = read_c0_cause(); + if (cause & C0_CAUSE_DC) + write_c0_cause(cause & ~(C0_CAUSE_DC)); + + /* And make sure that it starts from zero. */ + write_c0_count(0); } diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h index c61c58d..72775b5 100644 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -21,4 +21,11 @@ #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 +/* + * Reading at this address allows to identify the platform the code is running + * on. + */ +#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) +#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index a8fe27c..99c147b 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -17,9 +17,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <timer.h> +#include <timestamp.h> +#include <arch/cpu.h> +#include <soc/cpu.h> + +static int get_count_mhz_freq(void) +{ + static unsigned count_mhz_freq; + + if (!count_mhz_freq) { + if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) + count_mhz_freq = 25; /* FPGA board */ + /* + * Will need some means of finding out the counter + * frequency on a real SOC + */ + } + return count_mhz_freq; +} void timer_monotonic_get(struct mono_time *mt) { - /* to be defined */ + mt->microseconds = (long)timestamp_get(); +} + +uint64_t timestamp_get(void) +{ + return read_c0_count()/get_count_mhz_freq(); } diff --git a/src/soc/imgtec/pistachio/timestamp.c b/src/soc/imgtec/pistachio/timestamp.c deleted file mode 100644 index f0dc5ad..0000000 --- a/src/soc/imgtec/pistachio/timestamp.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <timestamp.h> - -uint64_t timestamp_get(void) -{ - return 0; -}

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Patch set updated for coreboot: b1d8418 pistachio: allow more room for bootblock
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9190 -gerrit commit b1d8418b8d205ba10bb0be8845a77e1db0ce8c11 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:28:23 2014 -0800 pistachio: allow more room for bootblock 32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/urara/Kconfig | 1 + src/soc/imgtec/pistachio/Kconfig | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index a9363f9..26add60 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -23,6 +23,7 @@ if BOARD_GOOGLE_URARA config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_512 select BOOTBLOCK_CONSOLE select CONFIG_SPI_FLASH_WINBOND select CPU_IMGTEC_PISTACHIO diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 70e5741..4671444 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -37,11 +37,11 @@ config BOOTBLOCK_CPU_INIT config CBFS_ROM_OFFSET hex - default 0x4100 + default 0x8100 config CBFS_HEADER_ROM_OFFSET # Effectively the maximum size of the bootblock hex - default 0x4000 + default 0x8000 endif

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Patch set updated for coreboot: 760887f pistachio: set correct CBMEM top address
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9191 -gerrit commit 760887ff0dac2c1eebb1e0067d807ec28d5a032c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:31:40 2014 -0800 pistachio: set correct CBMEM top address This is required for proper dynamic CBMEM operation. BRANCH=none BUG=chrome-os-partner:31438 TEST=urara ramstage does not crash anymore in CBMEM initialization Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232292 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/cbmem.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 373d4f8..1aed030 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -25,6 +25,5 @@ void *cbmem_top(void) { - uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20; - return _dram + top; + return _dram + (CONFIG_DRAM_SIZE_MB << 20); }

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Patch set updated for coreboot: cedc2fa pistachio: modify memory layout
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9337 -gerrit commit cedc2fa3a02d8c32f8365712eaded97484eaf1f3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 20:14:47 2014 -0800 pistachio: modify memory layout With the code now running on the FPGA board it makes sense to correct the memory layout definitions to match the actual hardware. Note that the latest FPGA board firmware introduced support of the additional 128KB of SRAM (called GRAM) at base address of 0x9a000000. These are still interim values, which will be tweaked when the actual bring up board is available. BRANCH=none BUG=chrome-os-partner:31438 TEST=the code put into SPI NOR flash boots all the way to ramstage. Change-Id: I00aa5bc3aabba50df2187bb208cf2fcd11b26b3d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a6378be5cd304744b40c57a34d7a276233d45779 Original-Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229203 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 21c3d73..554ebfc 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -21,18 +21,19 @@ #include <arch/header.ld> -/* TODO: This should be revised by someone who understands the SoC better. */ - SECTIONS { - CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */ - DRAM_START(0x80000000) RAMSTAGE(0x80000000, 128K) - /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */ - BOOTBLOCK(0x9B000000, 16K) - ROMSTAGE(0x9B004000, 40K) - STACK(0x9B00E000, 6K) - PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K) + /* GRAM becomes the SRAM. */ + SRAM_START(0x9a000000) + BOOTBLOCK(0x9a000000, 16K) + ROMSTAGE(0x9a004000, 32K) + STACK(0x9a01c000, 8K) + PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K) + SRAM_END(0x9a020000) + + /* Let's use SRAM for CBFS cache. */ + CBFS_CACHE(0x9b000000, 64K) }

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Patch set updated for coreboot: ff0e069 pistachio: add SOC descriptor
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9192 -gerrit commit ff0e0694538bcff8702250243b0db08fb0c069c2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Dec 1 18:34:37 2014 -0800 pistachio: add SOC descriptor With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start: ... Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038 Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232571 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/urara/devicetree.cb | 1 + src/soc/imgtec/pistachio/Makefile.inc | 1 + src/soc/imgtec/pistachio/soc.c | 48 ++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb index a328b9d..e3eb091 100644 --- a/src/mainboard/google/urara/devicetree.cb +++ b/src/mainboard/google/urara/devicetree.cb @@ -20,6 +20,7 @@ # chip soc/imgtec/pistachio + device cpu_cluster 0 on end chip drivers/generic/generic # I2C0 controller device i2c 6 on end # Fake component for testing end diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index f7a0848..fdeba0c 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += monotonic_timer.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c +ramstage-y += soc.c romstage-y += cbmem.c romstage-y += romstage.c diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c new file mode 100644 index 0000000..7c2884f --- /dev/null +++ b/src/soc/imgtec/pistachio/soc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <symbols.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, + (CONFIG_DRAM_SIZE_MB * MiB) / KiB); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_imgtec_pistachio_ops = { + CHIP_NAME("SOC: Imgtec Pistachio") + .enable_dev = enable_soc_dev, +};

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Patch set updated for coreboot: 60c8fa7 pistachio: add timer frequency for SOC; correct platform ID
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9193 -gerrit commit 60c8fa780e8d4b690b78bf8ec7050ec007793714 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Jan 19 02:39:18 2015 +0000 pistachio: add timer frequency for SOC; correct platform ID Corrected platform ID and added timer frequency for SOC. The timer frequency is half the CPU frequency. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241426 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/cpu.h | 12 ++++++++---- src/soc/imgtec/pistachio/monotonic_timer.c | 19 ++++++++++++++++--- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h index 72775b5..8995219 100644 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -18,14 +18,18 @@ #ifndef __SOC_IMGTEC_DANUBE_CPU_H__ #define __SOC_IMGTEC_DANUBE_CPU_H__ +#include <arch/io.h> + #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 /* - * Reading at this address allows to identify the platform the code is running - * on. + * This register holds the FPGA image version + * If we're not working on the FPGA this will be 0 */ -#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) -#define IMG_PLATFORM_ID_SILICON 0xF00D0006 +#define PRIMARY_FPGA_VERSION 0xB8149060 +#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) +#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ +#define IMG_PLATFORM_ID_SILICON 0 #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index 99c147b..c2408b0 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -23,6 +23,9 @@ #include <arch/cpu.h> #include <soc/cpu.h> +#define PISTACHIO_CLOCK_SWITCH 0xB8144200 +#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 + static int get_count_mhz_freq(void) { static unsigned count_mhz_freq; @@ -30,10 +33,20 @@ static int get_count_mhz_freq(void) if (!count_mhz_freq) { if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) count_mhz_freq = 25; /* FPGA board */ - /* - * Will need some means of finding out the counter - * frequency on a real SOC + else { + /* If MIPS PLL external bypass bit is set, it means + * that the MIPS PLL is already set up to work at a + * frequency of 550 MHz; otherwise, the crystal is + * used with a frequency of 52 MHz */ + if (read32(PISTACHIO_CLOCK_SWITCH) & + MIPS_EXTERN_PLL_BYPASS_MASK) + /* Half MIPS PLL freq. */ + count_mhz_freq = 275; + else + /* Half Xtal freq. */ + count_mhz_freq = 26; + } } return count_mhz_freq; }

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Patch set updated for coreboot: 26c04de bg4cd, cosmos: use SPI_WRAPPER configuration mode
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9356 -gerrit commit 26c04decba03d520628283142539cd9c4a9801b0 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 11:20:15 2014 -0700 bg4cd, cosmos: use SPI_WRAPPER configuration mode The SOC code should include the SPI controller driver when configured. Enable SPI support for cosmos. BRANCH=none BUG=chrome-os-partner:32631 TEST=cosmos builds Change-Id: I8212f191b7d80f0bee86f746813edaf8e5ee6db1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fd4853be5157247bb73fc22b9d4f8300228fe6ce Original-Change-Id: If7e12e2fb04e63c36d9696d13e08397b91a77a8c Original-Commit-Id: 7b1d095e5df6a864d3564bbf7a20cc211f75629a Original-Change-Id: If9dd80cb96120d34a0865f7882cd62e45fed749d Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223750 Original-Reviewed-on: https://chromium-review.googlesource.com/223752 --- src/mainboard/google/cosmos/Kconfig | 7 +++++-- src/soc/marvell/bg4cd/Makefile.inc | 8 ++++---- src/soc/marvell/bg4cd/media.c | 25 ------------------------- 3 files changed, 9 insertions(+), 31 deletions(-) diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index 4af9986..2aa4362 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -25,10 +25,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ID_SUPPORT select CHROMEOS select CHROMEOS_VBNV_FLASH - select SOC_MARVELL_BG4CD - select MAINBOARD_HAS_BOOTBLOCK_INIT + select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET + select MAINBOARD_HAS_BOOTBLOCK_INIT select RETURN_FROM_VERSTAGE + select SOC_MARVELL_BG4CD + select SPI_FLASH + select SPI_FLASH_SPANSION config MAINBOARD_DIR string diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 7d49486..af390d1 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -19,23 +19,23 @@ bootblock-y += cbmem.c bootblock-y += i2c.c -bootblock-y += media.c bootblock-y += monotonic_timer.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c verstage-y += i2c.c -verstage-y += media.c verstage-y += monotonic_timer.c +verstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += cbmem.c romstage-y += i2c.c -romstage-y += media.c romstage-y += monotonic_timer.c romstage-y += sdram.c +romstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += cbmem.c ramstage-y += i2c.c -ramstage-y += media.c ramstage-y += monotonic_timer.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/marvell/bg4cd/media.c b/src/soc/marvell/bg4cd/media.c deleted file mode 100644 index 5a4dc5f..0000000 --- a/src/soc/marvell/bg4cd/media.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cbfs.h> - -int init_default_cbfs_media(struct cbfs_media *media) -{ - return 0; -}

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Patch set updated for coreboot: 49196f2 bg4cd: Change all SoC headers to <soc/headername.h> system
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9358 -gerrit commit 49196f260adf0ac650f8eda2512e2b189197cb4f Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 14:21:22 2014 -0700 bg4cd: Change all SoC headers to <soc/headername.h> system This patch aligns bg4cd to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Cosmos. Change-Id: I32a4407f7deb2b1752b6220a140352724f320637 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b6bb6990417863010258632374c3f5ac19350c9 Original-Change-Id: Ia5299659ad186f2e7d698adfa7562396e747473f Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224506 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/cosmos/memlayout.ld | 2 +- src/mainboard/google/cosmos/romstage.c | 19 +++++++------ src/soc/marvell/bg4cd/Makefile.inc | 2 ++ src/soc/marvell/bg4cd/i2c.c | 2 +- src/soc/marvell/bg4cd/i2c.h | 26 ----------------- src/soc/marvell/bg4cd/include/soc/i2c.h | 26 +++++++++++++++++ src/soc/marvell/bg4cd/include/soc/memlayout.ld | 39 ++++++++++++++++++++++++++ src/soc/marvell/bg4cd/include/soc/sdram.h | 24 ++++++++++++++++ src/soc/marvell/bg4cd/memlayout.ld | 39 -------------------------- src/soc/marvell/bg4cd/sdram.c | 2 +- src/soc/marvell/bg4cd/sdram.h | 24 ---------------- 11 files changed, 104 insertions(+), 101 deletions(-) diff --git a/src/mainboard/google/cosmos/memlayout.ld b/src/mainboard/google/cosmos/memlayout.ld index d788b78..ead7f47 100644 --- a/src/mainboard/google/cosmos/memlayout.ld +++ b/src/mainboard/google/cosmos/memlayout.ld @@ -1 +1 @@ -#include <soc/marvell/bg4cd/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index f3e98e0..0c64728 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -17,21 +17,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/stages.h> #include <armv7.h> #include <cbfs.h> -#include <console/console.h> -#include <arch/stages.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> -#include <timestamp.h> -#include <arch/cache.h> -#include <arch/exception.h> -#include <stdlib.h> #include <program_loading.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/marvell/bg4cd/sdram.h> +#include <soc/sdram.h> +#include <stdlib.h> #include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + #include "timer.h" void main(void) diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index af390d1..18f9d8d 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -37,6 +37,8 @@ ramstage-y += i2c.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_SPI_FLASH) += spi.c +CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/ + $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/marvell/bg4cd/i2c.c b/src/soc/marvell/bg4cd/i2c.c index 1aa02d0..16ad9ab 100644 --- a/src/soc/marvell/bg4cd/i2c.c +++ b/src/soc/marvell/bg4cd/i2c.c @@ -18,7 +18,7 @@ */ #include <device/i2c.h> -#include "i2c.h" +#include <soc/i2c.h> int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) { diff --git a/src/soc/marvell/bg4cd/i2c.h b/src/soc/marvell/bg4cd/i2c.h deleted file mode 100644 index 40db31a..0000000 --- a/src/soc/marvell/bg4cd/i2c.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_MARVELL_BG4CD_I2C_H__ -#define __SOC_MARVELL_BG4CD_I2C_H__ - -void i2c_init(unsigned int bus, unsigned int hz); - -#endif - diff --git a/src/soc/marvell/bg4cd/include/soc/i2c.h b/src/soc/marvell/bg4cd/include/soc/i2c.h new file mode 100644 index 0000000..40db31a --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_I2C_H__ +#define __SOC_MARVELL_BG4CD_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld new file mode 100644 index 0000000..45cf395 --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + + SRAM_START(0x80000000) + TTB(0x80000000, 16K) + BOOTBLOCK(0x80004004, 16K - 4) + VBOOT2_WORK(0x80008000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) + PRERAM_CBFS_CACHE(0x80016000, 4K) + STACK(0x80017000, 4K) + SRAM_END(0x80018000) +} diff --git a/src/soc/marvell/bg4cd/include/soc/sdram.h b/src/soc/marvell/bg4cd/include/soc/sdram.h new file mode 100644 index 0000000..6850d27 --- /dev/null +++ b/src/soc/marvell/bg4cd/include/soc/sdram.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ +#define __SOC_MARVELL_BG4CD_SDRAM_H__ + +void sdram_init(void); +#endif diff --git a/src/soc/marvell/bg4cd/memlayout.ld b/src/soc/marvell/bg4cd/memlayout.ld deleted file mode 100644 index 45cf395..0000000 --- a/src/soc/marvell/bg4cd/memlayout.ld +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> - -#include <arch/header.ld> - -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - - SRAM_START(0x80000000) - TTB(0x80000000, 16K) - BOOTBLOCK(0x80004004, 16K - 4) - VBOOT2_WORK(0x80008000, 16K) - OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) - PRERAM_CBFS_CACHE(0x80016000, 4K) - STACK(0x80017000, 4K) - SRAM_END(0x80018000) -} diff --git a/src/soc/marvell/bg4cd/sdram.c b/src/soc/marvell/bg4cd/sdram.c index 1b5575b..0ebee15 100644 --- a/src/soc/marvell/bg4cd/sdram.c +++ b/src/soc/marvell/bg4cd/sdram.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> -#include "sdram.h" +#include <soc/sdram.h> void sdram_init(void) { diff --git a/src/soc/marvell/bg4cd/sdram.h b/src/soc/marvell/bg4cd/sdram.h deleted file mode 100644 index 6850d27..0000000 --- a/src/soc/marvell/bg4cd/sdram.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ -#define __SOC_MARVELL_BG4CD_SDRAM_H__ - -void sdram_init(void); -#endif

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coreboot-gerrit April 2015