coreboot-gerrit April 2015

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Patch set updated for coreboot: 104febb ipq806x: Change all SoC headers to <soc/headername.h> system
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9368 -gerrit commit 104febb9ad02e5a4aa95e61dc0bc9211b85acd15 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:20:49 2014 -0700 ipq806x: Change all SoC headers to <soc/headername.h> system This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Storm. Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/storm/boardid.c | 2 +- src/mainboard/google/storm/cdp.c | 4 +- src/mainboard/google/storm/mainboard.c | 7 +- src/mainboard/google/storm/memlayout.ld | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 2 + src/soc/qualcomm/ipq806x/clock.c | 2 +- src/soc/qualcomm/ipq806x/gpio.c | 4 +- src/soc/qualcomm/ipq806x/include/cdp.h | 137 ----------- src/soc/qualcomm/ipq806x/include/clock.h | 196 --------------- src/soc/qualcomm/ipq806x/include/gpio.h | 110 --------- src/soc/qualcomm/ipq806x/include/gsbi.h | 35 --- src/soc/qualcomm/ipq806x/include/iomap.h | 110 --------- src/soc/qualcomm/ipq806x/include/ipq_timer.h | 40 --- src/soc/qualcomm/ipq806x/include/ipq_uart.h | 271 --------------------- src/soc/qualcomm/ipq806x/include/soc/cdp.h | 139 +++++++++++ src/soc/qualcomm/ipq806x/include/soc/clock.h | 196 +++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/gpio.h | 110 +++++++++ src/soc/qualcomm/ipq806x/include/soc/gsbi.h | 35 +++ src/soc/qualcomm/ipq806x/include/soc/iomap.h | 110 +++++++++ src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h | 40 +++ src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h | 271 +++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 40 +++ src/soc/qualcomm/ipq806x/include/soc/spi.h | 282 ++++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/usb.h | 26 ++ src/soc/qualcomm/ipq806x/include/spi.h | 282 ---------------------- src/soc/qualcomm/ipq806x/include/usb.h | 26 -- src/soc/qualcomm/ipq806x/memlayout.ld | 40 --- src/soc/qualcomm/ipq806x/spi.c | 6 +- src/soc/qualcomm/ipq806x/timer.c | 4 +- src/soc/qualcomm/ipq806x/uart.c | 10 +- src/soc/qualcomm/ipq806x/usb.c | 9 +- 31 files changed, 1275 insertions(+), 1273 deletions(-) diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 683b5f4..a8dd844 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> #include <boardid.h> #include <gpiolib.h> #include <console/console.h> +#include <stdlib.h> /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 94845c7..7e1aeb6 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,9 +1,9 @@ /* * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.* */ +#include <soc/gpio.h> +#include <soc/cdp.h> #include <types.h> -#include <cdp.h> -#include <gpio.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) { diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 478e2a8..acadce5 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -24,13 +24,12 @@ #include <delay.h> #include <device/device.h> #include <gpiolib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/usb.h> #include <string.h> #include <symbols.h> -#include <soc/qualcomm/ipq806x/include/clock.h> -#include <soc/qualcomm/ipq806x/include/gpio.h> -#include <soc/qualcomm/ipq806x/include/usb.h> - /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram / MiB) #define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld index 1735835..ead7f47 100644 --- a/src/mainboard/google/storm/memlayout.ld +++ b/src/mainboard/google/storm/memlayout.ld @@ -1 +1 @@ -#include <soc/qualcomm/ipq806x/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 5dfca4d..6ee925c 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -40,6 +40,8 @@ ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += usb.c +INCLUDES += -Isrc/soc/qualcomm/ipq806x/include/ + ifeq ($(CONFIG_USE_BLOBS),y) # Generate the actual coreboot bootblock code diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index ee2ed64..fe7cfb8 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -3,8 +3,8 @@ */ #include <delay.h> +#include <soc/clock.h> #include <types.h> -#include <clock.h> /** * uart_pll_vote_clk_enable - enables PLL8 diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 8cce3ba..46dca4e 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -28,9 +28,9 @@ * SUCH DAMAGE. */ -#include <iomap.h> -#include <gpio.h> #include <arch/io.h> +#include <soc/gpio.h> +#include <soc/iomap.h> /******************************************************* Function description: check for invalid GPIO # diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h deleted file mode 100644 index 15f91cb..0000000 --- a/src/soc/qualcomm/ipq806x/include/cdp.h +++ /dev/null @@ -1,137 +0,0 @@ -/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ - - -#ifndef _IPQ806X_CDP_H_ -#define _IPQ806X_CDP_H_ - -unsigned smem_get_board_machtype(void); - -typedef enum { - PHY_INTERFACE_MODE_MII, - PHY_INTERFACE_MODE_GMII, - PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TBI, - PHY_INTERFACE_MODE_RMII, - PHY_INTERFACE_MODE_RGMII, - PHY_INTERFACE_MODE_RGMII_ID, - PHY_INTERFACE_MODE_RGMII_RXID, - PHY_INTERFACE_MODE_RGMII_TXID, - PHY_INTERFACE_MODE_RTBI, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_NONE /* Must be last */ -} phy_interface_t; - -typedef struct { - unsigned int gpio; - unsigned int func; - unsigned int dir; - unsigned int pull; - unsigned int drvstr; - unsigned int enable; -} gpio_func_data_t; - -typedef struct { - unsigned int m_value; - unsigned int n_value; - unsigned int d_value; -} uart_clk_mnd_t; - -/* SPI Mode */ - -typedef enum { - NOR_SPI_MODE_0, - NOR_SPI_MODE_1, - NOR_SPI_MODE_2, - NOR_SPI_MODE_3, -} spi_mode; - -/* SPI GSBI Bus number */ - -typedef enum { - GSBI_BUS_5 = 0, - GSBI_BUS_6, - GSBI_BUS_7, -} spi_gsbi_bus_num; - -/* SPI Chip selects */ - -typedef enum { - SPI_CS_0 , - SPI_CS_1, - SPI_CS_2, - SPI_CS_3, -} spi_cs; - -/* Flash Types */ - -typedef enum { - ONLY_NAND, - ONLY_NOR, - NAND_NOR, - NOR_MMC, -} flash_desc; - -#define NO_OF_DBG_UART_GPIOS 2 - -#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 -#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 - -/* SPI parameters */ - -typedef struct { - spi_mode mode; - spi_gsbi_bus_num bus_number; - spi_cs chip_select; - int vendor; -} spinorflash_params_t; - -typedef struct { - unsigned count; - uint8_t addr[7]; -} ipq_gmac_phy_addr_t; - -typedef struct { - unsigned base; - int unit; - unsigned is_macsec; - unsigned mac_pwr0; - unsigned mac_pwr1; - unsigned mac_conn_to_phy; - phy_interface_t phy; - ipq_gmac_phy_addr_t phy_addr; -} ipq_gmac_board_cfg_t; - -#define IPQ_GMAC_NMACS 4 - -/* Board specific parameters */ -typedef struct { -#if 0 - unsigned int gmac_gpio_count; - gpio_func_data_t *gmac_gpio; - ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; - flash_desc flashdesc; - spinorflash_params_t flash_param; -#endif -} __attribute__ ((__packed__)) board_ipq806x_params_t; - -extern board_ipq806x_params_t *gboard_param; - -#if 0 -static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) -{ - /* - * 'cfg' is valid if and only if - * unit number is non-negative and less than IPQ_GMAC_NMACS. - * 'cfg' pointer lies within the array range of - * board_ipq806x_params_t->gmac_cfg[] - */ - return ((cfg >= &gboard_param->gmac_cfg[0]) && - (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && - (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); -} -#endif - -unsigned int get_board_index(unsigned machid); -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); -#endif diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h deleted file mode 100644 index d9e7834..0000000 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK Boot - * - * Copyright (c) 2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IPQ860X_CLOCK_H_ -#define __IPQ860X_CLOCK_H_ - -#include <iomap.h> - -/* UART clock @ 7.3728 MHz */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC - -/* UART specific definitions */ - -#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) -#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) -#define Uart_mnd_en_mask BIT(8) * !!(625) -#define Uart_en_mask BIT(11) -#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) -#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) -#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) -#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) -#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) -#define BB_PLL_ENA_SC0_REG REG(0x34C0) -#define BB_PLL8_STATUS_REG REG(0x3158) -#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off))) -#define PLL8_STATUS_BIT 16 - -#define PLL_LOCK_DET_STATUS_REG REG(0x03420) -#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) -#define CFPB_CLK_NS_REG REG(0x0264C) -#define CFPB0_HCLK_CTL_REG REG(0x02650) -#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) -#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) -#define EBI2_CLK_CTL_REG REG(0x03B00) - -#define USB30_MASTER_CLK_CTL_REG REG(0x3b24) -#define USB30_MASTER_CLK_MD REG(0x3b28) -#define USB30_MASTER_CLK_NS REG(0x3b2c) -#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34) -#define USB30_MOC_UTMI_CLK_MD REG(0x3b40) -#define USB30_MOC_UTMI_CLK_NS REG(0x3b44) -#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48) -#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c) -#define USB30_RESET REG(0x3b50) - -#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) - -#define CLK_BRANCH_ENA_MASK 0x00000010 -#define CLK_BRANCH_ENA_ENABLE 0x00000010 -#define CLK_BRANCH_ENA_DISABLE 0x00000000 -#define CLK_BRANCH_ENA(i) ((i) << 4) - -/* Register: CFPB_CLK_NS */ -#define CLK_DIV_MASK 0x00000003 -#define CLK_DIV_DIV_1 0x00000000 -#define CLK_DIV_DIV_2 0x00000001 -#define CLK_DIV_DIV_3 0x00000002 -#define CLK_DIV_DIV_4 0x00000003 -#define CLK_DIV(i) ((i) << 0) - -#define MN_MODE_DUAL_EDGE 0x2 -#define BIT_POS_31 31 -#define BIT_POS_16 16 -#define BIT_POS_6 6 -#define BIT_POS_0 0 -#define BIT_POS_15 15 - -#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) -#define BVAL(m, l, val) (((val) << l) & BM(m, l)) - -/* MD Registers */ -#define MD4(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) - -#define MD8(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) - -/* NS Registers */ -#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) \ - | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ - | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ - | BVAL(s_msb, s_lsb, s)) - -#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_DIV(d_msb , d_lsb, d) \ - BVAL(d_msb, d_lsb, (d-1)) - -#define NS_SRC_SEL(s_msb, s_lsb, s) \ - BVAL(s_msb, s_lsb, s) - -#define GMAC_AHB_RESET 0x903E24 - -#define SRC_SEL_PLL0 (0x2 << 0) -#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) -#define MNCNTR_ENABLE (0x1 << 8) -#define MNCNTR_RST_ACTIVE (0x1 << 7) -#define N_VAL 15 - -#define GMAC_CORE_RESET(n) \ - ((void *)(0x903CBC + ((n) * 0x20))) - -#define GMACSEC_CORE_RESET(n) \ - ((void *)(0x903E28 + ((n - 1) * 4))) - -#define GMAC_COREn_CLCK_SRC_CTL(N) \ - (0x00900000 + (0x3CA0 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_MD(N) \ - (0x00900000 + (0x3CA4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_MD(N) \ - (0x00900000 + (0x3CA8 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_NS(N) \ - (0x00900000 + (0x3CAC + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_NS(N) \ - (0x00900000 + (0x3CB0 + (32*(N-1)))) - -#define DISABLE_DUAL_MN8_SEL (0) -#define DISABLE_CLK_LOW_PWR (0 << 2) -#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) - -/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_M 0x32 -#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ -#define GMAC_CORE_CLCK_M_SHIFT 16 -#define GMAC_CORE_CLCK_D_SHIFT 0 -#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) -#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) - -/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ -#define GMAC_CORE_CLCK_N_SHIFT 16 -#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) -#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 -#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 -#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ -#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ -#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 -#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ -#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) -#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) - - -/* Uart specific clock settings */ - -void uart_pll_vote_clk_enable(unsigned int); -void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, - unsigned int d, unsigned int clk_dummy); -void nand_clock_config(void); -void usb_clock_config(void); - -#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h deleted file mode 100644 index 276022c..0000000 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - Source : APQ8064 LK Boot - - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ -#define __SOC_QUALCOMM_IPQ806X_GPIO_H_ - -#include <gpiolib.h> - -#define GPIO_FUNC_ENABLE 1 -#define GPIO_FUNC_DISABLE 0 -#define FUNC_SEL_1 1 -#define FUNC_SEL_3 3 -#define FUNC_SEL_GPIO 0 -#define GPIO_DRV_STR_10MA 0x4 -#define GPIO_DRV_STR_11MA 0x7 - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_DISABLE 0 -#define GPIO_ENABLE 1 - -/* GPIO MAX Valid # */ -#define GPIO_MAX_NUM 68 - -/* GPIO TLMM: Mask */ -#define GPIO_CFG_PULL_MASK 0x3 -#define GPIO_CFG_FUNC_MASK 0xF -#define GPIO_CFG_DRV_MASK 0x7 -#define GPIO_CFG_OE_MASK 0x1 - -/* GPIO TLMM: Shift */ -#define GPIO_CFG_PULL_SHIFT 0 -#define GPIO_CFG_FUNC_SHIFT 2 -#define GPIO_CFG_DRV_SHIFT 6 -#define GPIO_CFG_OE_SHIFT 9 - -/* GPIO IO: Mask */ -#define GPIO_IO_IN_MASK 0x1 -#define GPIO_IO_OUT_MASK 0x1 - -/* GPIO IO: Shift */ -#define GPIO_IO_IN_SHIFT 0 -#define GPIO_IO_OUT_SHIFT 1 - -void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, - unsigned int pull, unsigned int drvstr, - unsigned int enable); - -void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, - unsigned int *pull, unsigned int *drvstr, - unsigned int *enable); - -void gpio_io_config_set(gpio_t gpio, unsigned int out); - -/* Keep this to maintain backwards compatibility with the vendor API. */ -static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, - unsigned int dir, unsigned int pull, - unsigned int drvstr, unsigned int enable) -{ - gpio_tlmm_config_set(gpio, func, pull, drvstr, enable); -} -#endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/gsbi.h b/src/soc/qualcomm/ipq806x/include/gsbi.h deleted file mode 100644 index c12d6fd..0000000 --- a/src/soc/qualcomm/ipq806x/include/gsbi.h +++ /dev/null @@ -1,35 +0,0 @@ -/* -* Copyright (c) 2004-2011 Atheros Communications Inc. -* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - - -#ifndef __GSBI_H_ -#define __GSBI_H_ - -/* GSBI Registers */ -#define GSBI_CTRL_REG(base) ((base) + 0x0) - -#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 -#define GSBI_PROTOCOL_CODE_I2C 0x2 -#define GSBI_PROTOCOL_CODE_SPI 0x3 -#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 -#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 - -#define GSBI_HCLK_CTL_S 4 -#define GSBI_HCLK_CTL_CLK_ENA 0x1 - -#endif - diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h deleted file mode 100644 index c9c8fc4..0000000 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * Copyright (c) 2008, Google Inc. - * All rights reserved. - * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ -#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ - -#include <arch/io.h> -#include <cdp.h> - -/* Typecast to allow integers being passed as address - This needs to be included because vendor code is not compliant with our - macros for read/write. Hence, special macros for readl_i and writel_i are - included to do this in one place for all occurrences in vendor code - */ -#define readl_i(a) read32((const void *)(a)) -#define writel_i(v,a) write32(v,(void *)a) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) - -#define MSM_CLK_CTL_BASE 0x00900000 - -#define MSM_TMR_BASE 0x0200A000 -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) - -#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off))) -#define DGT_REG(off) (MSM_DGT_BASE + (off)) - -#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) -#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) -#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) -#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) - -#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) - -#define GPT_MATCH_VAL GPT_REG(0x0000) -#define GPT_COUNT_VAL GPT_REG(0x0004) -#define GPT_ENABLE GPT_REG(0x0008) -#define GPT_CLEAR GPT_REG(0x000C) - -#define GPT1_MATCH_VAL GPT_REG(0x00010) -#define GPT1_COUNT_VAL GPT_REG(0x00014) -#define GPT1_ENABLE GPT_REG(0x00018) -#define GPT1_CLEAR GPT_REG(0x0001C) - -#define DGT_MATCH_VAL DGT_REG(0x0000) -#define DGT_COUNT_VAL DGT_REG(0x0004) -#define DGT_ENABLE DGT_REG(0x0008) -#define DGT_CLEAR DGT_REG(0x000C) -#define DGT_CLK_CTL DGT_REG(0x0010) - -#define TLMM_BASE_ADDR ((char *)0x00800000) -#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) -#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) - -/* Yes, this is not a typo... host2 is actually mapped before host1. */ -#define USB_HOST2_XHCI_BASE 0x10000000 -#define USB_HOST2_DWC3_BASE 0x1000C100 -#define USB_HOST2_PHY_BASE 0x100F8800 -#define USB_HOST1_XHCI_BASE 0x11000000 -#define USB_HOST1_DWC3_BASE 0x1100C100 -#define USB_HOST1_PHY_BASE 0x110F8800 - -#define GSBI_1 1 -#define GSBI_2 2 -#define GSBI_4 4 -#define GSBI_2 2 -#define UART1_DM_BASE 0x12450000 -#define UART_GSBI1_BASE 0x12440000 -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 -#define UART4_DM_BASE 0x16340000 -#define UART_GSBI4_BASE 0x16300000 - -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 - -#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_ diff --git a/src/soc/qualcomm/ipq806x/include/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/ipq_timer.h deleted file mode 100644 index 4e1ef34..0000000 --- a/src/soc/qualcomm/ipq806x/include/ipq_timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#define TIMER_LOAD_VAL 0x21 - -#define GPT_ENABLE_CLR_ON_MATCH_EN 2 -#define GPT_ENABLE_EN 1 -#define DGT_ENABLE_CLR_ON_MATCH_EN 2 -#define DGT_ENABLE_EN 1 - -#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) - - diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h deleted file mode 100644 index 90ca704..0000000 --- a/src/soc/qualcomm/ipq806x/include/ipq_uart.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __UART_DM_H__ -#define __UART_DM_H__ - -#define PERIPH_BLK_BLSP 0 - -#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ - ((value << (32 - end_pos))\ - >> (32 - (end_pos - start_pos))) - -extern void __udelay(unsigned long usec); - - -enum MSM_BOOT_UART_DM_PARITY_MODE { - MSM_BOOT_UART_DM_NO_PARITY, - MSM_BOOT_UART_DM_ODD_PARITY, - MSM_BOOT_UART_DM_EVEN_PARITY, - MSM_BOOT_UART_DM_SPACE_PARITY -}; - -/* UART Stop Bit Length */ -enum MSM_BOOT_UART_DM_STOP_BIT_LEN { - MSM_BOOT_UART_DM_SBL_9_16, - MSM_BOOT_UART_DM_SBL_1, - MSM_BOOT_UART_DM_SBL_1_9_16, - MSM_BOOT_UART_DM_SBL_2 -}; - -/* UART Bits per Char */ -enum MSM_BOOT_UART_DM_BITS_PER_CHAR { - MSM_BOOT_UART_DM_5_BPS, - MSM_BOOT_UART_DM_6_BPS, - MSM_BOOT_UART_DM_7_BPS, - MSM_BOOT_UART_DM_8_BPS -}; - -/* 8-N-1 Configuration */ -#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ - (MSM_BOOT_UART_DM_SBL_1 << 2) | \ - (MSM_BOOT_UART_DM_8_BPS << 4)) - -/* UART_DM Registers */ - -/* UART Operational Mode Register */ -#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) -#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) -#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) -#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) - -/* UART Clock Selection Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) -#else -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) -#endif - -/* UART DM TX FIFO Registers - 4 */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) -#else -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) -#endif - -/* UART Command Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) -#else -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) -#endif -#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) -#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) -#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) -#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) - -/* UART Channel Command */ -#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) -#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) -#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ - | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) -#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) -#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) -#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) -#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) -#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) -#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) -#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) -#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) -#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) -#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) -#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) -#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) -#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) -#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) -#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) -#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) -#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) -#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) - -/*UART General Command */ -#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) - -#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) -#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) -#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) -#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) -#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) - -/* UART Interrupt Mask Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) -#else -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) -#endif - -#define MSM_BOOT_UART_DM_TXLEV (1 << 0) -#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) -#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) -#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) -#define MSM_BOOT_UART_DM_RXLEV (1 << 4) -#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) -#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) -#define MSM_BOOT_UART_DM_TX_READY (1 << 7) -#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) -#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) -#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) -#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) -#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) - -#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ - MSM_BOOT_UART_DM_TXLEV | \ - MSM_BOOT_UART_DM_RXSTALE) - -/* UART Interrupt Programming Register */ -#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ - -/* UART Transmit/Receive FIFO Watermark Register */ -#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) -/* Interrupt is generated when FIFO level is less than or equal to this value */ -#define MSM_BOOT_UART_DM_TFW_VALUE 0 - -#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) -/*Interrupt generated when no of words in RX FIFO is greater than this value */ -#define MSM_BOOT_UART_DM_RFW_VALUE 0 - -/* UART Hunt Character Register */ -#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) - -/* Used for RX transfer initialization */ -#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) - -/* Default DMRX value - any value bigger than FIFO size would be fine */ -#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 - -/* Register to enable IRDA function */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) -#else -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) -#endif - -/* UART Data Mover Enable Register */ -#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) - -/* Number of characters for Transmission */ -#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) - -/* UART RX FIFO Base Address */ -#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) - -/* UART Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) -#else -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) -#endif -#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) -#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) -#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) -#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) -#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) -#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) -#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) -#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) -#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) - -/* UART Receive FIFO Registers - 4 in numbers */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) -#else -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) -#endif - -/* UART Masked Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) -#else -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) -#endif - -/* UART Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) -#else -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) -#endif - -/* Number of characters received since the end of last RX transfer */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) -#else -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) -#endif - -/* UART TX FIFO Status Register */ -#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) -#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* UART RX FIFO Status Register */ -#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) -#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* Macros for Common Errors */ -#define MSM_BOOT_UART_DM_E_SUCCESS 0 -#define MSM_BOOT_UART_DM_E_FAILURE 1 -#define MSM_BOOT_UART_DM_E_TIMEOUT 2 -#define MSM_BOOT_UART_DM_E_INVAL 3 -#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 -#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 - -#endif /* __UART_DM_H__ */ - diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h new file mode 100644 index 0000000..c7de23f --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -0,0 +1,139 @@ +/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ + + +#ifndef _IPQ806X_CDP_H_ +#define _IPQ806X_CDP_H_ + +#include <types.h> + +unsigned smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + unsigned int gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI GSBI Bus number */ + +typedef enum { + GSBI_BUS_5 = 0, + GSBI_BUS_6, + GSBI_BUS_7, +} spi_gsbi_bus_num; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0 , + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_gsbi_bus_num bus_number; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned base; + int unit; + unsigned is_macsec; + unsigned mac_pwr0; + unsigned mac_pwr1; + unsigned mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +/* Board specific parameters */ +typedef struct { +#if 0 + unsigned int gmac_gpio_count; + gpio_func_data_t *gmac_gpio; + ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; + flash_desc flashdesc; + spinorflash_params_t flash_param; +#endif +} __attribute__ ((__packed__)) board_ipq806x_params_t; + +extern board_ipq806x_params_t *gboard_param; + +#if 0 +static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) +{ + /* + * 'cfg' is valid if and only if + * unit number is non-negative and less than IPQ_GMAC_NMACS. + * 'cfg' pointer lies within the array range of + * board_ipq806x_params_t->gmac_cfg[] + */ + return ((cfg >= &gboard_param->gmac_cfg[0]) && + (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && + (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); +} +#endif + +unsigned int get_board_index(unsigned machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); +#endif diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h new file mode 100644 index 0000000..837b831 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK Boot + * + * Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IPQ860X_CLOCK_H_ +#define __IPQ860X_CLOCK_H_ + +#include <soc/iomap.h> + +/* UART clock @ 7.3728 MHz */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC + +/* UART specific definitions */ + +#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) +#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) +#define Uart_mnd_en_mask BIT(8) * !!(625) +#define Uart_en_mask BIT(11) +#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) +#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) +#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) +#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) +#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) +#define BB_PLL_ENA_SC0_REG REG(0x34C0) +#define BB_PLL8_STATUS_REG REG(0x3158) +#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off))) +#define PLL8_STATUS_BIT 16 + +#define PLL_LOCK_DET_STATUS_REG REG(0x03420) +#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) +#define CFPB_CLK_NS_REG REG(0x0264C) +#define CFPB0_HCLK_CTL_REG REG(0x02650) +#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) +#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) +#define EBI2_CLK_CTL_REG REG(0x03B00) + +#define USB30_MASTER_CLK_CTL_REG REG(0x3b24) +#define USB30_MASTER_CLK_MD REG(0x3b28) +#define USB30_MASTER_CLK_NS REG(0x3b2c) +#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34) +#define USB30_MOC_UTMI_CLK_MD REG(0x3b40) +#define USB30_MOC_UTMI_CLK_NS REG(0x3b44) +#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48) +#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c) +#define USB30_RESET REG(0x3b50) + +#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) + +#define CLK_BRANCH_ENA_MASK 0x00000010 +#define CLK_BRANCH_ENA_ENABLE 0x00000010 +#define CLK_BRANCH_ENA_DISABLE 0x00000000 +#define CLK_BRANCH_ENA(i) ((i) << 4) + +/* Register: CFPB_CLK_NS */ +#define CLK_DIV_MASK 0x00000003 +#define CLK_DIV_DIV_1 0x00000000 +#define CLK_DIV_DIV_2 0x00000001 +#define CLK_DIV_DIV_3 0x00000002 +#define CLK_DIV_DIV_4 0x00000003 +#define CLK_DIV(i) ((i) << 0) + +#define MN_MODE_DUAL_EDGE 0x2 +#define BIT_POS_31 31 +#define BIT_POS_16 16 +#define BIT_POS_6 6 +#define BIT_POS_0 0 +#define BIT_POS_15 15 + +#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) +#define BVAL(m, l, val) (((val) << l) & BM(m, l)) + +/* MD Registers */ +#define MD4(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) + +#define MD8(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) + +/* NS Registers */ +#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) \ + | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ + | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ + | BVAL(s_msb, s_lsb, s)) + +#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_DIV(d_msb , d_lsb, d) \ + BVAL(d_msb, d_lsb, (d-1)) + +#define NS_SRC_SEL(s_msb, s_lsb, s) \ + BVAL(s_msb, s_lsb, s) + +#define GMAC_AHB_RESET 0x903E24 + +#define SRC_SEL_PLL0 (0x2 << 0) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define MNCNTR_ENABLE (0x1 << 8) +#define MNCNTR_RST_ACTIVE (0x1 << 7) +#define N_VAL 15 + +#define GMAC_CORE_RESET(n) \ + ((void *)(0x903CBC + ((n) * 0x20))) + +#define GMACSEC_CORE_RESET(n) \ + ((void *)(0x903E28 + ((n - 1) * 4))) + +#define GMAC_COREn_CLCK_SRC_CTL(N) \ + (0x00900000 + (0x3CA0 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_MD(N) \ + (0x00900000 + (0x3CA4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_MD(N) \ + (0x00900000 + (0x3CA8 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_NS(N) \ + (0x00900000 + (0x3CAC + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_NS(N) \ + (0x00900000 + (0x3CB0 + (32*(N-1)))) + +#define DISABLE_DUAL_MN8_SEL (0) +#define DISABLE_CLK_LOW_PWR (0 << 2) +#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) + +/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_M 0x32 +#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ +#define GMAC_CORE_CLCK_M_SHIFT 16 +#define GMAC_CORE_CLCK_D_SHIFT 0 +#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) +#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) + +/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ +#define GMAC_CORE_CLCK_N_SHIFT 16 +#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) +#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 +#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 +#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ +#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ +#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 +#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ +#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) +#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) + + +/* Uart specific clock settings */ + +void uart_pll_vote_clk_enable(unsigned int); +void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, + unsigned int d, unsigned int clk_dummy); +void nand_clock_config(void); +void usb_clock_config(void); + +#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/gpio.h b/src/soc/qualcomm/ipq806x/include/soc/gpio.h new file mode 100644 index 0000000..276022c --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/gpio.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + Source : APQ8064 LK Boot + + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ +#define __SOC_QUALCOMM_IPQ806X_GPIO_H_ + +#include <gpiolib.h> + +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 +#define FUNC_SEL_1 1 +#define FUNC_SEL_3 3 +#define FUNC_SEL_GPIO 0 +#define GPIO_DRV_STR_10MA 0x4 +#define GPIO_DRV_STR_11MA 0x7 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO MAX Valid # */ +#define GPIO_MAX_NUM 68 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_MASK 0x3 +#define GPIO_CFG_FUNC_MASK 0xF +#define GPIO_CFG_DRV_MASK 0x7 +#define GPIO_CFG_OE_MASK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHIFT 0 +#define GPIO_CFG_FUNC_SHIFT 2 +#define GPIO_CFG_DRV_SHIFT 6 +#define GPIO_CFG_OE_SHIFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_MASK 0x1 +#define GPIO_IO_OUT_MASK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHIFT 0 +#define GPIO_IO_OUT_SHIFT 1 + +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable); + +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable); + +void gpio_io_config_set(gpio_t gpio, unsigned int out); + +/* Keep this to maintain backwards compatibility with the vendor API. */ +static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, + unsigned int dir, unsigned int pull, + unsigned int drvstr, unsigned int enable) +{ + gpio_tlmm_config_set(gpio, func, pull, drvstr, enable); +} +#endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h new file mode 100644 index 0000000..c12d6fd --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2004-2011 Atheros Communications Inc. +* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + + +#ifndef __GSBI_H_ +#define __GSBI_H_ + +/* GSBI Registers */ +#define GSBI_CTRL_REG(base) ((base) + 0x0) + +#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 +#define GSBI_PROTOCOL_CODE_I2C 0x2 +#define GSBI_PROTOCOL_CODE_SPI 0x3 +#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 +#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 + +#define GSBI_HCLK_CTL_S 4 +#define GSBI_HCLK_CTL_CLK_ENA 0x1 + +#endif + diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h new file mode 100644 index 0000000..ad7056e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ +#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ + +#include <arch/io.h> +#include <soc/cdp.h> + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32(v,(void *)a) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define MSM_CLK_CTL_BASE 0x00900000 + +#define MSM_TMR_BASE 0x0200A000 +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) + +#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off))) +#define DGT_REG(off) (MSM_DGT_BASE + (off)) + +#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) +#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) +#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) +#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) + +#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) + +#define GPT_MATCH_VAL GPT_REG(0x0000) +#define GPT_COUNT_VAL GPT_REG(0x0004) +#define GPT_ENABLE GPT_REG(0x0008) +#define GPT_CLEAR GPT_REG(0x000C) + +#define GPT1_MATCH_VAL GPT_REG(0x00010) +#define GPT1_COUNT_VAL GPT_REG(0x00014) +#define GPT1_ENABLE GPT_REG(0x00018) +#define GPT1_CLEAR GPT_REG(0x0001C) + +#define DGT_MATCH_VAL DGT_REG(0x0000) +#define DGT_COUNT_VAL DGT_REG(0x0004) +#define DGT_ENABLE DGT_REG(0x0008) +#define DGT_CLEAR DGT_REG(0x000C) +#define DGT_CLK_CTL DGT_REG(0x0010) + +#define TLMM_BASE_ADDR ((char *)0x00800000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define GSBI_1 1 +#define GSBI_2 2 +#define GSBI_4 4 +#define GSBI_2 2 +#define UART1_DM_BASE 0x12450000 +#define UART_GSBI1_BASE 0x12440000 +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 +#define UART4_DM_BASE 0x16340000 +#define UART_GSBI4_BASE 0x16300000 + +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 + +#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h new file mode 100644 index 0000000..4e1ef34 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define TIMER_LOAD_VAL 0x21 + +#define GPT_ENABLE_CLR_ON_MATCH_EN 2 +#define GPT_ENABLE_EN 1 +#define DGT_ENABLE_CLR_ON_MATCH_EN 2 +#define DGT_ENABLE_EN 1 + +#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) + + diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h new file mode 100644 index 0000000..90ca704 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 0 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos))\ + >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ + | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#endif /* __UART_DM_H__ */ + diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld new file mode 100644 index 0000000..de1b129 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* TODO: This should be revised by someone who understands the SoC better. */ + +SECTIONS +{ + /* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */ + TTB(0x2A05C000, 48K) + + DRAM_START(0x40000000) + CBFS_CACHE(0x405C0000, 240K) + STACK(0x405FC000, 16K) + /* TODO: "256K bytes left for TZBSP"... what does that mean? */ + BOOTBLOCK(0x40600000, 32K) + PRERAM_CBMEM_CONSOLE(0x40618000, 8K) + ROMSTAGE(0x40620000, 128K) + RAMSTAGE(0x40640000, 128K) + DMA_COHERENT(0x5A000000, 2M) +} diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h new file mode 100644 index 0000000..f7dda07 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -0,0 +1,282 @@ +/* + * Register definitions for the IPQ GSBI Controller + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ + +#ifndef _IPQ806X_SPI_H_ +#define _IPQ806X_SPI_H_ + +#include <spi_flash.h> + +#define QUP5_BASE 0x1a280000 +#define QUP6_BASE 0x16580000 +#define QUP7_BASE 0x16680000 + +#define GSBI5_BASE 0x1a200000 +#define GSBI6_BASE 0x16500000 +#define GSBI7_BASE 0x16600000 + +#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) +#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) +#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) + +#define GSBI5_REG_BASE (GSBI5_BASE + 0x00000000) +#define GSBI6_REG_BASE (GSBI6_BASE + 0x00000000) +#define GSBI7_REG_BASE (GSBI7_BASE + 0x00000000) + +#define BOOT_SPI_PORT5_BASE QUP5_BASE +#define BOOT_SPI_PORT6_BASE QUP6_BASE +#define BOOT_SPI_PORT7_BASE QUP7_BASE + +#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) +#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) +#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) + +#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) +#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) +#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) + +#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) +#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) +#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) + +#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) +#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) +#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) + +#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) +#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) +#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) +#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) +#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) +#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) +#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) + +#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) +#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) +#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) + +#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) +#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) +#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) + +#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) +#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) +#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) + +#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) +#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) +#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) + +#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) +#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) +#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) + +#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) +#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) +#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) + +#define GSBI5_QUP_INPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI6_QUP_INPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI7_QUP_INPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) + +#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) + +#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) +#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) +#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) + +#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) +#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) +#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) + +#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) +#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) +#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) + +#define CLK_CTL_REG_BASE 0x00900000 +#define GSBIn_RESET_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) + +#define SFAB_AHB_S3_FCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x0000216c) +#define CFPB_CLK_NS_REG \ + (CLK_CTL_REG_BASE + 0x0000264c) +#define SFAB_CFPB_S_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026c0) +#define CFPB_SPLITTER_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026e0) +#define CFPB0_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002650) +#define CFPB2_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002658) +#define GSBIn_HCLK_CTL_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_NS_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_MD_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) +#define CLK_HALT_CFPB_STATEB_REG \ + (CLK_CTL_REG_BASE + 0x00002fd0) + +#define GSBI5_HCLK 23 +#define GSBI6_HCLK 19 +#define GSBI7_HCLK 15 +#define GSBI5_QUP_APPS_CLK 20 +#define GSBI6_QUP_APPS_CLK 16 +#define GSBI7_QUP_APPS_CLK 12 +#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) +#define GSBI_CLK_BRANCH_ENA (1 << 4) +#define GSBI_CLK_BRANCH_DIS (0 << 4) +#define QUP_CLK_BRANCH_ENA_MSK (1 << 9) +#define QUP_CLK_BRANCH_ENA (1 << 9) +#define QUP_CLK_BRANCH_DIS (0 << 9) +#define CLK_ROOT_ENA_MSK (1 << 11) +#define CLK_ROOT_ENA (1 << 11) +#define CLK_ROOT_DIS (0 << 11) + +#define QUP_STATE_VALID_BIT 2 +#define QUP_STATE_VALID 1 +#define QUP_STATE_MASK 0x3 +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define SPI_QUP_CONF_INPUT_MSK (1 << 7) +#define SPI_QUP_CONF_INPUT_ENA (0 << 7) +#define SPI_QUP_CONF_NO_INPUT (1 << 7) +#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) +#define SPI_QUP_CONF_NO_OUTPUT (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_STATE_RESET_STATE 0x0 +#define QUP_STATE_RUN_STATE 0x1 +#define QUP_STATE_PAUSE_STATE 0x3 +#define SPI_BIT_WORD_MSK 0x1F +#define SPI_8_BIT_WORD 0x07 +#define PROTOCOL_CODE_MSK (0x07 << 4) +#define PROTOCOL_CODE_SPI (0x03 << 4) +#define LOOP_BACK_MSK (1 << 8) +#define NO_LOOP_BACK (0 << 8) +#define SLAVE_OPERATION_MSK (1 << 5) +#define SLAVE_OPERATION (0 << 5) +#define CLK_ALWAYS_ON (0 << 9) +#define MX_CS_MODE (0 << 8) +#define NO_TRI_STATE (1 << 0) +#define OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define OUTPUT_BIT_SHIFT_EN (1 << 16) +#define INPUT_BLOCK_MODE_MSK (0x03 << 12) +#define INPUT_BLOCK_MODE (0x01 << 12) +#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) +#define OUTPUT_BLOCK_MODE (0x01 << 10) +#define GSBI1_RESET (1 << 0) +#define GSBI1_RESET_MSK 0x1 + +#define GSBI_M_VAL_SHFT 16 +#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) +#define GSBI_N_VAL_SHFT 16 +#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) +#define GSBI_D_VAL_SHFT 0 +#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) +#define MNCNTR_RST_MSK (1 << 7) +#define MNCNTR_RST_ENA (1 << 7) +#define MNCNTR_RST_DIS (0 << 7) +#define MNCNTR_MSK (1 << 8) +#define MNCNTR_EN (1 << 8) +#define MNCNTR_DIS (0 << 8) +#define MNCNTR_MODE_MSK (0x3 << 5) +#define MNCNTR_MODE_BYPASS (0 << 5) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define GSBI_PRE_DIV_SEL_SHFT 3 +#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) +#define GSBIn_PLL_SRC_MSK (0x03 << 0) +#define GSBIn_PLL_SRC_PXO (0 << 0) +#define GSBIn_PLL_SRC_PLL8 (0x3 << 0) + +#define SPI_INPUT_FIRST_MODE (1 << 9) +#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) +#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) +#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) +#define OUTPUT_SERVICE_FLAG (1 << 8) +#define INPUT_SERVICE_FLAG (1 << 9) +#define QUP_OUTPUT_FIFO_FULL (1 << 6) +#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 +#define GSBI5_SPI_CLK 21 +#define GSBI5_SPI_MISO 19 +#define GSBI5_SPI_MOSI 18 +#define GSBI5_SPI_CS_0 20 +#define GSBI5_SPI_CS_1 61 +#define GSBI5_SPI_CS_2 62 +#define GSBI5_SPI_CS_3 2 +#define GSBI6_SPI_CLK 30 +#define GSBI6_SPI_CS_0 29 +#define GSBI6_SPI_MISO 28 +#define GSBI6_SPI_MOSI 27 +#define GSBI7_SPI_CLK 9 +#define GSBI7_SPI_CS_0 8 +#define GSBI7_SPI_MISO 7 +#define GSBI7_SPI_MOSI 6 + +#define MSM_GSBI_MAX_FREQ 51200000 + +#define SPI_RESET_STATE 0 +#define SPI_RUN_STATE 1 +#define SPI_PAUSE_STATE 3 +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define GSBI_SPI_MODE_0 0 +#define GSBI_SPI_MODE_1 1 +#define GSBI_SPI_MODE_2 2 +#define GSBI_SPI_MODE_3 3 +#define GSBI5_SPI 0 +#define GSBI6_SPI 1 +#define GSBI7_SPI 2 + +struct gsbi_spi { + unsigned int spi_config; + unsigned int io_control; + unsigned int error_flags; + unsigned int error_flags_en; + unsigned int gsbi_ctrl; + unsigned int qup_config; + unsigned int qup_error_flags; + unsigned int qup_error_flags_en; + unsigned int qup_operational; + unsigned int qup_io_modes; + unsigned int qup_state; + unsigned int qup_input_fifo; + unsigned int qup_output_fifo; + unsigned int qup_mx_input_count; + unsigned int qup_mx_output_count; + unsigned int qup_sw_reset; + unsigned int qup_ns_reg; + unsigned int qup_md_reg; +}; + +struct ipq_spi_slave { + struct spi_slave slave; + const struct gsbi_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ipq_spi_slave, slave); +} + +#endif /* _IPQ_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/usb.h b/src/soc/qualcomm/ipq806x/include/soc/usb.h new file mode 100644 index 0000000..c3c4c48 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/usb.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _IPQ806X_USB_H_ +#define _IPQ806X_USB_H_ + +void setup_usb_host1(void); +void setup_usb_host2(void); + +#endif /* _IPQ806X_USB_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/spi.h b/src/soc/qualcomm/ipq806x/include/spi.h deleted file mode 100644 index f7dda07..0000000 --- a/src/soc/qualcomm/ipq806x/include/spi.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Register definitions for the IPQ GSBI Controller - * Copyright (c) 2012 The Linux Foundation. All rights reserved. - */ - -#ifndef _IPQ806X_SPI_H_ -#define _IPQ806X_SPI_H_ - -#include <spi_flash.h> - -#define QUP5_BASE 0x1a280000 -#define QUP6_BASE 0x16580000 -#define QUP7_BASE 0x16680000 - -#define GSBI5_BASE 0x1a200000 -#define GSBI6_BASE 0x16500000 -#define GSBI7_BASE 0x16600000 - -#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) -#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) -#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) - -#define GSBI5_REG_BASE (GSBI5_BASE + 0x00000000) -#define GSBI6_REG_BASE (GSBI6_BASE + 0x00000000) -#define GSBI7_REG_BASE (GSBI7_BASE + 0x00000000) - -#define BOOT_SPI_PORT5_BASE QUP5_BASE -#define BOOT_SPI_PORT6_BASE QUP6_BASE -#define BOOT_SPI_PORT7_BASE QUP7_BASE - -#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) -#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) -#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) - -#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) -#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) -#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) - -#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) -#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) -#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) - -#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) -#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) -#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) - -#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) -#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) -#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) - -#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) -#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) -#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) - -#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) -#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) -#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) - -#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) -#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) -#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) - -#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) -#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) -#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) - -#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) -#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) -#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) - -#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) -#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) -#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) - -#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) -#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) -#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) - -#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) -#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) -#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) - -#define GSBI5_QUP_INPUT_FIFOc_REG(c) \ - (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) -#define GSBI6_QUP_INPUT_FIFOc_REG(c) \ - (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) -#define GSBI7_QUP_INPUT_FIFOc_REG(c) \ - (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) - -#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) -#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) -#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) - -#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) -#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) -#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) - -#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) -#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) -#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) - -#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) -#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) -#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) - -#define CLK_CTL_REG_BASE 0x00900000 -#define GSBIn_RESET_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) - -#define SFAB_AHB_S3_FCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x0000216c) -#define CFPB_CLK_NS_REG \ - (CLK_CTL_REG_BASE + 0x0000264c) -#define SFAB_CFPB_S_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x000026c0) -#define CFPB_SPLITTER_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x000026e0) -#define CFPB0_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x00002650) -#define CFPB2_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x00002658) -#define GSBIn_HCLK_CTL_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) -#define GSBIn_QUP_APPS_NS_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) -#define GSBIn_QUP_APPS_MD_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) -#define CLK_HALT_CFPB_STATEB_REG \ - (CLK_CTL_REG_BASE + 0x00002fd0) - -#define GSBI5_HCLK 23 -#define GSBI6_HCLK 19 -#define GSBI7_HCLK 15 -#define GSBI5_QUP_APPS_CLK 20 -#define GSBI6_QUP_APPS_CLK 16 -#define GSBI7_QUP_APPS_CLK 12 -#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) -#define GSBI_CLK_BRANCH_ENA (1 << 4) -#define GSBI_CLK_BRANCH_DIS (0 << 4) -#define QUP_CLK_BRANCH_ENA_MSK (1 << 9) -#define QUP_CLK_BRANCH_ENA (1 << 9) -#define QUP_CLK_BRANCH_DIS (0 << 9) -#define CLK_ROOT_ENA_MSK (1 << 11) -#define CLK_ROOT_ENA (1 << 11) -#define CLK_ROOT_DIS (0 << 11) - -#define QUP_STATE_VALID_BIT 2 -#define QUP_STATE_VALID 1 -#define QUP_STATE_MASK 0x3 -#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) -#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) -#define SPI_QUP_CONF_INPUT_MSK (1 << 7) -#define SPI_QUP_CONF_INPUT_ENA (0 << 7) -#define SPI_QUP_CONF_NO_INPUT (1 << 7) -#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) -#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) -#define SPI_QUP_CONF_NO_OUTPUT (1 << 6) -#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) -#define QUP_STATE_RESET_STATE 0x0 -#define QUP_STATE_RUN_STATE 0x1 -#define QUP_STATE_PAUSE_STATE 0x3 -#define SPI_BIT_WORD_MSK 0x1F -#define SPI_8_BIT_WORD 0x07 -#define PROTOCOL_CODE_MSK (0x07 << 4) -#define PROTOCOL_CODE_SPI (0x03 << 4) -#define LOOP_BACK_MSK (1 << 8) -#define NO_LOOP_BACK (0 << 8) -#define SLAVE_OPERATION_MSK (1 << 5) -#define SLAVE_OPERATION (0 << 5) -#define CLK_ALWAYS_ON (0 << 9) -#define MX_CS_MODE (0 << 8) -#define NO_TRI_STATE (1 << 0) -#define OUTPUT_BIT_SHIFT_MSK (1 << 16) -#define OUTPUT_BIT_SHIFT_EN (1 << 16) -#define INPUT_BLOCK_MODE_MSK (0x03 << 12) -#define INPUT_BLOCK_MODE (0x01 << 12) -#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) -#define OUTPUT_BLOCK_MODE (0x01 << 10) -#define GSBI1_RESET (1 << 0) -#define GSBI1_RESET_MSK 0x1 - -#define GSBI_M_VAL_SHFT 16 -#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) -#define GSBI_N_VAL_SHFT 16 -#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) -#define GSBI_D_VAL_SHFT 0 -#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) -#define MNCNTR_RST_MSK (1 << 7) -#define MNCNTR_RST_ENA (1 << 7) -#define MNCNTR_RST_DIS (0 << 7) -#define MNCNTR_MSK (1 << 8) -#define MNCNTR_EN (1 << 8) -#define MNCNTR_DIS (0 << 8) -#define MNCNTR_MODE_MSK (0x3 << 5) -#define MNCNTR_MODE_BYPASS (0 << 5) -#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) -#define GSBI_PRE_DIV_SEL_SHFT 3 -#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) -#define GSBIn_PLL_SRC_MSK (0x03 << 0) -#define GSBIn_PLL_SRC_PXO (0 << 0) -#define GSBIn_PLL_SRC_PLL8 (0x3 << 0) - -#define SPI_INPUT_FIRST_MODE (1 << 9) -#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) -#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) -#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) -#define OUTPUT_SERVICE_FLAG (1 << 8) -#define INPUT_SERVICE_FLAG (1 << 9) -#define QUP_OUTPUT_FIFO_FULL (1 << 6) -#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) -#define SPI_INPUT_BLOCK_SIZE 4 -#define SPI_OUTPUT_BLOCK_SIZE 4 -#define GSBI5_SPI_CLK 21 -#define GSBI5_SPI_MISO 19 -#define GSBI5_SPI_MOSI 18 -#define GSBI5_SPI_CS_0 20 -#define GSBI5_SPI_CS_1 61 -#define GSBI5_SPI_CS_2 62 -#define GSBI5_SPI_CS_3 2 -#define GSBI6_SPI_CLK 30 -#define GSBI6_SPI_CS_0 29 -#define GSBI6_SPI_MISO 28 -#define GSBI6_SPI_MOSI 27 -#define GSBI7_SPI_CLK 9 -#define GSBI7_SPI_CS_0 8 -#define GSBI7_SPI_MISO 7 -#define GSBI7_SPI_MOSI 6 - -#define MSM_GSBI_MAX_FREQ 51200000 - -#define SPI_RESET_STATE 0 -#define SPI_RUN_STATE 1 -#define SPI_PAUSE_STATE 3 -#define SPI_CORE_RESET 0 -#define SPI_CORE_RUNNING 1 -#define GSBI_SPI_MODE_0 0 -#define GSBI_SPI_MODE_1 1 -#define GSBI_SPI_MODE_2 2 -#define GSBI_SPI_MODE_3 3 -#define GSBI5_SPI 0 -#define GSBI6_SPI 1 -#define GSBI7_SPI 2 - -struct gsbi_spi { - unsigned int spi_config; - unsigned int io_control; - unsigned int error_flags; - unsigned int error_flags_en; - unsigned int gsbi_ctrl; - unsigned int qup_config; - unsigned int qup_error_flags; - unsigned int qup_error_flags_en; - unsigned int qup_operational; - unsigned int qup_io_modes; - unsigned int qup_state; - unsigned int qup_input_fifo; - unsigned int qup_output_fifo; - unsigned int qup_mx_input_count; - unsigned int qup_mx_output_count; - unsigned int qup_sw_reset; - unsigned int qup_ns_reg; - unsigned int qup_md_reg; -}; - -struct ipq_spi_slave { - struct spi_slave slave; - const struct gsbi_spi *regs; - unsigned int mode; - unsigned int initialized; - unsigned long freq; - int allocated; -}; - -static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) -{ - return container_of(slave, struct ipq_spi_slave, slave); -} - -#endif /* _IPQ_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/usb.h b/src/soc/qualcomm/ipq806x/include/usb.h deleted file mode 100644 index c3c4c48..0000000 --- a/src/soc/qualcomm/ipq806x/include/usb.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _IPQ806X_USB_H_ -#define _IPQ806X_USB_H_ - -void setup_usb_host1(void); -void setup_usb_host2(void); - -#endif /* _IPQ806X_USB_H_ */ diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld deleted file mode 100644 index de1b129..0000000 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* TODO: This should be revised by someone who understands the SoC better. */ - -SECTIONS -{ - /* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */ - TTB(0x2A05C000, 48K) - - DRAM_START(0x40000000) - CBFS_CACHE(0x405C0000, 240K) - STACK(0x405FC000, 16K) - /* TODO: "256K bytes left for TZBSP"... what does that mean? */ - BOOTBLOCK(0x40600000, 32K) - PRERAM_CBMEM_CONSOLE(0x40618000, 8K) - ROMSTAGE(0x40620000, 128K) - RAMSTAGE(0x40640000, 128K) - DMA_COHERENT(0x5A000000, 2M) -} diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 54d54b2..4cf64eb 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -4,11 +4,11 @@ #include <arch/io.h> #include <delay.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/spi.h> #include <stdlib.h> #include <string.h> -#include <spi.h> -#include <gpio.h> -#include <iomap.h> #define SUCCESS 0 diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 55386e9..f52f2ef 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -29,8 +29,8 @@ */ #include <delay.h> -#include <iomap.h> -#include <ipq_timer.h> +#include <soc/iomap.h> +#include <soc/ipq_timer.h> #include <timer.h> /* diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 4989247..3e8e187 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -34,12 +34,12 @@ #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <delay.h> -#include <clock.h> -#include <gpio.h> -#include <gsbi.h> #include <console/uart.h> -#include <ipq_uart.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/gsbi.h> +#include <soc/ipq_uart.h> #include <stdint.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index a9214be..fb89373 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -17,13 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <delay.h> #include <arch/io.h> #include <console/console.h> - -#include "clock.h" -#include "iomap.h" -#include "usb.h" +#include <delay.h> +#include <soc/clock.h> +#include <soc/iomap.h> +#include <soc/usb.h> #define CRPORT_TX_OVRD_DRV_LO 0x1002 #define CRPORT_RX_OVRD_IN_HI 0x1006

1 0

Patch set updated for coreboot: 9f489dc rk3288: support tsadc
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9348 -gerrit commit 9f489dce6856b729d9b2b46ac6b4ee607f141cb6 Author: huang lin <hl(a)rock-chips.com> Date: Tue Oct 14 10:04:16 2014 -0700 rk3288: support tsadc check the cpu and gpu temperature in romstage, if over 120 degrees celsius,shut down the device. BUG=None Test=Boot on veyron_pinky rev2, write value 3421(125 celsius) to grf_tsadc_testbitl register, the device will be shut down Change-Id: I275d643ce8560444a9b42ee566d5fd63ebcda35e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e0c597489dc0637ffa66ee9db0c4f60757f8889f Original-Change-Id: If406d6a4f6201150f52ea7fc64cd50b45778d7aa Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223259 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_pinky/romstage.c | 2 + src/soc/rockchip/rk3288/Makefile.inc | 1 + src/soc/rockchip/rk3288/addressmap.h | 1 + src/soc/rockchip/rk3288/clock.c | 11 +++ src/soc/rockchip/rk3288/clock.h | 2 + src/soc/rockchip/rk3288/pmu.h | 6 +- src/soc/rockchip/rk3288/tsadc.c | 119 +++++++++++++++++++++++++++ src/soc/rockchip/rk3288/tsadc.h | 25 ++++++ 8 files changed, 165 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 76a57e2..ab7903c 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -35,6 +35,7 @@ #include <soc/rockchip/rk3288/clock.h> #include <soc/rockchip/rk3288/pwm.h> #include <soc/rockchip/rk3288/grf.h> +#include <soc/rockchip/rk3288/tsadc.h> #include <symbols.h> #include "timer.h" @@ -86,6 +87,7 @@ void main(void) console_init(); configure_l2ctlr(); + tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index d41919b..076f0dc 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -53,6 +53,7 @@ romstage-y += spi.c romstage-y += media.c romstage-y += sdram.c romstage-y += pwm.c +romstage-y += tsadc.c ramstage-y += soc.c ramstage-y += cbmem.c diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h index 865e3c2..aea3bc0 100644 --- a/src/soc/rockchip/rk3288/addressmap.h +++ b/src/soc/rockchip/rk3288/addressmap.h @@ -36,6 +36,7 @@ #define UART0_BASE 0xFF180000 #define UART1_BASE 0xFF190000 #define DMAC_PERI_BASE 0xFF250000 +#define TSADC_BASE 0xFF280000 #define NANDC0_BASE 0xFF400000 #define NANDC1_BASE 0xFF410000 diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index bdfe079..5ad431c 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -480,3 +480,14 @@ void rkclk_configure_i2s(unsigned int hz) assert(hz == GPLL_HZ / n * d); writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); } + +void rkclk_configure_tsadc(unsigned int hz) +{ + u32 div; + u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/ + + div = src_clk / hz; + assert((div - 1 < 64) && (div * hz == 32 * KHz)); + writel(RK_CLRSETBITS(0x3f << 0, (div - 1) << 0), + &cru_ptr->cru_clksel_con[2]); +} diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index e767459..e2e8f3f 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -43,4 +43,6 @@ void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_i2s(unsigned int hz); void rkclk_configure_cpu(void); +void rkclk_configure_tsadc(unsigned int hz); + #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/pmu.h b/src/soc/rockchip/rk3288/pmu.h index 44e5989..23ca8b1 100644 --- a/src/soc/rockchip/rk3288/pmu.h +++ b/src/soc/rockchip/rk3288/pmu.h @@ -54,6 +54,7 @@ struct rk3288_pmu_regs { union { u32 gpio0b_iomux; u32 iomux_i2c0sda; + u32 iomux_tsadc_int; }; union { u32 gpio0c_iomux; @@ -69,7 +70,8 @@ check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0); static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE; -#define IOMUX_I2C0SDA 1 << 14 -#define IOMUX_I2C0SCL 1 << 0 +#define IOMUX_I2C0SDA (1 << 14) +#define IOMUX_I2C0SCL (1 << 0) +#define IOMUX_TSADC_INT (1 << 4) #endif diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c new file mode 100644 index 0000000..73980a0 --- /dev/null +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +#include <delay.h> +#include "tsadc.h" +#include "clock.h" +#include "pmu.h" +#include "grf.h" + +struct rk3288_tsadc_regs { + u32 user_con; + u32 auto_con; + u32 int_en; + u32 int_pd; + u32 reserved0[(0x20 - 0x10) / 4]; + u32 data0; + u32 data1; + u32 data2; + u32 data3; + u32 comp0_int; + u32 comp1_int; + u32 comp2_int; + u32 comp3_int; + u32 comp0_shut; + u32 comp1_shut; + u32 comp2_shut; + u32 comp3_shut; + u32 reserved1[(0x60 - 0x50) / 4]; + u32 hight_int_debounce; + u32 hight_tshut_debounce; + u32 auto_period; + u32 auto_period_ht; +}; +check_member(rk3288_tsadc_regs, auto_period_ht, 0x6c); + +/* auto_con */ +#define LAST_TSHUT (1 << 24) +#define TSHUT_POL_HIGH (1 << 8) +#define SRC3_EN (1 << 7) +#define SRC2_EN (1 << 6) +#define SRC1_EN (1 << 5) +#define SRC0_EN (1 << 4) +#define AUTO_EN (1 << 0) + +/* int_en */ +#define TSHUT_CRU_EN_SRC3 (1 << 11) +#define TSHUT_CRU_EN_SRC2 (1 << 10) +#define TSHUT_CRU_EN_SRC1 (1 << 9) +#define TSHUT_CRU_EN_SRC0 (1 << 8) +#define TSHUT_GPIO_EN_SRC3 (1 << 7) +#define TSHUT_GPIO_EN_SRC2 (1 << 6) +#define TSHUT_GPIO_EN_SRC1 (1 << 5) +#define TSHUT_GPIO_EN_SRC0 (1 << 4) + +#define AUTO_PERIOD 10 +#define AUTO_DEBOUNCE 4 +#define AUTO_PERIOD_HT 10 +#define AUTO_DEBOUNCE_HT 4 +#define TSADC_CLOCK_HZ (8 * KHz) + +/* AD value, correspond to 120 degrees Celsius */ +#define TSADC_SHUT_VALUE 3437 + +struct rk3288_tsadc_regs *rk3288_tsadc = (void *)TSADC_BASE; + +void tsadc_init(void) +{ + rkclk_configure_tsadc(TSADC_CLOCK_HZ); + + if (readl(&rk3288_tsadc->auto_con) & LAST_TSHUT) { + printk(BIOS_WARNING, "last shutdown/rebot was caused " + "by over-temperature hardware trigger!\n"); + setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); + } + + setbits_le32(&rk3288_tsadc->int_en, + TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | + TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); + + writel(AUTO_PERIOD, &rk3288_tsadc->auto_period); + writel(AUTO_DEBOUNCE, &rk3288_tsadc->hight_int_debounce); + writel(AUTO_PERIOD_HT, &rk3288_tsadc->auto_period_ht); + writel(AUTO_DEBOUNCE_HT, &rk3288_tsadc->hight_tshut_debounce); + + writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp1_shut); + writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp2_shut); + + /* polarity set to high,channel1 for cpu,channel2 for gpu */ + setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | + SRC1_EN | AUTO_EN); + + /* + tsadc iomux must be set after the tshut polarity setting, + since the tshut polarity defalut low active, + so if you enable tsadc iomux,it will output high + */ + setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); +} diff --git a/src/soc/rockchip/rk3288/tsadc.h b/src/soc/rockchip/rk3288/tsadc.h new file mode 100644 index 0000000..7412110 --- /dev/null +++ b/src/soc/rockchip/rk3288/tsadc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ +#define __SOC_ROCKCHIP_RK3288_TSADC_H__ + +void tsadc_init(void); + +#endif

1 0

Patch set updated for coreboot: f6a6345 rk3288: Change all SoC headers to <soc/headername.h> system
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9349 -gerrit commit f6a63459a4b36ab223a8e80aeb08352382161671 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 20 13:14:55 2014 -0700 rk3288: Change all SoC headers to <soc/headername.h> system This patch is the start of a series to change all non-x86 SoC-specific headers to be included as <soc/header.h> instead of the old <soc/vendor/chip/header.h> or "header.h". It will add an include/soc/ directory under every src/soc/vendor/chip/ and append the .../include/ part of that to the global include path. This matches the usage of <arch/header.h> for architecture-specific headers and had already been done for some headers on Tegra. It has the advantage that a source file which does not know the specific SoC used (e.g. Tegra files common for multiple chips, or a global include file) can still include SoC-specific headers and access macros/types defined there. It also makes the includes for mainboard files more readable, and reduces the chance to pull in a wrong header when copying mainboard sources to use a different-related SoC (e.g. using a Tegra124 mainboard as template for a Tegra132 one). For easier maintainability, every SoC family is modified individually. This patch starts out by changing Rk3288. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Whole series: compared binary images for Daisy, Nyan_Blaze, Rush_Ryu, Storm, Urara and Veyron_Pinky. Confirmed that they are byte-for-byte identical except for timestamps, hashes, and __LINE__ macro replacements. Compile-tested individual patches. Change-Id: I4d74a0c56be278e591a9cf43f93e9900e41f4319 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4ad8b6d2e0280428aa9742f0f7b723c00857334a Original-Change-Id: I415b8dbe735e572d4ae2cb1df62d66bcce386fff Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222025 --- src/mainboard/google/veyron_pinky/board.h | 2 +- src/mainboard/google/veyron_pinky/boardid.c | 7 +- src/mainboard/google/veyron_pinky/bootblock.c | 12 +- src/mainboard/google/veyron_pinky/chromeos.c | 2 +- src/mainboard/google/veyron_pinky/mainboard.c | 24 +-- src/mainboard/google/veyron_pinky/memlayout.ld | 2 +- src/mainboard/google/veyron_pinky/reset.c | 2 +- src/mainboard/google/veyron_pinky/romstage.c | 25 +-- src/mainboard/google/veyron_pinky/sdram_configs.c | 6 +- src/soc/rockchip/rk3288/Makefile.inc | 2 + src/soc/rockchip/rk3288/addressmap.h | 103 ---------- src/soc/rockchip/rk3288/bootblock.c | 8 +- src/soc/rockchip/rk3288/cbmem.c | 5 +- src/soc/rockchip/rk3288/clock.c | 16 +- src/soc/rockchip/rk3288/clock.h | 48 ----- src/soc/rockchip/rk3288/gpio.c | 9 +- src/soc/rockchip/rk3288/gpio.h | 77 -------- src/soc/rockchip/rk3288/grf.h | 220 ---------------------- src/soc/rockchip/rk3288/i2c.c | 20 +- src/soc/rockchip/rk3288/i2c.h | 26 --- src/soc/rockchip/rk3288/include/soc/addressmap.h | 103 ++++++++++ src/soc/rockchip/rk3288/include/soc/clock.h | 48 +++++ src/soc/rockchip/rk3288/include/soc/gpio.h | 76 ++++++++ src/soc/rockchip/rk3288/include/soc/grf.h | 220 ++++++++++++++++++++++ src/soc/rockchip/rk3288/include/soc/i2c.h | 26 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 49 +++++ src/soc/rockchip/rk3288/include/soc/pmu.h | 78 ++++++++ src/soc/rockchip/rk3288/include/soc/pwm.h | 26 +++ src/soc/rockchip/rk3288/include/soc/rk808.h | 27 +++ src/soc/rockchip/rk3288/include/soc/sdram.h | 102 ++++++++++ src/soc/rockchip/rk3288/include/soc/soc.h | 38 ++++ src/soc/rockchip/rk3288/include/soc/spi.h | 204 ++++++++++++++++++++ src/soc/rockchip/rk3288/include/soc/timer.h | 45 +++++ src/soc/rockchip/rk3288/include/soc/tsadc.h | 25 +++ src/soc/rockchip/rk3288/media.c | 3 +- src/soc/rockchip/rk3288/memlayout.ld | 49 ----- src/soc/rockchip/rk3288/monotonic_timer.c | 6 +- src/soc/rockchip/rk3288/pmu.h | 77 -------- src/soc/rockchip/rk3288/pwm.c | 17 +- src/soc/rockchip/rk3288/pwm.h | 26 --- src/soc/rockchip/rk3288/rk808.c | 4 +- src/soc/rockchip/rk3288/rk808.h | 27 --- src/soc/rockchip/rk3288/sdram.c | 16 +- src/soc/rockchip/rk3288/sdram.h | 104 ---------- src/soc/rockchip/rk3288/soc.c | 17 +- src/soc/rockchip/rk3288/soc.h | 38 ---- src/soc/rockchip/rk3288/spi.c | 14 +- src/soc/rockchip/rk3288/spi.h | 204 -------------------- src/soc/rockchip/rk3288/timer.c | 5 +- src/soc/rockchip/rk3288/timer.h | 45 ----- src/soc/rockchip/rk3288/tsadc.c | 12 +- src/soc/rockchip/rk3288/tsadc.h | 25 --- src/soc/rockchip/rk3288/uart.c | 4 +- 53 files changed, 1189 insertions(+), 1187 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h index 2ffa9cf..8d452c8 100644 --- a/src/mainboard/google/veyron_pinky/board.h +++ b/src/mainboard/google/veyron_pinky/board.h @@ -21,7 +21,7 @@ #define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H #include <boardid.h> -#include <soc/rockchip/rk3288/gpio.h> +#include <soc/gpio.h> #define PMIC_BUS 0 diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c index ca446a1..01e92a3 100644 --- a/src/mainboard/google/veyron_pinky/boardid.c +++ b/src/mainboard/google/veyron_pinky/boardid.c @@ -17,11 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> -#include <console/console.h> -#include <soc/rockchip/rk3288/gpio.h> - #include <boardid.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <stdlib.h> uint8_t board_id(void) { diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index a66d748..b34199d 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -20,12 +20,12 @@ #include <arch/io.h> #include <bootblock_common.h> -#include <soc/rockchip/rk3288/grf.h> -#include <soc/rockchip/rk3288/spi.h> -#include <soc/rockchip/rk3288/rk808.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/pmu.h> -#include <soc/rockchip/rk3288/i2c.h> +#include <soc/clock.h> +#include <soc/i2c.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/rk808.h> +#include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h> #include "board.h" diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 827b004..30cd277 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -21,9 +21,9 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> +#include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/gpio.h> #include "board.h" diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 19d6675..a8cc3c3 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -17,22 +17,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <device/device.h> #include <arch/cache.h> +#include <arch/io.h> +#include <console/console.h> #include <delay.h> +#include <device/device.h> #include <edid.h> -#include <symbols.h> -#include <vbe.h> #include <boot/coreboot_tables.h> #include <device/i2c.h> -#include <soc/rockchip/rk3288/gpio.h> -#include <soc/rockchip/rk3288/soc.h> -#include <soc/rockchip/rk3288/pmu.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/rk808.h> -#include <soc/rockchip/rk3288/spi.h> -#include <soc/rockchip/rk3288/i2c.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <soc/clock.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <soc/i2c.h> +#include <symbols.h> +#include <vbe.h> #include "board.h" diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld index a8b7465..ead7f47 100644 --- a/src/mainboard/google/veyron_pinky/memlayout.ld +++ b/src/mainboard/google/veyron_pinky/memlayout.ld @@ -1 +1 @@ -#include <soc/rockchip/rk3288/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c index 45c28b2..a2777f8 100644 --- a/src/mainboard/google/veyron_pinky/reset.c +++ b/src/mainboard/google/veyron_pinky/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/rockchip/rk3288/gpio.h> +#include <soc/gpio.h> #include <reset.h> #include "board.h" diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index ab7903c..38166ed 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -17,26 +17,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <arch/cache.h> +#include <arch/exception.h> #include <arch/stages.h> #include <armv7.h> +#include <assert.h> #include <cbfs.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <delay.h> #include <program_loading.h> -#include <timestamp.h> -#include <arch/cache.h> -#include <arch/exception.h> +#include <soc/sdram.h> +#include <soc/clock.h> +#include <soc/pwm.h> +#include <soc/grf.h> +#include <soc/tsadc.h> #include <stdlib.h> -#include <assert.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/rockchip/rk3288/sdram.h> -#include <soc/rockchip/rk3288/clock.h> -#include <soc/rockchip/rk3288/pwm.h> -#include <soc/rockchip/rk3288/grf.h> -#include <soc/rockchip/rk3288/tsadc.h> #include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + #include "timer.h" static void regulate_vdd_log(unsigned int mv) diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index cc29de0..1a331ce 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> +#include <console/console.h> +#include <soc/sdram.h> +#include <soc/gpio.h> #include <string.h> #include <types.h> -#include <console/console.h> -#include <soc/rockchip/rk3288/sdram.h> -#include <soc/rockchip/rk3288/gpio.h> static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 076f0dc..9885aaf 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -68,6 +68,8 @@ ramstage-y += rk808.c ramstage-y += pwm.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/ + $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h deleted file mode 100644 index aea3bc0..0000000 --- a/src/soc/rockchip/rk3288/addressmap.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ -#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ - -#define SDMMC1_BASE 0xFF0C0000 -#define SDMMC0_BASE 0xFF0D0000 -#define EMMC_BASE 0xFF0F0000 -#define SARADC_BASE 0xFF100000 - -#define SPI0_BASE 0xFF110000 -#define SPI1_BASE 0xFF120000 -#define SPI2_BASE 0xFF130000 - -#define I2C1_BASE 0xFF140000 -#define I2C3_BASE 0xFF150000 -#define I2C4_BASE 0xFF160000 -#define I2C5_BASE 0xFF170000 -#define UART0_BASE 0xFF180000 -#define UART1_BASE 0xFF190000 -#define DMAC_PERI_BASE 0xFF250000 -#define TSADC_BASE 0xFF280000 - -#define NANDC0_BASE 0xFF400000 -#define NANDC1_BASE 0xFF410000 - -#define USB_HOST0_EHCI_BASE 0xFF500000 -#define USB_HOST0_OHCI_BASE 0xFF520000 -#define USB_HOST1_BASE 0xFF540000 -#define USB_OTG_BASE 0xFF580000 - -#define DMAC_BUS_BASE 0xFF600000 - -#define DDR_PCTL0_BASE 0xFF610000 -#define DDR_PCTL1_BASE 0xFF630000 -#define DDR_PUBL0_BASE 0xFF620000 -#define DDR_PUBL1_BASE 0xFF640000 - -#define I2C0_BASE 0xFF650000 -#define I2C2_BASE 0xFF660000 -#define DW_PWM0123_BASE 0xFF670000 -#define RK_PWM0123_BASE 0xFF680000 -#define UART2_BASE 0xFF690000 -#define TIMER0_BASE 0xFF6B0000 - -#define SRAM_BASE 0xFF700000 -#define PMU_BASE 0xFF730000 -#define GRF_SECURE_BASE 0xFF740000 -#define GPIO0_BASE 0xFF750000 -#define CRU_BASE 0xFF760000 -#define GRF_BASE 0xFF770000 -#define GPIO1_BASE 0xFF780000 -#define GPIO2_BASE 0xFF790000 -#define GPIO3_BASE 0xFF7A0000 -#define GPIO4_BASE 0xFF7B0000 -#define GPIO5_BASE 0xFF7C0000 -#define GPIO6_BASE 0xFF7D0000 -#define GPIO7_BASE 0xFF7E0000 -#define GPIO8_BASE 0xFF7F0000 - -#define TIMER6_BASE 0xFF810000 -#define TIMER7_BASE 0xFF810020 - -#define VOP_BIG_BASE 0xFF930000 -#define HDMI_TX_BASE 0xFF980000 -#define DMACS_BUS_BASE 0xFFB20000 - -#define SERVICE_CORE_BASE 0xFFA80000 -#define SERVICE_DMA_BASE 0xFFA90000 -#define SERVICE_GPU_BASE 0xFFAA0000 -#define SERVICE_PERI_BASE 0xFFAB0000 -#define SERVICE_BUS_BASE 0xFFAC0000 -#define SERVICE_VIO_BASE 0xFFAD0000 -#define SERVICE_VPU_BASE 0xFFAE0000 -#define SERVICE_HEVC_BASE 0xFFAF0000 - -#define EFUSE_BASE 0xFFB40000 - -#define CORE_GICD_BASE 0xFFC01000 -#define CORE_GICC_BASE 0xFFC02000 -#define CPU_AXI_BUS_BASE 0xFFE00000 - -#define BOOT_ROM_BASE 0xFFFF0000 -#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) - -#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index b2f5bd9..26a6569 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -21,11 +21,11 @@ #include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> -#include <soc/rockchip/rk3288/grf.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/timer.h> #include <symbols.h> -#include "addressmap.h" -#include "timer.h" -#include "clock.h" static void bootblock_cpu_init(void) { diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c index dc1e0aa..1c3a902 100644 --- a/src/soc/rockchip/rk3288/cbmem.c +++ b/src/soc/rockchip/rk3288/cbmem.c @@ -17,9 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stddef.h> #include <cbmem.h> -#include "soc.h" +#include <soc/soc.h> +#include <stddef.h> + void *cbmem_top(void) { return (void *)(get_fb_base_kb()*KiB); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 5ad431c..d95257f 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <assert.h> -#include <stdlib.h> #include <arch/io.h> -#include <stdint.h> -#include <string.h> +#include <assert.h> #include <console/console.h> #include <delay.h> -#include "clock.h" -#include "grf.h" -#include "addressmap.h" -#include "soc.h" +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> struct pll_div { u32 nr; diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h deleted file mode 100644 index e2e8f3f..0000000 --- a/src/soc/rockchip/rk3288/clock.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ -#define __SOC_ROCKCHIP_RK3288_CLOCK_H__ - -#include "addressmap.h" - -#define OSC_HZ (24*MHz) - -#define APLL_HZ (1800*MHz) -#define GPLL_HZ (594*MHz) -#define CPLL_HZ (384*MHz) - -#define PD_BUS_ACLK_HZ (148500*KHz) -#define PD_BUS_HCLK_HZ (148500*KHz) -#define PD_BUS_PCLK_HZ (74250*KHz) - -#define PERI_ACLK_HZ (148500*KHz) -#define PERI_HCLK_HZ (148500*KHz) -#define PERI_PCLK_HZ (74250*KHz) - -void rkclk_init(void); -void rkclk_configure_spi(unsigned int bus, unsigned int hz); -void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); -void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); -void rkclk_configure_ddr(unsigned int hz); -void rkclk_configure_i2s(unsigned int hz); -void rkclk_configure_cpu(void); -void rkclk_configure_tsadc(unsigned int hz); - -#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 2d1ae15..c3784ec 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -17,12 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> +#include <console/console.h> +#include <soc/soc.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/pmu.h> #include <stdlib.h> -#include "soc.h" -#include "gpio.h" -#include "pmu.h" struct rk3288_gpio_regs *gpio_port[] = { (struct rk3288_gpio_regs *)0xff750000, diff --git a/src/soc/rockchip/rk3288/gpio.h b/src/soc/rockchip/rk3288/gpio.h deleted file mode 100644 index 7049ddf..0000000 --- a/src/soc/rockchip/rk3288/gpio.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__ -#define __SOC_ROCKCHIP_RK3288_GPIO_H__ - -#include "addressmap.h" -#include "grf.h" - -#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) - -struct rk3288_gpio_regs { - u32 swporta_dr; - u32 swporta_ddr; - u32 reserved0[(0x30 - 0x08) / 4]; - u32 inten; - u32 intmask; - u32 inttype_level; - u32 int_polarity; - u32 int_status; - u32 int_rawstatus; - u32 debounce; - u32 porta_eoi; - u32 ext_porta; - u32 reserved1[(0x60 - 0x54) / 4]; - u32 ls_sync; -}; -check_member(rk3288_gpio_regs, ls_sync, 0x60); - -typedef union { - u32 raw; - struct { - u16 port; - union { - struct { - u16 num:5; - u16 :11; - }; - struct { - u16 idx:3; - u16 bank:2; - u16 :11; - }; - }; - }; -} gpio_t; - -enum { - GPIO_A = 0, - GPIO_B, - GPIO_C, - GPIO_D, -}; - -void gpio_input(gpio_t gpio); -void gpio_input_pulldown(gpio_t gpio); -void gpio_input_pullup(gpio_t gpio); -void gpio_output(gpio_t gpio, int value); -int gpio_get_in_value(gpio_t gpio); - -#endif /* _ASM_ROCKCHIP_GPIO_H_ */ diff --git a/src/soc/rockchip/rk3288/grf.h b/src/soc/rockchip/rk3288/grf.h deleted file mode 100644 index e84359b..0000000 --- a/src/soc/rockchip/rk3288/grf.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ -#define __SOC_ROCKCHIP_RK3288_GRF_H__ - -#include <types.h> -#include "addressmap.h" -#include "soc.h" - -struct rk3288_grf_gpio_lh { - u32 l; - u32 h; -}; -check_member(rk3288_grf_gpio_lh, h, 0x4); - -struct rk3288_grf_regs { - u32 reserved[3]; - union { - u32 gpio1d_iomux; - u32 iomux_lcdc; - }; - u32 gpio2a_iomux; - u32 gpio2b_iomux; - union { - u32 gpio2c_iomux; - u32 iomux_i2c3; - }; - u32 reserved2; - union { - u32 gpio3a_iomux; - u32 iomux_emmcdata; - }; - union { - u32 gpio3b_iomux; - u32 iomux_emmcpwren; - }; - union { - u32 gpio3c_iomux; - u32 iomux_emmccmd; - }; - u32 gpio3dl_iomux; - u32 gpio3dh_iomux; - u32 gpio4al_iomux; - u32 gpio4ah_iomux; - u32 gpio4bl_iomux; - u32 reserved3; - u32 gpio4c_iomux; - u32 gpio4d_iomux; - u32 reserved4; - union { - u32 gpio5b_iomux; - u32 iomux_spi0; - }; - u32 gpio5c_iomux; - u32 reserved5; - union { - u32 gpio6a_iomux; - u32 iomux_i2s; - }; - union { - u32 gpio6b_iomux; - u32 iomux_i2c2; - u32 iomux_i2sclk; - }; - union { - u32 gpio6c_iomux; - u32 iomux_sdmmc0; - }; - u32 reserved6; - union { - u32 gpio7a_iomux; - u32 iomux_pwm0; - u32 iomux_pwm1; - }; - u32 gpio7b_iomux; - union { - u32 gpio7cl_iomux; - u32 iomux_i2c5sda; - u32 iomux_i2c4; - }; - union { - u32 gpio7ch_iomux; - u32 iomux_uart2; - u32 iomux_i2c5scl; - }; - u32 reserved7; - union { - u32 gpio8a_iomux; - u32 iomux_spi2csclk; - u32 iomux_i2c1; - }; - union { - u32 gpio8b_iomux; - u32 iomux_spi2txrx; - }; - u32 reserved8[30]; - struct rk3288_grf_gpio_lh gpio_sr[8]; - u32 gpio1_p[8][4]; - u32 gpio1_e[8][4]; - u32 gpio_smt; - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_status[22]; - u32 reserved9[2]; - u32 peridmac_con[4]; - u32 ddrc0_con0; - u32 ddrc1_con0; - u32 cpu_con[5]; - u32 reserved10[3]; - u32 cpu_status0; - u32 reserved11; - u32 uoc0_con[5]; - u32 uoc1_con[5]; - u32 uoc2_con[4]; - u32 uoc3_con[2]; - u32 uoc4_con[2]; - u32 pvtm_con[3]; - u32 pvtm_status[3]; - u32 io_vsel; - u32 saradc_testbit; - u32 tsadc_testbit_l; - u32 tsadc_testbit_h; - u32 os_reg[4]; - u32 reserved12; - u32 soc_con15; - u32 soc_con16; -}; -check_member(rk3288_grf_regs, soc_con16, 0x3a8); - -struct rk3288_sgrf_regs { - u32 soc_con0; - u32 soc_con1; - u32 soc_con2; - u32 soc_con3; - u32 soc_con4; - u32 soc_con5; - u32 reserved1[(0x20-0x18)/4]; - u32 busdmac_con[2]; - u32 reserved2[(0x40-0x28)/4]; - u32 cpu_con[3]; - u32 reserved3[(0x50-0x4c)/4]; - u32 soc_con6; - u32 soc_con7; - u32 soc_con8; - u32 soc_con9; - u32 soc_con10; - u32 soc_con11; - u32 soc_con12; - u32 soc_con13; - u32 soc_con14; - u32 soc_con15; - u32 soc_con16; - u32 soc_con17; - u32 soc_con18; - u32 soc_con19; - u32 soc_con20; - u32 soc_con21; - u32 reserved4[(0x100-0x90)/4]; - u32 soc_status[2]; - u32 reserved5[(0x120-0x108)/4]; - u32 fast_boot_addr; -}; -check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); - -static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; -static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; - -#define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) -#define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) -#define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) -#define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) -#define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) -#define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) -#define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ - 1 << 10 | 1 << 8) -#define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) -#define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) -#define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_I2SCLK RK_SETBITS(1 << 0) -#define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) -#define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ - 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) -#define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ - 2 << 8 | 2 << 6 | 2 << 4 |\ - 2 << 2 | 2 << 0) -#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) -#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) -#define IOMUX_PWM1 RK_SETBITS(1 << 2) -#endif diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c index eb480a7..d69bb7c 100644 --- a/src/soc/rockchip/rk3288/i2c.c +++ b/src/soc/rockchip/rk3288/i2c.c @@ -17,21 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> - -#include <delay.h> #include <cbfs.h> -#include <string.h> +#include <console/console.h> +#include <delay.h> #include <device/i2c.h> - -#include "addressmap.h" -#include "grf.h" -#include "soc.h" -#include "i2c.h" -#include "clock.h" +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/i2c.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <string.h> #define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/rk3288/i2c.h b/src/soc/rockchip/rk3288/i2c.h deleted file mode 100644 index 84d9b75..0000000 --- a/src/soc/rockchip/rk3288/i2c.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__ -#define __SOC_ROCKCHIP_RK3288_I2C_H__ - -void i2c_init(unsigned int bus, unsigned int hz); - -#endif - diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h new file mode 100644 index 0000000..aea3bc0 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ + +#define SDMMC1_BASE 0xFF0C0000 +#define SDMMC0_BASE 0xFF0D0000 +#define EMMC_BASE 0xFF0F0000 +#define SARADC_BASE 0xFF100000 + +#define SPI0_BASE 0xFF110000 +#define SPI1_BASE 0xFF120000 +#define SPI2_BASE 0xFF130000 + +#define I2C1_BASE 0xFF140000 +#define I2C3_BASE 0xFF150000 +#define I2C4_BASE 0xFF160000 +#define I2C5_BASE 0xFF170000 +#define UART0_BASE 0xFF180000 +#define UART1_BASE 0xFF190000 +#define DMAC_PERI_BASE 0xFF250000 +#define TSADC_BASE 0xFF280000 + +#define NANDC0_BASE 0xFF400000 +#define NANDC1_BASE 0xFF410000 + +#define USB_HOST0_EHCI_BASE 0xFF500000 +#define USB_HOST0_OHCI_BASE 0xFF520000 +#define USB_HOST1_BASE 0xFF540000 +#define USB_OTG_BASE 0xFF580000 + +#define DMAC_BUS_BASE 0xFF600000 + +#define DDR_PCTL0_BASE 0xFF610000 +#define DDR_PCTL1_BASE 0xFF630000 +#define DDR_PUBL0_BASE 0xFF620000 +#define DDR_PUBL1_BASE 0xFF640000 + +#define I2C0_BASE 0xFF650000 +#define I2C2_BASE 0xFF660000 +#define DW_PWM0123_BASE 0xFF670000 +#define RK_PWM0123_BASE 0xFF680000 +#define UART2_BASE 0xFF690000 +#define TIMER0_BASE 0xFF6B0000 + +#define SRAM_BASE 0xFF700000 +#define PMU_BASE 0xFF730000 +#define GRF_SECURE_BASE 0xFF740000 +#define GPIO0_BASE 0xFF750000 +#define CRU_BASE 0xFF760000 +#define GRF_BASE 0xFF770000 +#define GPIO1_BASE 0xFF780000 +#define GPIO2_BASE 0xFF790000 +#define GPIO3_BASE 0xFF7A0000 +#define GPIO4_BASE 0xFF7B0000 +#define GPIO5_BASE 0xFF7C0000 +#define GPIO6_BASE 0xFF7D0000 +#define GPIO7_BASE 0xFF7E0000 +#define GPIO8_BASE 0xFF7F0000 + +#define TIMER6_BASE 0xFF810000 +#define TIMER7_BASE 0xFF810020 + +#define VOP_BIG_BASE 0xFF930000 +#define HDMI_TX_BASE 0xFF980000 +#define DMACS_BUS_BASE 0xFFB20000 + +#define SERVICE_CORE_BASE 0xFFA80000 +#define SERVICE_DMA_BASE 0xFFA90000 +#define SERVICE_GPU_BASE 0xFFAA0000 +#define SERVICE_PERI_BASE 0xFFAB0000 +#define SERVICE_BUS_BASE 0xFFAC0000 +#define SERVICE_VIO_BASE 0xFFAD0000 +#define SERVICE_VPU_BASE 0xFFAE0000 +#define SERVICE_HEVC_BASE 0xFFAF0000 + +#define EFUSE_BASE 0xFFB40000 + +#define CORE_GICD_BASE 0xFFC01000 +#define CORE_GICC_BASE 0xFFC02000 +#define CPU_AXI_BUS_BASE 0xFFE00000 + +#define BOOT_ROM_BASE 0xFFFF0000 +#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) + +#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h new file mode 100644 index 0000000..d11c6ec --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CLOCK_H__ +#define __SOC_ROCKCHIP_RK3288_CLOCK_H__ + +#include <soc/addressmap.h> + +#define OSC_HZ (24*MHz) + +#define APLL_HZ (1800*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) + +#define PD_BUS_ACLK_HZ (148500*KHz) +#define PD_BUS_HCLK_HZ (148500*KHz) +#define PD_BUS_PCLK_HZ (74250*KHz) + +#define PERI_ACLK_HZ (148500*KHz) +#define PERI_HCLK_HZ (148500*KHz) +#define PERI_PCLK_HZ (74250*KHz) + +void rkclk_init(void); +void rkclk_configure_spi(unsigned int bus, unsigned int hz); +void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); +void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); +void rkclk_configure_ddr(unsigned int hz); +void rkclk_configure_i2s(unsigned int hz); +void rkclk_configure_cpu(void); +void rkclk_configure_tsadc(unsigned int hz); + +#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/gpio.h b/src/soc/rockchip/rk3288/include/soc/gpio.h new file mode 100644 index 0000000..c459de9 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/gpio.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__ +#define __SOC_ROCKCHIP_RK3288_GPIO_H__ + +#include <types.h> + +#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i}) + +struct rk3288_gpio_regs { + u32 swporta_dr; + u32 swporta_ddr; + u32 reserved0[(0x30 - 0x08) / 4]; + u32 inten; + u32 intmask; + u32 inttype_level; + u32 int_polarity; + u32 int_status; + u32 int_rawstatus; + u32 debounce; + u32 porta_eoi; + u32 ext_porta; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 ls_sync; +}; +check_member(rk3288_gpio_regs, ls_sync, 0x60); + +typedef union { + u32 raw; + struct { + u16 port; + union { + struct { + u16 num:5; + u16 :11; + }; + struct { + u16 idx:3; + u16 bank:2; + u16 :11; + }; + }; + }; +} gpio_t; + +enum { + GPIO_A = 0, + GPIO_B, + GPIO_C, + GPIO_D, +}; + +void gpio_input(gpio_t gpio); +void gpio_input_pulldown(gpio_t gpio); +void gpio_input_pullup(gpio_t gpio); +void gpio_output(gpio_t gpio, int value); +int gpio_get_in_value(gpio_t gpio); + +#endif /* _ASM_ROCKCHIP_GPIO_H_ */ diff --git a/src/soc/rockchip/rk3288/include/soc/grf.h b/src/soc/rockchip/rk3288/include/soc/grf.h new file mode 100644 index 0000000..8325638 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/grf.h @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ +#define __SOC_ROCKCHIP_RK3288_GRF_H__ + +#include <soc/addressmap.h> +#include <soc/soc.h> +#include <types.h> + +struct rk3288_grf_gpio_lh { + u32 l; + u32 h; +}; +check_member(rk3288_grf_gpio_lh, h, 0x4); + +struct rk3288_grf_regs { + u32 reserved[3]; + union { + u32 gpio1d_iomux; + u32 iomux_lcdc; + }; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + union { + u32 gpio2c_iomux; + u32 iomux_i2c3; + }; + u32 reserved2; + union { + u32 gpio3a_iomux; + u32 iomux_emmcdata; + }; + union { + u32 gpio3b_iomux; + u32 iomux_emmcpwren; + }; + union { + u32 gpio3c_iomux; + u32 iomux_emmccmd; + }; + u32 gpio3dl_iomux; + u32 gpio3dh_iomux; + u32 gpio4al_iomux; + u32 gpio4ah_iomux; + u32 gpio4bl_iomux; + u32 reserved3; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + u32 reserved4; + union { + u32 gpio5b_iomux; + u32 iomux_spi0; + }; + u32 gpio5c_iomux; + u32 reserved5; + union { + u32 gpio6a_iomux; + u32 iomux_i2s; + }; + union { + u32 gpio6b_iomux; + u32 iomux_i2c2; + u32 iomux_i2sclk; + }; + union { + u32 gpio6c_iomux; + u32 iomux_sdmmc0; + }; + u32 reserved6; + union { + u32 gpio7a_iomux; + u32 iomux_pwm0; + u32 iomux_pwm1; + }; + u32 gpio7b_iomux; + union { + u32 gpio7cl_iomux; + u32 iomux_i2c5sda; + u32 iomux_i2c4; + }; + union { + u32 gpio7ch_iomux; + u32 iomux_uart2; + u32 iomux_i2c5scl; + }; + u32 reserved7; + union { + u32 gpio8a_iomux; + u32 iomux_spi2csclk; + u32 iomux_i2c1; + }; + union { + u32 gpio8b_iomux; + u32 iomux_spi2txrx; + }; + u32 reserved8[30]; + struct rk3288_grf_gpio_lh gpio_sr[8]; + u32 gpio1_p[8][4]; + u32 gpio1_e[8][4]; + u32 gpio_smt; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_status[22]; + u32 reserved9[2]; + u32 peridmac_con[4]; + u32 ddrc0_con0; + u32 ddrc1_con0; + u32 cpu_con[5]; + u32 reserved10[3]; + u32 cpu_status0; + u32 reserved11; + u32 uoc0_con[5]; + u32 uoc1_con[5]; + u32 uoc2_con[4]; + u32 uoc3_con[2]; + u32 uoc4_con[2]; + u32 pvtm_con[3]; + u32 pvtm_status[3]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 os_reg[4]; + u32 reserved12; + u32 soc_con15; + u32 soc_con16; +}; +check_member(rk3288_grf_regs, soc_con16, 0x3a8); + +struct rk3288_sgrf_regs { + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 reserved1[(0x20-0x18)/4]; + u32 busdmac_con[2]; + u32 reserved2[(0x40-0x28)/4]; + u32 cpu_con[3]; + u32 reserved3[(0x50-0x4c)/4]; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 reserved4[(0x100-0x90)/4]; + u32 soc_status[2]; + u32 reserved5[(0x120-0x108)/4]; + u32 fast_boot_addr; +}; +check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); + +static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; +static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; + +#define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) +#define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) +#define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) +#define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) +#define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) +#define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) +#define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ + 1 << 10 | 1 << 8) +#define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) +#define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) +#define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_I2SCLK RK_SETBITS(1 << 0) +#define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) +#define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ + 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) +#define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ + 2 << 8 | 2 << 6 | 2 << 4 |\ + 2 << 2 | 2 << 0) +#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) +#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) +#define IOMUX_PWM1 RK_SETBITS(1 << 2) +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/i2c.h b/src/soc/rockchip/rk3288/include/soc/i2c.h new file mode 100644 index 0000000..84d9b75 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/i2c.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_I2C_H__ +#define __SOC_ROCKCHIP_RK3288_I2C_H__ + +void i2c_init(unsigned int bus, unsigned int hz); + +#endif + diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld new file mode 100644 index 0000000..2ddb6a6 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, + * so the bootblock loading address must be at 0xFF704004. + */ +SECTIONS +{ + DRAM_START(0x00000000) + RAMSTAGE(0x00200000, 128K) + POSTRAM_CBFS_CACHE(0x01000000, 1M) + DMA_COHERENT(0x10000000, 2M) + + SRAM_START(0xFF700000) + TTB(0xFF700000, 16K) + BOOTBLOCK(0xFF704004, 15K - 4) + TTB_SUBTABLES(0xFF707c00, 1K) + VBOOT2_WORK(0xFF708000, 16K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) + PRERAM_CBFS_CACHE(0xFF716000, 4K) + STACK(0xFF717000, 4K) + SRAM_END(0xFF718000) + + /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit + * wide write accesses! Only use with MMU and writeback mapping. */ + SYMBOL(pmu_sram, 0xFF720000) + SYMBOL(epmu_sram, 0xFF721000) +} diff --git a/src/soc/rockchip/rk3288/include/soc/pmu.h b/src/soc/rockchip/rk3288/include/soc/pmu.h new file mode 100644 index 0000000..2a93515 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/pmu.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PMU_H__ +#define __SOC_ROCKCHIP_RK3288_PMU_H__ + +#include <soc/addressmap.h> + +struct rk3288_pmu_regs { + u32 wakeup_cfg[2]; + u32 pwrdn_con; + u32 pwrdn_st; + u32 idle_req; + u32 idle_st; + u32 pwrmode_con; + u32 pwr_state; + u32 osc_cnt; + u32 pll_cnt; + u32 stabl_cnt; + u32 ddr0io_pwron_cnt; + u32 ddr1io_pwron_cnt; + u32 core_pwrdn_cnt; + u32 core_pwrup_cnt; + u32 gpu_pwrdn_cnt; + u32 gpu_pwrup_cnt; + u32 wakeup_rst_clr_cnt; + u32 sft_con; + u32 ddr_sref_st; + u32 int_con; + u32 int_st; + u32 boot_addr_sel; + u32 grf_con; + u32 gpio_sr; + u32 gpio0pull[3]; + u32 gpio0drv[3]; + u32 gpio_op; + u32 gpio0_sel18; + u32 gpio0a_iomux; + union { + u32 gpio0b_iomux; + u32 iomux_i2c0sda; + u32 iomux_tsadc_int; + }; + union { + u32 gpio0c_iomux; + u32 iomux_i2c0scl; + }; + union { + u32 gpio0d_iomux; + u32 iomux_lcdc0; + }; + u32 sys_reg[4]; +}; +check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0); + +static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE; + +#define IOMUX_I2C0SDA (1 << 14) +#define IOMUX_I2C0SCL (1 << 0) +#define IOMUX_TSADC_INT (1 << 4) + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/pwm.h b/src/soc/rockchip/rk3288/include/soc/pwm.h new file mode 100644 index 0000000..168d8a7 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/pwm.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__ +#define __SOC_ROCKCHIP_RK3288_PWM_H__ + +void pwm_init(u32 id, u32 period_ns, u32 duty_ns); + +#endif + diff --git a/src/soc/rockchip/rk3288/include/soc/rk808.h b/src/soc/rockchip/rk3288/include/soc/rk808.h new file mode 100644 index 0000000..e03ace8 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/rk808.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ +#define __SOC_ROCKCHIP_RK3288_PMIC_H__ + +void rk808_configure_switch(uint8_t bus, int sw, int enabled); +void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); +void rk808_configure_buck(uint8_t bus, int buck, int millivolts); + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/sdram.h b/src/soc/rockchip/rk3288/include/soc/sdram.h new file mode 100644 index 0000000..16e4f81 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/sdram.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ +#define __SOC_ROCKCHIP_RK3288_SDRAM_H__ + +enum { + DDR3 = 3, + LPDDR3 = 6, + UNUSED = 0xFF, +}; + +struct rk3288_sdram_channel { + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +}; + +struct rk3288_sdram_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; +check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); + +struct rk3288_sdram_phy_timing { + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr[4]; +}; + +struct rk3288_sdram_params { + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + u32 noc_timing; + u32 noc_activate; + u32 ddrconfig; + u32 ddr_freq; + u8 dramtype; + u8 num_channels; + u8 stride; + u8 odt; +}; + +void sdram_init(const struct rk3288_sdram_params *sdram_params); +u32 sdram_get_ram_code(void); +const struct rk3288_sdram_params *get_sdram_config(void); +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/soc.h b/src/soc/rockchip/rk3288/include/soc/soc.h new file mode 100644 index 0000000..00f35b2 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/soc.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_CPU_H__ +#define __SOC_ROCKCHIP_RK3288_CPU_H__ + +#include <arch/io.h> +#include <symbols.h> + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#define FB_SIZE_KB 4096 +#define RAM_BASE_KB ((uintptr_t)_dram >> 10) +#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) + +static inline u32 get_fb_base_kb(void) +{ + return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; +} +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/spi.h b/src/soc/rockchip/rk3288/include/soc/spi.h new file mode 100644 index 0000000..bba38ef --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/spi.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__ +#define __SOC_ROCKCHIP_RK3288_SPI_H__ + +/* This driver serves as a CBFS media source. */ +#include <cbfs.h> +#include <spi-generic.h> +#include <stdint.h> + +struct rockchip_spi { + u32 ctrlr0; + u32 ctrlr1; + u32 spienr; + u32 ser; + u32 baudr; + u32 txftlr; + u32 rxftlr; + u32 txflr; + u32 rxflr; + u32 sr; + u32 ipr; + u32 imr; + u32 isr; + u32 risr; + u32 icr; + u32 dmacr; + u32 damtdlr; + u32 damrdlr; + u32 reserved[(0x400-0x48)/4]; + u32 txdr[0x100]; + u32 rxdr[0x100]; +}; +check_member(rockchip_spi, rxdr, 0x800); + + +#define SF_READ_DATA_CMD 0x3 + +/* --------Bit fields in CTRLR0--------begin */ + +#define SPI_DFS_OFFSET 0 /* Data Frame Size */ +#define SPI_DFS_MASK 0x3 +#define SPI_DFS_4BIT 0x00 +#define SPI_DFS_8BIT 0x01 +#define SPI_DFS_16BIT 0x02 +#define SPI_DFS_RESV 0x03 + +/* Control Frame Size */ +#define SPI_CFS_OFFSET 2 +#define SPI_CFS_MASK 0xF + +/* Serial Clock Phase */ +#define SPI_SCPH_OFFSET 6 +#define SPI_SCPH_MASK 0x1 + +/* Serial clock toggles in middle of first data bit */ +#define SPI_SCPH_TOGMID 0 + +/* Serial clock toggles at start of first data bit */ +#define SPI_SCPH_TOGSTA 1 + +/* Serial Clock Polarity */ +#define SPI_SCOL_OFFSET 7 +#define SPI_SCOL_MASK 0x1 + +/* Inactive state of clock serial clock is low */ +#define SPI_SCOL_LOW 0 + +/* Inactive state of clock serial clock is high */ +#define SPI_SCOL_HIGH 1 + +/* Chip Select Mode */ +#define SPI_CSM_OFFSET 8 +#define SPI_CSM_MASK 0x3 + +/* ss_n keep low after every frame data is transferred */ +#define SPI_CSM_KEEP 0x00 + +/* + * ss_n be high for half sclk_out cycles after + * every frame data is transferred + */ +#define SPI_CSM_HALF 0x01 + +/* ss_n be high for one sclk_out cycle after every frame data is transferred */ +#define SPI_CSM_ONE 0x02 +#define SPI_CSM_RESV 0x03 + +/* SSN to Sclk_out delay */ +#define SPI_SSN_DELAY_OFFSET 10 +#define SPI_SSN_DELAY_MASK 0x1 +/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +#define SPI_SSN_DELAY_HALF 0x00 +/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +#define SPI_SSN_DELAY_ONE 0x01 + +/* Serial Endian Mode */ +#define SPI_SEM_OFFSET 11 +#define SPI_SEM_MASK 0x1 +/* little endian */ +#define SPI_SEM_LITTLE 0x00 +/* big endian */ +#define SPI_SEM_BIG 0x01 + +/* First Bit Mode */ +#define SPI_FBM_OFFSET 12 +#define SPI_FBM_MASK 0x1 +/* first bit in MSB */ +#define SPI_FBM_MSB 0x00 +/* first bit in LSB */ +#define SPI_FBM_LSB 0x01 + +/* Byte and Halfword Transform */ +#define SPI_HALF_WORLD_TX_OFFSET 13 +#define SPI_HALF_WORLD_MASK 0x1 +/* apb 16bit write/read, spi 8bit write/read */ +#define SPI_APB_16BIT 0x00 +/* apb 8bit write/read, spi 8bit write/read */ +#define SPI_APB_8BIT 0x01 + +/* Rxd Sample Delay */ +#define SPI_RXDSD_OFFSET 14 +#define SPI_RXDSD_MASK 0x3 + +/* Frame Format */ +#define SPI_FRF_OFFSET 16 +#define SPI_FRF_MASK 0x3 +/* motorola spi */ +#define SPI_FRF_SPI 0x00 +/* Texas Instruments SSP*/ +#define SPI_FRF_SSP 0x01 +/* National Semiconductors Microwire */ +#define SPI_FRF_MICROWIRE 0x02 +#define SPI_FRF_RESV 0x03 + +/* Transfer Mode */ +#define SPI_TMOD_OFFSET 18 +#define SPI_TMOD_MASK 0x3 +/* xmit & recv */ +#define SPI_TMOD_TR 0x00 +/* xmit only */ +#define SPI_TMOD_TO 0x01 +/* recv only */ +#define SPI_TMOD_RO 0x02 +#define SPI_TMOD_RESV 0x03 + +/* Operation Mode */ +#define SPI_OMOD_OFFSET 20 +#define SPI_OMOD_MASK 0x1 +/* Master Mode */ +#define SPI_OMOD_MASTER 0x00 +/* Slave Mode */ +#define SPI_OMOD_SLAVE 0x01 + +/* --------Bit fields in CTRLR0--------end */ +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f +#define SR_BUSY (1 << 0) +#define SR_TF_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << 0) +#define SPI_INT_TXOI (1 << 1) +#define SPI_INT_RXUI (1 << 2) +#define SPI_INT_RXOI (1 << 3) +#define SPI_INT_RXFI (1 << 4) + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << 1) +#define SPI_DMACR_RX_ENABLE (1 << 0) + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << 0) +#define SPI_CLEAR_INT_RXUI (1 << 1) +#define SPI_CLEAR_INT_RXOI (1 << 2) +#define SPI_CLEAR_INT_TXOI (1 << 3) + +/* Serve as CBFS media source */ +int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif diff --git a/src/soc/rockchip/rk3288/include/soc/timer.h b/src/soc/rockchip/rk3288/include/soc/timer.h new file mode 100644 index 0000000..2301686 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/timer.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ +#define __SOC_ROCKCHIP_RK3288_TIMER_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <timer.h> + +static const u32 clocks_per_usec = OSC_HZ/USECS_PER_SEC; + +struct rk3288_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; + +#define TIMER_LOAD_VAL 0xffffffff + +void rk3288_init_timer(void); + +#endif /* __SOC_ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/tsadc.h b/src/soc/rockchip/rk3288/include/soc/tsadc.h new file mode 100644 index 0000000..7412110 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/tsadc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ +#define __SOC_ROCKCHIP_RK3288_TSADC_H__ + +void tsadc_init(void); + +#endif diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c index f2471f9..7f0ea51 100644 --- a/src/soc/rockchip/rk3288/media.c +++ b/src/soc/rockchip/rk3288/media.c @@ -18,10 +18,9 @@ */ #include <cbfs.h> +#include <soc/spi.h> #include <symbols.h> -#include "spi.h" - int init_default_cbfs_media(struct cbfs_media *media) { return initialize_rockchip_spi_cbfs_media(media, diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld deleted file mode 100644 index 2ddb6a6..0000000 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> - -#include <arch/header.ld> - -/* Note: The BootROM will jump to 0xFF704004 after loading bootblock, - * so the bootblock loading address must be at 0xFF704004. - */ -SECTIONS -{ - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - DMA_COHERENT(0x10000000, 2M) - - SRAM_START(0xFF700000) - TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 15K - 4) - TTB_SUBTABLES(0xFF707c00, 1K) - VBOOT2_WORK(0xFF708000, 16K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) - PRERAM_CBFS_CACHE(0xFF716000, 4K) - STACK(0xFF717000, 4K) - SRAM_END(0xFF718000) - - /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit - * wide write accesses! Only use with MMU and writeback mapping. */ - SYMBOL(pmu_sram, 0xFF720000) - SYMBOL(epmu_sram, 0xFF721000) -} diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c index d33ed68..4062860 100644 --- a/src/soc/rockchip/rk3288/monotonic_timer.c +++ b/src/soc/rockchip/rk3288/monotonic_timer.c @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/timer.h> #include <stdint.h> #include <timer.h> -#include <arch/io.h> -#include "addressmap.h" -#include "timer.h" static uint64_t timer_raw_value(void) { diff --git a/src/soc/rockchip/rk3288/pmu.h b/src/soc/rockchip/rk3288/pmu.h deleted file mode 100644 index 23ca8b1..0000000 --- a/src/soc/rockchip/rk3288/pmu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PMU_H__ -#define __SOC_ROCKCHIP_RK3288_PMU_H__ -#include "addressmap.h" - -struct rk3288_pmu_regs { - u32 wakeup_cfg[2]; - u32 pwrdn_con; - u32 pwrdn_st; - u32 idle_req; - u32 idle_st; - u32 pwrmode_con; - u32 pwr_state; - u32 osc_cnt; - u32 pll_cnt; - u32 stabl_cnt; - u32 ddr0io_pwron_cnt; - u32 ddr1io_pwron_cnt; - u32 core_pwrdn_cnt; - u32 core_pwrup_cnt; - u32 gpu_pwrdn_cnt; - u32 gpu_pwrup_cnt; - u32 wakeup_rst_clr_cnt; - u32 sft_con; - u32 ddr_sref_st; - u32 int_con; - u32 int_st; - u32 boot_addr_sel; - u32 grf_con; - u32 gpio_sr; - u32 gpio0pull[3]; - u32 gpio0drv[3]; - u32 gpio_op; - u32 gpio0_sel18; - u32 gpio0a_iomux; - union { - u32 gpio0b_iomux; - u32 iomux_i2c0sda; - u32 iomux_tsadc_int; - }; - union { - u32 gpio0c_iomux; - u32 iomux_i2c0scl; - }; - union { - u32 gpio0d_iomux; - u32 iomux_lcdc0; - }; - u32 sys_reg[4]; -}; -check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0); - -static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE; - -#define IOMUX_I2C0SDA (1 << 14) -#define IOMUX_I2C0SCL (1 << 0) -#define IOMUX_TSADC_INT (1 << 4) - -#endif diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c index 7f659f2..a447249 100644 --- a/src/soc/rockchip/rk3288/pwm.c +++ b/src/soc/rockchip/rk3288/pwm.c @@ -17,18 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> -#include <timer.h> +#include <console/console.h> #include <delay.h> - -#include "addressmap.h" -#include "grf.h" -#include "soc.h" -#include "pwm.h" -#include "clock.h" +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pwm.h> +#include <soc/clock.h> +#include <stdlib.h> +#include <timer.h> struct pwm_ctl { u32 pwm_cnt; diff --git a/src/soc/rockchip/rk3288/pwm.h b/src/soc/rockchip/rk3288/pwm.h deleted file mode 100644 index 168d8a7..0000000 --- a/src/soc/rockchip/rk3288/pwm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__ -#define __SOC_ROCKCHIP_RK3288_PWM_H__ - -void pwm_init(u32 id, u32 period_ns, u32 duty_ns); - -#endif - diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index 48cfa86..aa39b8d 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -19,11 +19,11 @@ #include <assert.h> #include <console/console.h> +#include <delay.h> #include <device/i2c.h> +#include <soc/rk808.h> #include <stdint.h> #include <stdlib.h> -#include <delay.h> -#include "rk808.h" #define RK808_ADDR 0x1b diff --git a/src/soc/rockchip/rk3288/rk808.h b/src/soc/rockchip/rk3288/rk808.h deleted file mode 100644 index e03ace8..0000000 --- a/src/soc/rockchip/rk3288/rk808.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__ -#define __SOC_ROCKCHIP_RK3288_PMIC_H__ - -void rk808_configure_switch(uint8_t bus, int sw, int enabled); -void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts); -void rk808_configure_buck(uint8_t bus, int buck, int millivolts); - -#endif diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 2b0a396..d49b860 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> -#include <string.h> -#include <types.h> #include <console/console.h> #include <delay.h> -#include "addressmap.h" -#include "clock.h" -#include "sdram.h" -#include "grf.h" -#include "soc.h" -#include "pmu.h" +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/sdram.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <string.h> +#include <types.h> struct rk3288_ddr_pctl_regs { u32 scfg; diff --git a/src/soc/rockchip/rk3288/sdram.h b/src/soc/rockchip/rk3288/sdram.h deleted file mode 100644 index 1da14b7..0000000 --- a/src/soc/rockchip/rk3288/sdram.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ -#define __SOC_ROCKCHIP_RK3288_SDRAM_H__ - -#include <arch/io.h> - -enum { - DDR3 = 3, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - -struct rk3288_sdram_channel { - u8 rank; - u8 col; - u8 bk; - u8 bw; - u8 dbw; - u8 row_3_4; - u8 cs0_row; - u8 cs1_row; -}; - -struct rk3288_sdram_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; -}; -check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); - -struct rk3288_sdram_phy_timing { - u32 dtpr0; - u32 dtpr1; - u32 dtpr2; - u32 mr[4]; -}; - -struct rk3288_sdram_params { - struct rk3288_sdram_channel ch[2]; - struct rk3288_sdram_pctl_timing pctl_timing; - struct rk3288_sdram_phy_timing phy_timing; - u32 noc_timing; - u32 noc_activate; - u32 ddrconfig; - u32 ddr_freq; - u8 dramtype; - u8 num_channels; - u8 stride; - u8 odt; -}; - -void sdram_init(const struct rk3288_sdram_params *sdram_params); -u32 sdram_get_ram_code(void); -const struct rk3288_sdram_params *get_sdram_config(void); -#endif diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 0985c08..f5e52eb 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -17,16 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> -#include <string.h> -#include <stddef.h> -#include <delay.h> +#include <arch/cache.h> +#include <cbmem.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> -#include <cbmem.h> -#include <arch/cache.h> -#include <soc/rockchip/rk3288/gpio.h> -#include "soc.h" +#include <soc/gpio.h> +#include <soc/soc.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + #include "chip.h" static void soc_enable(device_t dev) diff --git a/src/soc/rockchip/rk3288/soc.h b/src/soc/rockchip/rk3288/soc.h deleted file mode 100644 index 00f35b2..0000000 --- a/src/soc/rockchip/rk3288/soc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_CPU_H__ -#define __SOC_ROCKCHIP_RK3288_CPU_H__ - -#include <arch/io.h> -#include <symbols.h> - -#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) -#define RK_SETBITS(set) RK_CLRSETBITS(0, set) -#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) - -#define FB_SIZE_KB 4096 -#define RAM_BASE_KB ((uintptr_t)_dram >> 10) -#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) - -static inline u32 get_fb_base_kb(void) -{ - return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; -} -#endif diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 796107e..6ece8c1 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -17,18 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> -#include <stdlib.h> #include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <delay.h> +#include <stdlib.h> #include <timer.h> -#include <endian.h> -#include "addressmap.h" -#include "spi.h" -#include "clock.h" struct rockchip_spi_slave { struct spi_slave slave; diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h deleted file mode 100644 index bba38ef..0000000 --- a/src/soc/rockchip/rk3288/spi.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_SPI_H__ -#define __SOC_ROCKCHIP_RK3288_SPI_H__ - -/* This driver serves as a CBFS media source. */ -#include <cbfs.h> -#include <spi-generic.h> -#include <stdint.h> - -struct rockchip_spi { - u32 ctrlr0; - u32 ctrlr1; - u32 spienr; - u32 ser; - u32 baudr; - u32 txftlr; - u32 rxftlr; - u32 txflr; - u32 rxflr; - u32 sr; - u32 ipr; - u32 imr; - u32 isr; - u32 risr; - u32 icr; - u32 dmacr; - u32 damtdlr; - u32 damrdlr; - u32 reserved[(0x400-0x48)/4]; - u32 txdr[0x100]; - u32 rxdr[0x100]; -}; -check_member(rockchip_spi, rxdr, 0x800); - - -#define SF_READ_DATA_CMD 0x3 - -/* --------Bit fields in CTRLR0--------begin */ - -#define SPI_DFS_OFFSET 0 /* Data Frame Size */ -#define SPI_DFS_MASK 0x3 -#define SPI_DFS_4BIT 0x00 -#define SPI_DFS_8BIT 0x01 -#define SPI_DFS_16BIT 0x02 -#define SPI_DFS_RESV 0x03 - -/* Control Frame Size */ -#define SPI_CFS_OFFSET 2 -#define SPI_CFS_MASK 0xF - -/* Serial Clock Phase */ -#define SPI_SCPH_OFFSET 6 -#define SPI_SCPH_MASK 0x1 - -/* Serial clock toggles in middle of first data bit */ -#define SPI_SCPH_TOGMID 0 - -/* Serial clock toggles at start of first data bit */ -#define SPI_SCPH_TOGSTA 1 - -/* Serial Clock Polarity */ -#define SPI_SCOL_OFFSET 7 -#define SPI_SCOL_MASK 0x1 - -/* Inactive state of clock serial clock is low */ -#define SPI_SCOL_LOW 0 - -/* Inactive state of clock serial clock is high */ -#define SPI_SCOL_HIGH 1 - -/* Chip Select Mode */ -#define SPI_CSM_OFFSET 8 -#define SPI_CSM_MASK 0x3 - -/* ss_n keep low after every frame data is transferred */ -#define SPI_CSM_KEEP 0x00 - -/* - * ss_n be high for half sclk_out cycles after - * every frame data is transferred - */ -#define SPI_CSM_HALF 0x01 - -/* ss_n be high for one sclk_out cycle after every frame data is transferred */ -#define SPI_CSM_ONE 0x02 -#define SPI_CSM_RESV 0x03 - -/* SSN to Sclk_out delay */ -#define SPI_SSN_DELAY_OFFSET 10 -#define SPI_SSN_DELAY_MASK 0x1 -/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ -#define SPI_SSN_DELAY_HALF 0x00 -/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ -#define SPI_SSN_DELAY_ONE 0x01 - -/* Serial Endian Mode */ -#define SPI_SEM_OFFSET 11 -#define SPI_SEM_MASK 0x1 -/* little endian */ -#define SPI_SEM_LITTLE 0x00 -/* big endian */ -#define SPI_SEM_BIG 0x01 - -/* First Bit Mode */ -#define SPI_FBM_OFFSET 12 -#define SPI_FBM_MASK 0x1 -/* first bit in MSB */ -#define SPI_FBM_MSB 0x00 -/* first bit in LSB */ -#define SPI_FBM_LSB 0x01 - -/* Byte and Halfword Transform */ -#define SPI_HALF_WORLD_TX_OFFSET 13 -#define SPI_HALF_WORLD_MASK 0x1 -/* apb 16bit write/read, spi 8bit write/read */ -#define SPI_APB_16BIT 0x00 -/* apb 8bit write/read, spi 8bit write/read */ -#define SPI_APB_8BIT 0x01 - -/* Rxd Sample Delay */ -#define SPI_RXDSD_OFFSET 14 -#define SPI_RXDSD_MASK 0x3 - -/* Frame Format */ -#define SPI_FRF_OFFSET 16 -#define SPI_FRF_MASK 0x3 -/* motorola spi */ -#define SPI_FRF_SPI 0x00 -/* Texas Instruments SSP*/ -#define SPI_FRF_SSP 0x01 -/* National Semiconductors Microwire */ -#define SPI_FRF_MICROWIRE 0x02 -#define SPI_FRF_RESV 0x03 - -/* Transfer Mode */ -#define SPI_TMOD_OFFSET 18 -#define SPI_TMOD_MASK 0x3 -/* xmit & recv */ -#define SPI_TMOD_TR 0x00 -/* xmit only */ -#define SPI_TMOD_TO 0x01 -/* recv only */ -#define SPI_TMOD_RO 0x02 -#define SPI_TMOD_RESV 0x03 - -/* Operation Mode */ -#define SPI_OMOD_OFFSET 20 -#define SPI_OMOD_MASK 0x1 -/* Master Mode */ -#define SPI_OMOD_MASTER 0x00 -/* Slave Mode */ -#define SPI_OMOD_SLAVE 0x01 - -/* --------Bit fields in CTRLR0--------end */ -/* Bit fields in SR, 7 bits */ -#define SR_MASK 0x7f -#define SR_BUSY (1 << 0) -#define SR_TF_FULL (1 << 1) -#define SR_TF_EMPT (1 << 2) -#define SR_RF_EMPT (1 << 3) -#define SR_RF_FULL (1 << 4) - -/* Bit fields in ISR, IMR, RISR, 7 bits */ -#define SPI_INT_TXEI (1 << 0) -#define SPI_INT_TXOI (1 << 1) -#define SPI_INT_RXUI (1 << 2) -#define SPI_INT_RXOI (1 << 3) -#define SPI_INT_RXFI (1 << 4) - -/* Bit fields in DMACR */ -#define SPI_DMACR_TX_ENABLE (1 << 1) -#define SPI_DMACR_RX_ENABLE (1 << 0) - -/* Bit fields in ICR */ -#define SPI_CLEAR_INT_ALL (1 << 0) -#define SPI_CLEAR_INT_RXUI (1 << 1) -#define SPI_CLEAR_INT_RXOI (1 << 2) -#define SPI_CLEAR_INT_TXOI (1 << 3) - -/* Serve as CBFS media source */ -int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); -void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); - -#endif diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 91186cc..7162482 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <console/console.h> #include <delay.h> -#include <arch/io.h> -#include "timer.h" +#include <soc/timer.h> +#include <timer.h> void init_timer(void) { diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h deleted file mode 100644 index 8507939..0000000 --- a/src/soc/rockchip/rk3288/timer.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__ -#define __SOC_ROCKCHIP_RK3288_TIMER_H__ - -#include <inttypes.h> -#include <timer.h> -#include "addressmap.h" -#include "clock.h" - -static const u32 clocks_per_usec = OSC_HZ/USECS_PER_SEC; - -struct rk3288_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; - -#define TIMER_LOAD_VAL 0xffffffff - -void rk3288_init_timer(void); - -#endif /* __SOC_ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 73980a0..b7d8e9d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <assert.h> #include <console/console.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/tsadc.h> #include <stdint.h> #include <stdlib.h> -#include <arch/io.h> -#include <delay.h> -#include "tsadc.h" -#include "clock.h" -#include "pmu.h" -#include "grf.h" struct rk3288_tsadc_regs { u32 user_con; diff --git a/src/soc/rockchip/rk3288/tsadc.h b/src/soc/rockchip/rk3288/tsadc.h deleted file mode 100644 index 7412110..0000000 --- a/src/soc/rockchip/rk3288/tsadc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__ -#define __SOC_ROCKCHIP_RK3288_TSADC_H__ - -void tsadc_init(void); - -#endif diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 60b14a3..01759fe 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -17,12 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/console.h> /* for __console definition */ -#include <stdint.h> +#include <console/uart.h> #include <drivers/uart/uart8250reg.h> +#include <stdint.h> /* * TODO: Use DRIVERS_UART_8250MEM driver instead.

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Patch set updated for coreboot: 2bebce9 arm: Add timestamp.c to bootblock and verstage
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9344 -gerrit commit 2bebce984e8088f9ddc44410aa3140055d5745d8 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:24:50 2014 -0700 arm: Add timestamp.c to bootblock and verstage BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t and verified timestamps on ryu Change-Id: Ia2d4d88c5230702319c5651641d8a1a3cc5128b5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a227beb4dd4de8c9e6188a62a3b92ba4eeded80c Original-Change-Id: I4687c2ffe77dcc93d0853de32c8492c7b4d1dbb0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223346 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 4b8b473..4277ca7 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -62,6 +62,7 @@ bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c +bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -83,6 +84,7 @@ verstage-y += memset.S verstage-y += memcpy.S verstage-y += memmove.S verstage-y += stages.c +verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ############################################################################### # romstage

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Patch set updated for coreboot: 1a74307 armv7: Change all memory domains to Client so XN bits work
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9343 -gerrit commit 1a743070f4c60bbac64d1db729dc05155cbd8b39 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 16 09:56:27 2014 -0700 armv7: Change all memory domains to Client so XN bits work Remember the XN bit? The one we had so much fun with on Nyan (LPAE) because not setting it allows random instruction prefetches to device memory that hang the system every few thousand boots? Thankfully, we had always been setting it in the non-LPAE MMU code already... "When the XN bit is 1, a Permission fault is generated if the processor attempts to execute an instruction fetched from the corresponding memory region. However, when using the Short-descriptor translation table format, the fault is generated only if the access is to memory in the Client domain, see Domains[...]" - ARM A.R.M. section B3.7.2 Oops. This patch changes our Domain Access Control Register (DACR) to set domain 0 (the only one we are using) to Client. This means that access permissions (AP[2:0] bits) become enforced, but they are already set to full access (0b011). It also means that non-LPAE systems will not be allowed to execute from DCACHE_OFF memory with enabled MMU anymore. As far as I can see, Veyron_Pinky has been the only board that does that. BUG=chrome-os-partner:32118 TEST=Booted Veyron_Pinky with MMU in the bootblock, saw hangs that look like spurious prefetches and confirmed that this patch fixes them. Change-Id: I81c00743f938924a5dc8825389fe512a069b77db Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cbc96db296a41ae700371a8515a1179c142f58e7 Original-Change-Id: I30676a5bfe12d516e5f910f51ee6854f6e5be557 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/armv7/mmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index de7fa40..581c572 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -302,6 +302,6 @@ void mmu_init(void) 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ ); - /* disable domain-level checking of permissions */ - write_dacr(~0); + /* Set domain 0 to Client so XN bit works (to prevent prefetches) */ + write_dacr(0x5); }

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Patch set updated for coreboot: 234e60e arm: Dump additional fault registers in abort handlers
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9345 -gerrit commit 234e60e7442f07eda2befc7575b6635ef16a5461 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 16 10:23:36 2014 -0700 arm: Dump additional fault registers in abort handlers Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm/exception.c | 12 +++++++ payloads/libpayload/include/arm/arch/cache.h | 48 ++++++++++++++++++++++++++++ src/arch/arm/armv7/exception.c | 6 ++++ src/arch/arm/include/armv7/arch/cache.h | 48 ++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/payloads/libpayload/arch/arm/exception.c b/payloads/libpayload/arch/arm/exception.c index d100937..6f17960 100644 --- a/payloads/libpayload/arch/arm/exception.c +++ b/payloads/libpayload/arch/arm/exception.c @@ -90,6 +90,18 @@ void exception_dispatch(u32 idx) printf("%s Exception\n", names[idx]); print_regs(); + switch (idx) { + case EXC_PABORT: + printf("IFAR = %#.8x\n", read_ifar()); + printf("IFSR = %#.8x\n", read_ifsr()); + printf("AIFSR = %#.8x\n", read_aifsr()); + break; + case EXC_DABORT: + printf("DFAR = %#.8x\n", read_dfar()); + printf("DFSR = %#.8x\n", read_dfsr()); + printf("ADFSR = %#.8x\n", read_adfsr()); + break; + }; dump_stack(exception_state.regs[13], 512); halt(); } diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index 67f6fd4..b258185 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -268,6 +268,54 @@ static inline void write_sctlr(uint32_t val) isb(); } +/* read data fault address register (DFAR) */ +static inline uint32_t read_dfar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val)); + return val; +} + +/* read data fault status register (DFSR) */ +static inline uint32_t read_dfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val)); + return val; +} + +/* read instruction fault address register (IFAR) */ +static inline uint32_t read_ifar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val)); + return val; +} + +/* read instruction fault status register (IFSR) */ +static inline uint32_t read_ifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val)); + return val; +} + +/* read auxiliary data fault status register (ADFSR) */ +static inline uint32_t read_adfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val)); + return val; +} + +/* read auxiliary instruction fault status register (AIFSR) */ +static inline uint32_t read_aifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val)); + return val; +} + /* * Cache maintenance API */ diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index eedd47d..4fac0bc 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -100,6 +100,9 @@ void exception_prefetch_abort(uint32_t *regs) printk(BIOS_ERR, "exception _prefetch_abort\n"); regs[15] -= 4; print_regs(regs); + printk(BIOS_ERR, "IFAR = %#.8x\n", read_ifar()); + printk(BIOS_ERR, "IFSR = %#.8x\n", read_ifsr()); + printk(BIOS_ERR, "AIFSR = %#.8x\n", read_aifsr()); dump_stack(regs[13], 512); die("exception"); } @@ -109,6 +112,9 @@ void exception_data_abort(uint32_t *regs) printk(BIOS_ERR, "exception _data_abort\n"); regs[15] -= 8; print_regs(regs); + printk(BIOS_ERR, "DFAR = %#.8x\n", read_dfar()); + printk(BIOS_ERR, "DFSR = %#.8x\n", read_dfsr()); + printk(BIOS_ERR, "ADFSR = %#.8x\n", read_adfsr()); dump_stack(regs[13], 512); die("exception"); } diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index f23dec1..12df5c3 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -295,6 +295,54 @@ static inline void write_sctlr(uint32_t val) isb(); } +/* read data fault address register (DFAR) */ +static inline uint32_t read_dfar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val)); + return val; +} + +/* read data fault status register (DFSR) */ +static inline uint32_t read_dfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val)); + return val; +} + +/* read instruction fault address register (IFAR) */ +static inline uint32_t read_ifar(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val)); + return val; +} + +/* read instruction fault status register (IFSR) */ +static inline uint32_t read_ifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val)); + return val; +} + +/* read auxiliary data fault status register (ADFSR) */ +static inline uint32_t read_adfsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val)); + return val; +} + +/* read auxiliary instruction fault status register (AIFSR) */ +static inline uint32_t read_aifsr(void) +{ + uint32_t val; + asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val)); + return val; +} + /* * Cache maintenance API */

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Patch set updated for coreboot: ed76eab tegra132: Remove clamp_tristate_inputs() call
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9346 -gerrit commit ed76eab8d13684d2187cd7321a69def5c39bf407 Author: Tom Warren <twarren(a)nvidia.com> Date: Fri Oct 17 10:27:09 2014 -0700 tegra132: Remove clamp_tristate_inputs() call As per NV SysEng, setting PINMUX_CLAMP_INPUTS=1 is now considered a bad thing. It clamps _all_ tristated inputs to zero, and isn't really the panacea for duplicated pinmux mappings as was stated previously. BUG=None BRANCH=None TEST=Built both Rush and Ryu OK. Tested on Rush, booted kernel OK. Change-Id: I7d6982a18a772efda7f1d3bf0dcb0d4d0a5bed8f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c5f77fa31961d39dd7b4bd2902288ead9ad80100 Original-Change-Id: I566c4516b34686b744a47a2b0c18c4b801456727 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224032 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra132/bootblock.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6f25050..0394c78 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -59,9 +59,6 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) void main(void) { - // enable pinmux clamp inputs - clamp_tristate_inputs(); - // enable JTAG at the earliest stage enable_jtag();

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Patch set updated for coreboot: 563add1 rk3288: configure l2ctlr in romstage
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9347 -gerrit commit 563add12945530a219d6b4a415ef8c8f33529683 Author: huang lin <hl(a)rock-chips.com> Date: Thu Oct 16 09:27:31 2014 -0700 rk3288: configure l2ctlr in romstage Data RAM write latency: 2 cycles Data RAM read latency: 2 cycles Data RAM setup latency: 1 cycle Tag RAM write latency: 1 cycle Tag RAM read latency: 1 cycle Tag RAM setup latency: 1 cycle BUG=None TEST=Boot Veyron Pinky Change-Id: I1d710f65114be6a976aa3fe23b076e89c14ac8b8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 421c2e5ba44f1693f8b3c869289fc93ab9ef5965 Original-Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223713 Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org> Original-Commit-Queue: Doug Anderson <dianders(a)chromium.org> --- src/mainboard/google/veyron_pinky/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 6f9b9d1..76a57e2 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -55,6 +55,25 @@ static void regulate_vdd_log(unsigned int mv) pwm_init(1, period_ns, duty_ns); } +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + void main(void) { #if CONFIG_COLLECT_TIMESTAMPS @@ -66,6 +85,7 @@ void main(void) #endif console_init(); + configure_l2ctlr(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200);

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Patch set updated for coreboot: 7948533 console: fix Kconfig uses
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9350 -gerrit commit 7948533cd84abf364652bf27303a02b1a099075d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Apr 7 13:49:32 2015 +0200 console: fix Kconfig uses CONFIG_CONSOLE_SERIAL_UART was renamed to CONFIG_DRIVERS_UART, so match that. Change-Id: I148fd8f46bc88c38ce1f62efe5771555bd5dcc5c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/romstage/Makefile.inc | 2 +- src/soc/rockchip/rk3288/Makefile.inc | 2 +- src/soc/rockchip/rk3288/bootblock.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index f8a9617..ae0f980 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -10,4 +10,4 @@ romstage-y += smbus.c romstage-y += spi.c romstage-y += stack.c romstage-y += systemagent.c -romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart.c +romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index d41919b..6af6225 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -36,7 +36,7 @@ bootblock-y += rk808.c verstage-y += monotonic_timer.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += gpio.c verstage-y += clock.c verstage-y += i2c.c diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index eec3456..27d78b4 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -29,7 +29,7 @@ static void bootblock_cpu_init(void) { rk3288_init_timer(); - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { + if (IS_ENABLED(CONFIG_DRIVERS_UART)) { switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) { case UART2_BASE: writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);

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Patch merged into coreboot/master: dae15a6 rk3288: Add early SRAM mapping
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit dae15a63e426230117b575f9acc504110748e98f Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Oct 15 18:50:45 2014 -0700 rk3288: Add early SRAM mapping Solving the DACR bug will mean that XN bits suddenly become enforced on non-LPAE systems, and we will no longer be able to execute out of a region mapped DCACHE_OFF. When we enable the MMU in romstage we are still executing out of SRAM, so we would instantly kill ourselves. Solve this issue by enabling the MMU earlier (in the bootblock) and mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be DCACHE_WRITEBACK, but it looks like there might be hardware limitations in the Cortex-A12 cache architecture that prevent us from doing so. Write-through mappings are equivalent to normal non-cacheable on the A12 anyway, and by using this attribute we don't need to introduce a new DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal non-cacheable might still have a slight speed advantage over strongly ordered since it should fetch whole cache lines at once if the processor finds enough accesses it can combine.) CQ-DEPEND=CL:223783 BUG=chrome-os-partner:32118 TEST=None (depends on follow-up CL) Change-Id: I1e5127421f82177ca11af892b1539538b379625e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847 Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223782 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9342 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9342 for details. -gerrit

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coreboot-gerrit April 2015