coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 108548a armv7: Add fine-grained page table support
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 108548a42aa3a255bd84247549cd1bf406a152f1 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 9 17:31:45 2014 -0700 armv7: Add fine-grained page table support This patch adds an mmu_config_range_kb() function, which can set memory types at the 4KB level by chaining a fine-grained page table to an existing superpage entry. It is only intended for special cases where this level of precision is really necessary and therefore comes with a few practical limitations (the area for each invocation must be confined within a single superpage, and you are not allowed to remap the same region with mmu_config_range() again later). Since the fine-grained page tables need some space, boards intending to use this feature must define a TTB_SUBTABLES() region in their memlayout.ld. BUG=chrome-os-partner:32848 TEST=Booted both Veyron_Pinky (normal) and Nyan_Blaze (LPAE), ensured that they still work. Checksummed the page tables with and without this patch, confirmed that they end up equal. Hacked in some subtable test entries, hexdumped all tables and manually confirmed that they look as expected. Change-Id: I8c3eb7c2eb9c82e2abc5f2c0dda91f5b2eee7023 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2f13e60cf5509b9a63fb7b8d84846daf889dc1b7 Original-Change-Id: Iedf7ca435ae337ead85115200d6987fb0d4828d7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223781 Reviewed-on: http://review.coreboot.org/9341 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9341 for details. -gerrit

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Patch merged into coreboot/master: 42e23a6 timestamp: Add bootblock start and end to timestamp constants
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 42e23a67ad2cd99fe7f9658b82d9dd2109643d68 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:18:38 2014 -0700 timestamp: Add bootblock start and end to timestamp constants BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t to check proper timestamps on ryu Change-Id: Ic31c5d9f3e397d90b08fe1c5e152148f4a278b95 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 92469e04c1c52bd60a8a37f017d865d0a838bff5 Original-Change-Id: I95419a6d240c168c8b6a489cac969390ecf6dea0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223345 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9340 for details. -gerrit

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Patch merged into coreboot/master: f8dcdea rk3288: Fix some PLL divisors and improve clock code
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit f8dcdea60973b729bf9eee0fb46dccf1b4b2aeb6 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 6 15:02:12 2014 -0700 rk3288: Fix some PLL divisors and improve clock code This patch does some general cleanup in the Rockchip clock code, and adds some more assertions regarding the PLL VCO and output frequency ranges. It changes all PLL divisors to use the lowest values that can still hit the target frequency, since higher NR values lead to higher jitter and higher NO values increase power draw. Also change DDR3 frequency code to hardcode the optimal divisors for certail frequencies. As a little hack we will interpret 666000000 to actually mean 666666666.6P (and analogous for 533MHz), since that's what you usually want for memory. BUG=chrome-os-partner:32139 TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in /sys/kernel/debug/clk/clk_summary. Change-Id: I57d7ef34500984184e010c0cc7d73789338834d4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7466ffc035b3f06ac280f412bc496059abf3239c Original-Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221801 Reviewed-on: http://review.coreboot.org/9339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9339 for details. -gerrit

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Patch merged into coreboot/master: 558614d rk3288: Re-write spi_xfer() to support full duplex
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 558614d4d38d149865c2186802548eec55a03082 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Sep 12 18:58:47 2014 -0700 rk3288: Re-write spi_xfer() to support full duplex This change re-writes the spi_xfer() function to support full-duplex transfers. Even though the code looks much different, the same basic algorithm for setting up the transfer is used. The main difference is that reads from rxdr and writes to txdr occur simultaneously and accounting is more complicated, so I separated the higher-level accounting portion from the low-level FIFO handling portion to simplify things. BUG=chrome-os-partner:31850 BRANCH=none TEST=Loaded content from SPI ROM fine, needs testing w/ EC Change-Id: Ic109a02daf52ba694b63a73fec1a72b3c5c0fd71 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6a14f5ff8ed04d62e8de6ad2f468b763ffb8213c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I33d2f5179360baf94627c86b57d12f032897caf5 Original-Reviewed-on: https://chromium-review.googlesource.com/218881 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/9338 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9338 for details. -gerrit

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Patch merged into coreboot/master: 0edf419 ectool: add query function to ectool
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 0edf419852501583985475ae7084e508dc66eb8f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Feb 6 22:27:33 2015 +0100 ectool: add query function to ectool `ectool -q` - Query the EC IRQ byte. Should return 0x00 otherwise the IRQ handler is usally broken or disabled. Tested-on: Lenovo X201t Change-Id: I0b8c2dbcf38d2eab89d0fbea05795759c4517f6d Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8382 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/8382 for details. -gerrit

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Patch merged into coreboot/master: 46ca3a5 ectool: add --dump / -d for RAM dump
by gerrit＠coreboot.org 08 Apr '15

08 Apr '15

the following patch was just integrated into master: commit 46ca3a55344b326553358b5119cb8a342a493ed4 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Feb 7 04:10:12 2015 +0100 ectool: add --dump / -d for RAM dump This moves the ram dump behind an argument, but it's still called by default when no other arguments given. To hold backward compatibility -i also prints out RAM. Change-Id: I82648e8cf1eac455e9937bd3669a0e91a3ee87cf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8381 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/8381 for details. -gerrit

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Patch merged into coreboot/master: 7ca6522 rmodule: remove cbmem_entry usage
by gerrit＠coreboot.org 07 Apr '15

07 Apr '15

the following patch was just integrated into master: commit 7ca6522412fe75bab69f18107d7efa2e05381d38 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 6 17:18:18 2015 -0500 rmodule: remove cbmem_entry usage As cbmem_entry has been removed from ramstage loading there's no need to keep the intermediate cbmem_entry around. The region containing the rmodule program can just be used directly. Change-Id: I06fe07f07130b1c7f9e374a00c6793d241364ba8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9328 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9328 for details. -gerrit

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Patch set updated for coreboot: 578d549 rmodule: remove cbmem_entry usage
by Aaron Durbin 07 Apr '15

07 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9328 -gerrit commit 578d5496485e66657c278ee0997665f4aee8967b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 6 17:18:18 2015 -0500 rmodule: remove cbmem_entry usage As cbmem_entry has been removed from ramstage loading there's no need to keep the intermediate cbmem_entry around. The region containing the rmodule program can just be used directly. Change-Id: I06fe07f07130b1c7f9e374a00c6793d241364ba8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/rmodule.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index d7dc969..799d8f0 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -259,7 +259,6 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) char *stage_region; int rmodule_offset; int load_offset; - const struct cbmem_entry *cbmem_entry; if (stage == NULL || rsl->prog == NULL || rsl->prog->name == NULL) return -1; @@ -268,13 +267,11 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, stage->memlen, &region_size, &load_offset); - cbmem_entry = cbmem_entry_add(rsl->cbmem_id, region_size); + stage_region = cbmem_add(rsl->cbmem_id, region_size); - if (cbmem_entry == NULL) + if (stage_region == NULL) return -1; - stage_region = cbmem_entry_start(cbmem_entry); - printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", rsl->prog->name, &stage_region[rmodule_offset], stage->memlen); @@ -288,7 +285,8 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) if (rmodule_load(&stage_region[load_offset], &rmod_stage)) return -1; - prog_set_area(rsl->prog, stage_region, cbmem_entry_size(cbmem_entry)); + prog_set_area(rsl->prog, rmod_stage.location, + rmodule_memory_size(&rmod_stage)); prog_set_entry(rsl->prog, rmodule_entry(&rmod_stage), NULL); return 0;

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Patch merged into coreboot/master: b0d8f5e hardwaremain: explicitly call cbmem_initialize() early
by gerrit＠coreboot.org 07 Apr '15

07 Apr '15

the following patch was just integrated into master: commit b0d8f5e9cdab5c53cb8438175517ad171e9e5ddb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 6 16:12:58 2015 -0500 hardwaremain: explicitly call cbmem_initialize() early Over the course of time there have been some implicit assumptions about cbmem being available for find() or add() operations. However, the cbmem area was never fully recovered until entering the state machine: BS_ON_ENTRY into BS_PRE_DEVICE. Correct this assumption by explicitly calling cbmem_initialize() in the EARLY_CBMEM_INIT case. This, however, doesn't fix timestamp_init() showing an error about not being able to allocate the timestamp table. Change-Id: Ib93fcc932e202ebd37822f07a278ea9694fe965c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9327 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9327 for details. -gerrit

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Patch merged into coreboot/master: 8c5e4d9 cbfs: Enforce media->map() result checking, improve error messages
by gerrit＠coreboot.org 07 Apr '15

07 Apr '15

the following patch was just integrated into master: commit 8c5e4d93db845fc1942438d54eedbdefcfd2bbf9 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Oct 10 14:11:11 2014 -0700 cbfs: Enforce media->map() result checking, improve error messages If you try to boot a VBOOT2_VERIFY_FIRMWARE with less than 4K CBFS cache right now, your system will try and fail to validate the FMAP signature at (u8 *)0xFFFFFFFF and go into recovery mode. This patch avoids the memcmp() to potentially invalid memory, and also adds an error message to cbfs_simple_buffer_map() to make it explicit that we ran out of CBFS cache space. BUG=None TEST=Booted on Veyron_Pinky with reduced CBFS cache, saw the message. Original-Change-Id: Ic5773b4e0b36dc621513f58fc9bd29c17afbf1b7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222899 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 0ed3c0c2b63be0d32e8162faf892e41cef1f1f23) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I20ccac83bff4a377caca6327d0e21032efff44c1 Reviewed-on: http://review.coreboot.org/9373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9373 for details. -gerrit

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coreboot-gerrit April 2015