coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 2089f6e arm64: secmon: prepare for passing more state into secmon
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9395 -gerrit commit 2089f6e0951815c4306323272469b70cd8ec12a7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 5 10:48:16 2014 -0600 arm64: secmon: prepare for passing more state into secmon The current implementation of secmon assumes just entry/arg are passed to secmon for starting up a CPU. That's lacking in flexibility. Therefore change secmon_params to contain both the BSP and secondary CPUs' entry/arg information. That way more information can be added to secmon_params when needed. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and booted SMP kernel using PSCI and spin table. Change-Id: I84c478ccefdfa4580fcc078a2491f49f86a9757a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c5fb5bd857a4318174f5b9b48e28406e60a466f8 Original-Change-Id: Iafb82d5cabc806b6625799a6b3dff8d77bdb27e9 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227548 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/secmon_init.c | 22 ++++++++------- src/arch/arm64/armv8/secmon_loader.c | 43 +++++++++++++++++------------- src/arch/arm64/include/armv8/arch/secmon.h | 4 +-- 3 files changed, 39 insertions(+), 30 deletions(-) diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c index fb3422f..8fd3917 100644 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ b/src/arch/arm64/armv8/secmon/secmon_init.c @@ -30,16 +30,21 @@ #include <stddef.h> #include "secmon.h" -/* Save initial secmon params per CPU to handle turn up. */ -static struct secmon_params *init_params[CONFIG_MAX_CPUS]; - static void start_up_cpu(void *arg) { - struct secmon_params *params = init_params[cpu_info()->id]; + struct secmon_params *params = arg; + struct cpu_action *action; + + if (cpu_is_bsp()) + action = &params->bsp; + else + action = &params->secondary; + - if (params == NULL) + if (action->run == NULL) psci_turn_off_self(); - psci_turn_on_self(params->entry, params->arg); + + psci_turn_on_self(action->run, action->arg); } static void cpu_init(int bsp) @@ -75,13 +80,12 @@ static void secmon_init(struct secmon_params *params, int bsp) { struct cpu_action action = { .run = start_up_cpu, + .arg = params, }; exception_hwinit(); cpu_init(bsp); - init_params[cpu_info()->id] = params; - if (!cpu_is_bsp()) secmon_wait_for_action(); @@ -94,7 +98,7 @@ static void secmon_init(struct secmon_params *params, int bsp) /* Make sure all non-BSP CPUs take action before the BSP. */ arch_run_on_all_cpus_but_self_async(&action); /* Turn on BSP. */ - start_up_cpu(NULL); + start_up_cpu(params); printk(BIOS_ERR, "CPU turn on failed for BSP.\n"); while (1) diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c index 0098228..59a6ba7 100644 --- a/src/arch/arm64/armv8/secmon_loader.c +++ b/src/arch/arm64/armv8/secmon_loader.c @@ -79,26 +79,22 @@ static secmon_entry_t secmon_load_rmodule(void) struct secmon_runit { secmon_entry_t entry; - struct secmon_params bsp_params; - struct secmon_params secondary_params; + struct secmon_params params; }; static void secmon_start(void *arg) { uint32_t scr; secmon_entry_t entry; - struct secmon_params *p = NULL; + struct secmon_params *p; struct secmon_runit *r = arg; entry = r->entry; + p = &r->params; - if (cpu_is_bsp()) - p = &r->bsp_params; - else { + /* Obtain secondary entry point for non-BSP CPUs. */ + if (!cpu_is_bsp()) entry = secondary_entry_point(entry); - if (r->secondary_params.entry != NULL) - p = &r->secondary_params; - } printk(BIOS_DEBUG, "CPU%x entering secure monitor %p.\n", cpu_info()->id, entry); @@ -113,9 +109,26 @@ static void secmon_start(void *arg) entry(p); } -void secmon_run(void (*entry)(void *), void *cb_tables) +static void fill_secmon_params(struct secmon_params *p, + void (*bsp_entry)(void *), void *bsp_arg) { const struct spintable_attributes *spin_attrs; + + memset(p, 0, sizeof(*p)); + + spin_attrs = spintable_get_attributes(); + + if (spin_attrs != NULL) { + p->secondary.run = spin_attrs->entry; + p->secondary.arg = spin_attrs->addr; + } + + p->bsp.run = bsp_entry; + p->bsp.arg = bsp_arg; +} + +void secmon_run(void (*entry)(void *), void *cb_tables) +{ static struct secmon_runit runit; struct cpu_action action = { .run = secmon_start, @@ -137,15 +150,7 @@ void secmon_run(void (*entry)(void *), void *cb_tables) printk(BIOS_DEBUG, "ARM64: Loaded the el3 monitor...jumping to %p\n", runit.entry); - runit.bsp_params.entry = entry; - runit.bsp_params.arg = cb_tables; - - spin_attrs = spintable_get_attributes(); - - if (spin_attrs != NULL) { - runit.secondary_params.entry = spin_attrs->entry; - runit.secondary_params.arg = spin_attrs->addr; - } + fill_secmon_params(&runit.params, entry, cb_tables); arch_run_on_all_cpus_but_self_async(&action); secmon_start(&runit); diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h index 12dd8c4..dc4b2e0 100644 --- a/src/arch/arm64/include/armv8/arch/secmon.h +++ b/src/arch/arm64/include/armv8/arch/secmon.h @@ -25,8 +25,8 @@ #if IS_ENABLED(CONFIG_ARCH_USE_SECURE_MONITOR) struct secmon_params { - void (*entry)(void *); - void *arg; + struct cpu_action bsp; + struct cpu_action secondary; }; void secmon_run(void (*entry)(void *), void *arg);

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New patch to review for coreboot: 4aa7426 arm64: secmon: wait for all CPUs to enter secmon
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9394 -gerrit commit 4aa74268c94b4c1daec8c5b591b791a5ae3c76c3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 5 10:23:33 2014 -0600 arm64: secmon: wait for all CPUs to enter secmon There is state within the system that relies on having all CPUs present in order to proceed with initialization. The current expectation is that all CPUs are online and entering the secure monitor. Therefore, wait until all CONFIG_MAX_CPUs show up. BUG=chrome-os-partner:32112 BRANCH=None TEST=Can get all CPUs up in kernel using PSCI. Change-Id: I741a09128e99e0cb0c9f4046b1c0d27582fda963 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 030535b7c9821b40bf4a51f88e289eab8af9aa13 Original-Change-Id: Ia0f744c93766efc694b522ab0af9aedf7329ac43 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227547 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/secmon_init.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c index 2ec2f13..fb3422f 100644 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ b/src/arch/arm64/armv8/secmon/secmon_init.c @@ -53,6 +53,24 @@ static void cpu_init(int bsp) cpu_set_bsp(); } +static void wait_for_all_cpus(void) +{ + int all_online; + + while (1) { + int i; + + all_online = 1; + for (i = 0; i < CONFIG_MAX_CPUS; i++) { + if (!cpu_online(cpu_info_for_cpu(i))) + all_online = 0; + } + + if (all_online) + break; + } +} + static void secmon_init(struct secmon_params *params, int bsp) { struct cpu_action action = { @@ -67,6 +85,9 @@ static void secmon_init(struct secmon_params *params, int bsp) if (!cpu_is_bsp()) secmon_wait_for_action(); + /* Wait for all CPUs to enter secmon. */ + wait_for_all_cpus(); + smc_init(); psci_init();

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New patch to review for coreboot: bf86fd6 arm: Fix CONFIG name: ARM_V7 to ARMV7
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9393 -gerrit commit bf86fd6c51350dd6862e6d879676c13d50a812a5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 8 12:24:09 2015 +0200 arm: Fix CONFIG name: ARM_V7 to ARMV7 Introduced in commit dfb8eb10 Change-Id: I18d44c2b2dcb8bd8e2b5487d76951640ffeece1b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index dac4276..17cb69e 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -50,7 +50,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 ## verification stage ################################################################################ -ifeq ($(CONFIG_ARCH_VERSTAGE_ARM_V7),y) +ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7),y) verstage-c-ccopts += $(armv7_flags) verstage-S-ccopts += $(armv7_asm_flags)

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New patch to review for coreboot: 3ac7beb arm64: secmon: direct non-BSP cpus to start before BSP
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9392 -gerrit commit 3ac7beb57e1fde769ea97230d99eb48848333e16 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 4 20:47:23 2014 -0600 arm64: secmon: direct non-BSP cpus to start before BSP The arch_run_on_all_cpus[_async]() APIs can run the BSP before the APs if the BSP's id is less than the APs' ids. Fix this by ensuring we run the necessary callback on all but self. BUG=chrome-os-partner:33532 BRANCH=None TEST=Booted spin table kernel. All CPUs are up. Change-Id: Ic9a466c3642595bad06cac83647de81873b8353e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 575437354cc20eeac8015a0f7b0c9999ecb0deee Original-Change-Id: I87e944f870105dbde33b5460660c96c93c3cdf93 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227488 Original-Tested-by: David Riley <davidriley(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/secmon_init.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c index 9097a08..2ec2f13 100644 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ b/src/arch/arm64/armv8/secmon/secmon_init.c @@ -70,7 +70,10 @@ static void secmon_init(struct secmon_params *params, int bsp) smc_init(); psci_init(); - arch_run_on_all_cpus_async(&action); + /* Make sure all non-BSP CPUs take action before the BSP. */ + arch_run_on_all_cpus_but_self_async(&action); + /* Turn on BSP. */ + start_up_cpu(NULL); printk(BIOS_ERR, "CPU turn on failed for BSP.\n"); while (1)

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New patch to review for coreboot: 0952085 tegra132: configure debug uart to 115200n8 in tegra_lp0_resume
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9391 -gerrit commit 095208556d53180a30ac9a1365352a1d4376cff1 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Oct 29 17:42:47 2014 -0700 tegra132: configure debug uart to 115200n8 in tegra_lp0_resume Need to configure debug uart port to have proper baudrate/width/parity. Hard-code it to 115200n8. BUG=chrome-os-partner:32015 BRANCH=None TEST=successfully suspend/resume on Rush/Ryu Change-Id: I502fd8361baf2bea642fabbc4d5e126da5411ba3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c70625ad41efca9117c8682113b226e929e93c5 Original-Change-Id: I6a96c80654ce52f5b877fd46995ca8c1aceb7017 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226407 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c | 38 ++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 87c3ccb..a52e918 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -311,6 +311,27 @@ static uint32_t *uart_clk_source_regs[4] = { (uint32_t *)0x600061c0, }; +static uint32_t *uart_base_regs[4] = { + (uint32_t *)0x70006000, + (uint32_t *)0x70006040, + (uint32_t *)0x70006200, + (uint32_t *)0x70006300, +}; +enum { + UART_THR_DLAB = 0x0, + UART_IER_DLAB = 0x1, + UART_IIR_FCR = 0x2, + UART_LCR = 0x3 +}; +enum { + UART_RATE_115200 = (408000000/115200/16), /* based on 408000000 PLLP */ + FCR_TX_CLR = 0x4, /* bit 2 of FCR : clear TX FIFO */ + FCR_RX_CLR = 0x2, /* bit 1 of FCR : clear RX FIFO */ + FCR_EN_FIFO = 0x1, /* bit 0 of FCR : enable TX & RX FIFO */ + LCR_DLAB = 0x80, /* bit 7 of LCR : Divisor Latch Access Bit */ + LCR_WD_SIZE_8 = 0x3, /* bit 1:0 of LCR : word length of 8 */ +}; + static void enable_uart(void) { uint32_t *uart_clk_enb_reg; @@ -318,6 +339,7 @@ static void enable_uart(void) uint32_t *uart_clk_source; uint32_t uart_port; uint32_t uart_mask; + uint32_t *uart_base; /* * Read odmdata (stored in pmc->odmdata) to determine debug uart port. @@ -330,14 +352,15 @@ static void enable_uart(void) */ uart_port = (read32(pmc_odmdata_ptr) >> 15) & 0x7; - /* Default to UARTA, since pmc_odmdata is not programmed yet. */ - /* TODO: if (uart_port >= 4) */ + /* Default to UARTA if uart_port is out of range */ + if (uart_port >= 4) uart_port = 0; uart_clk_enb_reg = uart_clk_out_enb_regs[uart_port]; uart_rst_reg = uart_rst_devices_regs[uart_port]; uart_mask = uart_enable_mask[uart_port]; uart_clk_source = uart_clk_source_regs[uart_port]; + uart_base = uart_base_regs[uart_port]; /* Enable UART clock */ setbits32(uart_mask, uart_clk_enb_reg); @@ -348,6 +371,17 @@ static void enable_uart(void) /* Program UART clock source: PLLP (408000000) */ write32(0, uart_clk_source); + + /* Program 115200n8 to the uart port */ + /* baud-rate of 115200 */ + write32(LCR_DLAB, (uart_base + UART_LCR)); + write32((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB)); + write32((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB)); + /* 8-bit and no parity */ + write32(LCR_WD_SIZE_8, (uart_base + UART_LCR)); + /* enable and clear RX/TX FIFO */ + write32((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO), + (uart_base + UART_IIR_FCR)); } /* Accessors. */

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New patch to review for coreboot: 775ffea arm64: psci: add node hierarchy
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9390 -gerrit commit 775ffea82c670f7d50f2151ae73d4627934bb3c0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 28 15:38:17 2014 -0500 arm64: psci: add node hierarchy In order to properly support more arm64 SoCs PSCI needs to handle the hierarchy of cpus/clusters within the SoC. The nodes within PSCI are kept in a tree as well as a depth-first ordered array of same tree. Additionally, the PSCI states are now maintained in a hierachal manner. OFF propogates up the tree as long as all siblings are set to OFF. ON propogates up the tree until a node is not already set to OFF. The SoC provides the operations for determining how many children are at a given affinity level. Lastly, the secmon startup has been reworked in that all non-BSP CPUs wait for instructions from the BSP. BUG=chrome-os-partner:32136 BRANCH=None TEST=Can still boot into kernel with SMP. Change-Id: I036fabaf0f1cefa2841264c47e4092c75a2ff4dc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 721d408cd110e1b56d38789177b740aa0e54ca33 Original-Change-Id: I520a9726e283bee7edcb514cda28ec1eb31b5ea0 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226480 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/psci.c | 440 ++++++++++++++++++++++++------ src/arch/arm64/armv8/secmon/secmon_init.c | 29 +- src/arch/arm64/armv8/secmon/smc.c | 12 +- src/arch/arm64/include/arch/psci.h | 82 ++++++ src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/psci.c | 46 ++++ 6 files changed, 527 insertions(+), 83 deletions(-) diff --git a/src/arch/arm64/armv8/secmon/psci.c b/src/arch/arm64/armv8/secmon/psci.c index 9764cac..0051031 100644 --- a/src/arch/arm64/armv8/secmon/psci.c +++ b/src/arch/arm64/armv8/secmon/psci.c @@ -28,23 +28,14 @@ #include <console/console.h> #include "secmon.h" -enum { - PSCI_CPU_STATE_OFF = 0, - PSCI_CPU_STATE_ON_PENDING, - PSCI_CPU_STATE_ON, -}; - -struct psci_cpu_state { - uint64_t mpidr; - void *entry; - void *arg; - int state; -}; - DECLARE_SPIN_LOCK(psci_spinlock); -static struct psci_cpu_state psci_state[CONFIG_MAX_CPUS]; +/* Root of PSCI node tree. */ +static struct psci_node psci_root; +/* Array of all the psci_nodes in system. */ +static size_t psci_num_nodes; +static struct psci_node **psci_nodes; static inline void psci_lock(void) { @@ -56,33 +47,173 @@ static inline void psci_unlock(void) spin_unlock(&psci_spinlock); } -static inline int psci_cpu_state_locked(int i) +static inline int psci_state_locked(const struct psci_node *e) { - return psci_state[i].state; + return e->state; } -static inline void psci_cpu_set_state_locked(int i, int s) +static inline void psci_set_state_locked(struct psci_node *e, int s) { - psci_state[i].state = s; + e->state = s; } -static struct cpu_info *mpidr_to_cpu_info(uint64_t mpidr) +static struct psci_node *psci_node_lookup(uint64_t mpidr, int level) { - int i; + size_t i; + + /* The array of node pointers are in depth-first order of the tree. */ + for (i = 0; i < psci_num_nodes; i++) { + struct psci_node *current = psci_nodes[i]; + + if (current->mpidr > mpidr) + break; + if (current->mpidr < mpidr) + continue; + if (current->level == level) + return current; + } + return NULL; +} + +static inline struct psci_node *node_self(void) +{ + return psci_node_lookup(cpu_info()->mpidr, PSCI_AFFINITY_LEVEL_0); +} - for (i = 0; i < ARRAY_SIZE(psci_state); i++) { - if (mpidr == psci_state[i].mpidr) - return cpu_info_for_cpu(i); +/* Find the ancestor of node affected by a state transition limited by level. */ +static struct psci_node *psci_find_ancestor(struct psci_node *e, int level, + int state) +{ + struct psci_node *p; + + /* If all siblings of the node are already off then parent can be + * set to off as well. */ + if (state == PSCI_STATE_OFF) { + while (1) { + size_t i; + struct psci_node *s; + + if (psci_root_node(e)) + return e; + + p = psci_node_parent(e); + + if (p->level > level) + return e; + + for (i = 0; i < p->children.num; i++) { + s = &p->children.nodes[i]; + /* Don't check target. */ + if (s == e) + continue; + if (psci_state_locked(s) != PSCI_STATE_OFF) + return e; + } + + e = p; + } } - return NULL; + /* All ancestors in state OFF are affected. */ + if (state == PSCI_STATE_ON_PENDING) { + while (1) { + /* At the root. Return last affected node. */ + if (psci_root_node(e)) + return e; + + p = psci_node_parent(e); + + if (p->level > level) + return e; + + /* This parent is already ON. */ + if (psci_state_locked(p) != PSCI_STATE_OFF) + return e; + + e = p; + } + } + + /* Default to returning node passed in. */ + return e; +} + +static void psci_set_hierarchy_state(struct psci_node *from, + struct psci_node *to, + int state) +{ + struct psci_node *end; + + end = psci_node_parent(to); + + while (from != end) { + /* Raced with another CPU as state is already set. */ + if (psci_state_locked(from) == state) + break; + psci_set_state_locked(from, state); + from = psci_node_parent(from); + } } static void psci_cpu_on_callback(void *arg) { - struct psci_cpu_state *s = arg; + struct exc_state state; + int target_el; + struct psci_node *e = arg; - psci_turn_on_self(s->entry, s->arg); + psci_lock(); + psci_set_hierarchy_state(e, e->cpu_state.ancestor, PSCI_STATE_ON); + psci_unlock(); + + /* Target EL is determined if HVC is enabled or not. */ + target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1; + + memset(&state, 0, sizeof(state)); + state.elx.spsr = get_eret_el(target_el, SPSR_USE_H); + transition_with_entry(e->cpu_state.entry, e->cpu_state.arg, &state); +} + +static void psci_cpu_on_prepare(struct psci_node *e, + void *entry, void *arg) +{ + struct psci_node *ancestor; + int state = PSCI_STATE_ON_PENDING; + + e->cpu_state.entry = entry; + e->cpu_state.arg = arg; + ancestor = psci_find_ancestor(e, PSCI_AFFINITY_LEVEL_HIGHEST, state); + e->cpu_state.ancestor = ancestor; + psci_set_hierarchy_state(e, ancestor, state); +} + +static int psci_schedule_cpu_on(struct psci_node *e) +{ + struct cpu_action action = { + .run = &psci_cpu_on_callback, + .arg = e, + }; + + if (arch_run_on_cpu_async(e->cpu_state.ci->id, &action)) + return PSCI_RET_INTERNAL_FAILURE; + + return PSCI_RET_SUCCESS; +} + +void psci_turn_on_self(void *entry, void *arg) +{ + struct psci_node *e = node_self(); + + if (e == NULL) { + printk(BIOS_ERR, "Couldn't turn on self: mpidr %llx\n", + cpu_info()->mpidr); + return; + } + + psci_lock(); + psci_cpu_on_prepare(e, entry, arg); + psci_unlock(); + + psci_schedule_cpu_on(e); } static void psci_cpu_on(struct psci_func *pf) @@ -90,60 +221,68 @@ static void psci_cpu_on(struct psci_func *pf) uint64_t entry; uint64_t target_mpidr; uint64_t context_id; - struct cpu_info *ci; int cpu_state; - struct cpu_action action; + struct psci_node *e; target_mpidr = psci64_arg(pf, PSCI_PARAM_0); entry = psci64_arg(pf, PSCI_PARAM_1); context_id = psci64_arg(pf, PSCI_PARAM_2); - ci = mpidr_to_cpu_info(target_mpidr); + e = psci_node_lookup(target_mpidr, PSCI_AFFINITY_LEVEL_0); - if (ci == NULL) { + if (e == NULL) { psci32_return(pf, PSCI_RET_INVALID_PARAMETERS); return; } psci_lock(); - cpu_state = psci_cpu_state_locked(ci->id); + cpu_state = psci_state_locked(e); - if (cpu_state == PSCI_CPU_STATE_ON_PENDING) { + if (cpu_state == PSCI_STATE_ON_PENDING) { psci32_return(pf, PSCI_RET_ON_PENDING); psci_unlock(); return; - } else if (cpu_state == PSCI_CPU_STATE_ON) { + } else if (cpu_state == PSCI_STATE_ON) { psci32_return(pf, PSCI_RET_ALREADY_ON); psci_unlock(); return; } - psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON_PENDING); - /* Set the parameters and initialize the action. */ - psci_state[ci->id].entry = (void *)(uintptr_t)entry; - psci_state[ci->id].arg = (void *)(uintptr_t)context_id; - action.run = &psci_cpu_on_callback; - action.arg = &psci_state[ci->id]; - - if (arch_run_on_cpu_async(ci->id, &action)) { - psci32_return(pf, PSCI_RET_INTERNAL_FAILURE); - psci_unlock(); - return; - } - + psci_cpu_on_prepare(e, (void *)entry, (void *)context_id); psci_unlock(); - psci32_return(pf, PSCI_RET_SUCCESS); + psci32_return(pf, psci_schedule_cpu_on(e)); } -static void psci_cpu_off(struct psci_func *pf) +static int psci_turn_off_node(struct psci_node *e, int level, + int state_id) { + struct psci_node *ancestor; + psci_lock(); - psci_cpu_set_state_locked(cpu_info()->id, PSCI_CPU_STATE_OFF); + ancestor = psci_find_ancestor(e, level, PSCI_STATE_OFF); + psci_set_hierarchy_state(e, ancestor, PSCI_STATE_OFF); psci_unlock(); /* TODO(adurbin): writeback cache and actually turn off CPU. */ secmon_trampoline(&secmon_wait_for_action, NULL); + + return PSCI_RET_SUCCESS; +} + +int psci_turn_off_self(void) +{ + struct psci_node *e = node_self(); + + if (e == NULL) { + printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n", + cpu_info()->mpidr); + return PSCI_RET_INTERNAL_FAILURE; + } + + /* -1 state id indicates to SoC to make its own decision for + * internal state when powering off the node. */ + return psci_turn_off_node(e, PSCI_AFFINITY_LEVEL_HIGHEST, -1); } static int psci_handler(struct smc_call *smc) @@ -158,7 +297,7 @@ static int psci_handler(struct smc_call *smc) psci_cpu_on(pf); break; case PSCI_CPU_OFF64: - psci_cpu_off(pf); + psci32_return(pf, psci_turn_off_self()); break; default: psci32_return(pf, PSCI_RET_NOT_SUPPORTED); @@ -168,41 +307,190 @@ static int psci_handler(struct smc_call *smc) return 0; } -void psci_init(void) +static void psci_link_cpu_info(void *arg) { - struct cpu_info *ci; + struct psci_node *e = node_self(); + + if (e == NULL) { + printk(BIOS_ERR, "No PSCI node for MPIDR %llx.\n", + cpu_info()->mpidr); + return; + } + + e->cpu_state.ci = cpu_info(); +} + +static int psci_init_node(struct psci_node *e, + struct psci_node *parent, + int level, uint64_t mpidr) +{ + size_t i; + uint64_t mpidr_inc; + struct psci_node_group *ng; + size_t num_children; + + memset(e, 0, sizeof(*e)); + e->mpidr = mpidr; + psci_set_state_locked(e, PSCI_STATE_OFF); + e->parent = parent; + e->level = level; + + if (level == PSCI_AFFINITY_LEVEL_0) + return 0; + + num_children = soc_psci_ops.children_at_level(level, mpidr); + + if (num_children == 0) + return 0; + + ng = &e->children; + ng->num = num_children; + ng->nodes = malloc(ng->num * sizeof(struct psci_node)); + if (ng->nodes == NULL) { + printk(BIOS_DEBUG, "PSCI: Allocation failure at level %d\n", + level); + return -1; + } + + /* Switch to next level below. */ + level = psci_level_below(level); + mpidr_inc = mpidr_mask(!!(level == PSCI_AFFINITY_LEVEL_3), + !!(level == PSCI_AFFINITY_LEVEL_2), + !!(level == PSCI_AFFINITY_LEVEL_1), + !!(level == PSCI_AFFINITY_LEVEL_0)); + + for (i = 0; i < ng->num; i++) { + struct psci_node *c = &ng->nodes[i]; + + /* Recursively initialize the nodes. */ + if (psci_init_node(c, e, level, mpidr)) + return -1; + mpidr += mpidr_inc; + } + + return 0; +} + +static size_t psci_count_children(struct psci_node *e) +{ + size_t i; + size_t count; + + if (e->level == PSCI_AFFINITY_LEVEL_0) + return 0; + + count = e->children.num; + for (i = 0; i < e->children.num; i++) + count += psci_count_children(&e->children.nodes[i]); + + return count; +} + +static size_t psci_write_nodes(struct psci_node *e, size_t index) +{ + size_t i; + + /* + * Recursively save node pointers in array. Node pointers are + * ordered in ascending mpidr and descending level within same mpidr. + * i.e. each node is saved in depth-first order of the tree. + */ + if (e->level != PSCI_AFFINITY_ROOT) { + psci_nodes[index] = e; + index++; + } + + if (e->level == PSCI_AFFINITY_LEVEL_0) + return index; + + for (i = 0; i < e->children.num; i++) + index = psci_write_nodes(&e->children.nodes[i], index); + + return index; +} + +static int psci_allocate_nodes(void) +{ + int level; + size_t num_children; uint64_t mpidr; + struct psci_node *e; - /* Set this CPUs MPIDR clearing the bits that are not per-cpu. */ - ci = cpu_info(); - mpidr = raw_read_mpidr_el1(); - mpidr &= ~(1ULL << 31); /* RES1 */ - mpidr &= ~(1ULL << 30); /* U */ - mpidr &= ~(1ULL << 24); /* MT */ - psci_state[ci->id].mpidr = mpidr; + mpidr = 0; + level = PSCI_AFFINITY_ROOT; - if (!cpu_is_bsp()) - return; + /* Find where the root should start. */ + while (psci_level_below(level) >= PSCI_AFFINITY_LEVEL_0) { + num_children = soc_psci_ops.children_at_level(level, mpidr); - /* Register PSCI handlers. */ - if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler)) - printk(BIOS_ERR, "Couldn't register PSCI handler.\n"); + if (num_children == 0) { + printk(BIOS_ERR, "PSCI: No children at level %d!\n", + level); + return -1; + } + + /* The root starts where the affinity levels branch. */ + if (num_children > 1) + break; + + level = psci_level_below(level); + } + + if (psci_init_node(&psci_root, NULL, level, mpidr)) { + printk(BIOS_ERR, "PSCI init node failure.\n"); + return -1; + } + + num_children = psci_count_children(&psci_root); + /* Count the root node if isn't a fake node. */ + if (psci_root.level != PSCI_AFFINITY_ROOT) + num_children++; + + psci_nodes = malloc(num_children * sizeof(void *)); + psci_num_nodes = num_children; + + if (psci_nodes == NULL) { + printk(BIOS_ERR, "PSCI node pointer array failure.\n"); + return -1; + } + + num_children = psci_write_nodes(&psci_root, 0); + if (num_children != psci_num_nodes) { + printk(BIOS_ERR, "Wrong nodes written: %zd vs %zd.\n", + num_children, psci_num_nodes); + return -1; + } + + /* + * By default all nodes are set to PSCI_STATE_OFF. In order not + * to race with other CPUs turning themselves off set the BSPs + * affinity node to ON. + */ + e = node_self(); + if (e == NULL) { + printk(BIOS_ERR, "No PSCI node for BSP.\n"); + return -1; + } + psci_set_state_locked(e, PSCI_STATE_ON); + + return 0; } -void psci_turn_on_self(void *entry, void *arg) +void psci_init(void) { - struct exc_state state; - int target_el; - struct cpu_info *ci = cpu_info(); + struct cpu_action action = { + .run = &psci_link_cpu_info, + }; - psci_lock(); - psci_cpu_set_state_locked(ci->id, PSCI_CPU_STATE_ON); - psci_unlock(); + if (psci_allocate_nodes()) { + printk(BIOS_ERR, "PSCI support not enabled.\n"); + return; + } - /* Target EL is determined if HVC is enabled or not. */ - target_el = (raw_read_scr_el3() & SCR_HVC_ENABLE) ? EL2 : EL1; + if (arch_run_on_all_cpus_async(&action)) + printk(BIOS_ERR, "Error linking cpu_info to PSCI nodes.\n"); - memset(&state, 0, sizeof(state)); - state.elx.spsr = get_eret_el(target_el, SPSR_USE_H); - transition_with_entry(entry, arg, &state); + /* Register PSCI handlers. */ + if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler)) + printk(BIOS_ERR, "Couldn't register PSCI handler.\n"); } diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c index 56ed4f1..9097a08 100644 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ b/src/arch/arm64/armv8/secmon/secmon_init.c @@ -30,6 +30,18 @@ #include <stddef.h> #include "secmon.h" +/* Save initial secmon params per CPU to handle turn up. */ +static struct secmon_params *init_params[CONFIG_MAX_CPUS]; + +static void start_up_cpu(void *arg) +{ + struct secmon_params *params = init_params[cpu_info()->id]; + + if (params == NULL) + psci_turn_off_self(); + psci_turn_on_self(params->entry, params->arg); +} + static void cpu_init(int bsp) { struct cpu_info *ci = cpu_info(); @@ -43,17 +55,26 @@ static void cpu_init(int bsp) static void secmon_init(struct secmon_params *params, int bsp) { + struct cpu_action action = { + .run = start_up_cpu, + }; + exception_hwinit(); cpu_init(bsp); + init_params[cpu_info()->id] = params; + + if (!cpu_is_bsp()) + secmon_wait_for_action(); + smc_init(); psci_init(); - /* Turn on CPU if params are not NULL. */ - if (params != NULL) - psci_turn_on_self(params->entry, params->arg); + arch_run_on_all_cpus_async(&action); - secmon_wait_for_action(); + printk(BIOS_ERR, "CPU turn on failed for BSP.\n"); + while (1) + ; } void secmon_wait_for_action(void) diff --git a/src/arch/arm64/armv8/secmon/smc.c b/src/arch/arm64/armv8/secmon/smc.c index 8aa6d41..ae0f130 100644 --- a/src/arch/arm64/armv8/secmon/smc.c +++ b/src/arch/arm64/armv8/secmon/smc.c @@ -140,7 +140,7 @@ static struct exception_handler smc_handler32 = { .handler = &smc_handler, }; -void smc_init(void) +static void enable_smc(void *arg) { uint32_t scr; @@ -149,9 +149,15 @@ void smc_init(void) scr &= ~(SCR_SMC_MASK); scr |= SCR_SMC_ENABLE; raw_write_scr_el3(scr); +} + +void smc_init(void) +{ + struct cpu_action action = { + .run = enable_smc, + }; - if (!cpu_is_bsp()) - return; + arch_run_on_all_cpus_async(&action); /* Register SMC handlers. */ exception_handler_register(EXC_VID_LOW64_SYNC, &smc_handler64); diff --git a/src/arch/arm64/include/arch/psci.h b/src/arch/arm64/include/arch/psci.h index c39f13a..afa4c42 100644 --- a/src/arch/arm64/include/arch/psci.h +++ b/src/arch/arm64/include/arch/psci.h @@ -20,6 +20,8 @@ #ifndef __ARCH_PSCI_H__ #define __ARCH_PSCI_H__ +#include <stdint.h> +#include <arch/cpu.h> #include <arch/smc.h> /* Return Values */ @@ -35,6 +37,85 @@ enum { PSCI_RET_DISABLED = -8, }; +/* Generic PSCI state. */ +enum { + PSCI_STATE_OFF = 0, + PSCI_STATE_ON_PENDING, + PSCI_STATE_ON, +}; + +/* Affinity level support. */ +enum { + PSCI_AFFINITY_LEVEL_0, + PSCI_AFFINITY_LEVEL_1, + PSCI_AFFINITY_LEVEL_2, + PSCI_AFFINITY_LEVEL_3, + PSCI_AFFINITY_ROOT, + PSCI_AFFINITY_LEVEL_HIGHEST = PSCI_AFFINITY_ROOT, +}; + +static inline int psci_level_below(int level) +{ + return level - 1; +} + +struct psci_node; + +struct psci_cpu_state { + struct cpu_info *ci; + void *entry; + void *arg; + /* Ancestor of target to update state in CPU_ON case. */ + struct psci_node *ancestor; +}; + +struct psci_node_group { + size_t num; + struct psci_node *nodes; +}; + +struct psci_node { + uint64_t mpidr; + /* Affinity level of node. */ + int level; + /* Generic power state of this entity. */ + int state; + /* The SoC can stash its own state accounting in here. */ + int soc_state; + /* Parent of curernt entity. */ + struct psci_node *parent; + /* + * CPUs are leaves in the tree. They don't have children. The + * CPU-specific bits of storage can be shared with the children + * storage. + */ + union { + struct psci_node_group children; + struct psci_cpu_state cpu_state; + }; +}; + +static inline struct psci_node *psci_node_parent(const struct psci_node *n) +{ + return n->parent; +} + +static inline int psci_root_node(const struct psci_node *n) +{ + return psci_node_parent(n) == NULL; +} + +struct psci_soc_ops { + /* + * Return number of entities one level below given parent affinitly + * level and mpidr. + */ + size_t (*children_at_level)(int parent_level, uint64_t mpidr); +}; + +/* Each SoC needs to provide the functions in the psci_soc_ops structure. */ +extern struct psci_soc_ops soc_psci_ops; + /* PSCI Functions. */ enum { /* 32-bit System level functions. */ @@ -111,5 +192,6 @@ void psci_init(void); /* Turn on the current CPU within the PSCI subsystem. */ void psci_turn_on_self(void *entry, void *arg); +int psci_turn_off_self(void); #endif /* __ARCH_PSCI_H__ */ diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 81d08f5..af4456d 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -77,6 +77,7 @@ ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu_lib.S +secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += psci.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += uart.c modules_arm-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c new file mode 100644 index 0000000..b039dfb --- /dev/null +++ b/src/soc/nvidia/tegra132/psci.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/psci.h> + +static size_t children_at_level(int parent_level, uint64_t mpidr) +{ + if (mpidr != 0) + return 0; + + /* T132 just has 2 cores. 0. Level 1 has 2 children at level 0. */ + switch (parent_level) { + case PSCI_AFFINITY_ROOT: + return 1; + case PSCI_AFFINITY_LEVEL_3: + return 1; + case PSCI_AFFINITY_LEVEL_2: + return 1; + case PSCI_AFFINITY_LEVEL_1: + return 2; + case PSCI_AFFINITY_LEVEL_0: + return 0; + default: + return 0; + } +} + +struct psci_soc_ops soc_psci_ops = { + .children_at_level = &children_at_level, +};

1 0

New patch to review for coreboot: ed00754 arm64: add malloc support to secmon
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9389 -gerrit commit ed00754641b4fee43c9aec49394b0e42cf7e19ac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 28 17:23:17 2014 -0500 arm64: add malloc support to secmon In order to dynamically allocate structures based on affinity levels add malloc() support. BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted to kernel. Change-Id: I40cbd8497a1599db12b9e87eeb379f7dcd21c9b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9cd2b23c2ea045b5832b3d838e29f4b6a1b6cdfb Original-Change-Id: Ie1412a3a9eb07689059a2cd69bd111274bcb88fa Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226482 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Makefile.inc | 1 + src/arch/arm64/armv8/secmon/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 0b3e32e..bb3cab5 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -157,6 +157,7 @@ rmodules_arm64-y += ../../lib/memmove.c rmodules_arm64-y += eabi_compat.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += stage_entry.S +secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/malloc.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memset.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcmp.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcpy.c diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index f9ce4f6..1b774ff 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -43,7 +43,7 @@ ramstage-srcs += $(SECMON_RAMSTAGE) $(SECMON_OBJ): $$(secmon-objs) $(CC_secmon) $(LDFLAGS) -nostdlib -r -o $@ $^ -$(eval $(call rmodule_link,$(SECMON_ELF), $(SECMON_OBJ), 0,arm64)) +$(eval $(call rmodule_link,$(SECMON_ELF), $(SECMON_OBJ), 8192,arm64)) $(SECMON_BIN): $(SECMON_RMOD) $(OBJCOPY_secmon) -O binary $< $@

1 0

New patch to review for coreboot: 94fee32 arm64: add mpidr field to cpu_info struct
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9388 -gerrit commit 94fee32cf7ab50f576caf0431e086e634a72f49e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 28 17:01:28 2014 -0500 arm64: add mpidr field to cpu_info struct The cpu_info struct can be easily obtained at runtime based on smp_processor_id(). To allow easier mapping between cpu_info and PSCI entities add the mpidr info to the cpu_info struct. BUG=chrome-os-partner:32136 BRANCH=None TEST=Built and booted in SMP. Noted MPIDR messages for each cpu. Change-Id: I390392a391d953a3b144b56b42e7b81f90d5fec1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d091706f64f1fc4b1b72b1825cab82a5d3cbf23e Original-Change-Id: Ib10ee4413d467b22050edec5388c0cae57128911 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226481 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/cpu_ramstage.c | 2 ++ src/arch/arm64/include/arch/mpidr.h | 64 +++++++++++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/cpu.h | 3 ++ 3 files changed, 69 insertions(+) diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c index 0f26206..f286678 100644 --- a/src/arch/arm64/cpu_ramstage.c +++ b/src/arch/arm64/cpu_ramstage.c @@ -105,6 +105,8 @@ static void init_this_cpu(void *arg) cpu_set_device_operations(dev); + printk(BIOS_DEBUG, "CPU%x: MPIDR: %llx\n", ci->id, ci->mpidr); + el3_init(); /* Initialize the GIC. */ diff --git a/src/arch/arm64/include/arch/mpidr.h b/src/arch/arm64/include/arch/mpidr.h new file mode 100644 index 0000000..0735a6a --- /dev/null +++ b/src/arch/arm64/include/arch/mpidr.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __ARCH_MPIDR_H__ +#define __ARCH_MPIDR_H__ + +#include <stdint.h> +#include <arch/lib_helpers.h> + +enum { + MPIDR_RES1_SHIFT = 31, + MPIDR_U_SHIFT = 30, + MPIDR_MT_SHIFT = 24, + + MPIDR_AFFINITY_0_SHIFT = 0, + MPIDR_AFFINITY_1_SHIFT = 8, + MPIDR_AFFINITY_2_SHIFT = 16, + MPIDR_AFFINITY_3_SHIFT = 32, + MPIDR_AFFINITY_MASK = 0xff, +}; + +static inline uint64_t mpidr_mask(uint8_t aff3, uint8_t aff2, + uint8_t aff1, uint8_t aff0) +{ + uint64_t mpidr = 0; + + mpidr |= (uint64_t)aff3 << MPIDR_AFFINITY_3_SHIFT; + mpidr |= (uint64_t)aff2 << MPIDR_AFFINITY_2_SHIFT; + mpidr |= (uint64_t)aff1 << MPIDR_AFFINITY_1_SHIFT; + mpidr |= (uint64_t)aff0 << MPIDR_AFFINITY_0_SHIFT; + + return mpidr; +} + +static inline uint64_t read_mpidr(void) +{ + return raw_read_mpidr_el1(); +} + +static inline uint64_t read_affinity_mpidr(void) +{ + uint64_t affinity_mask; + affinity_mask = mpidr_mask(MPIDR_AFFINITY_MASK, MPIDR_AFFINITY_MASK, + MPIDR_AFFINITY_MASK, MPIDR_AFFINITY_MASK); + return read_mpidr() & affinity_mask; +} + +#endif /* __ARCH_MPIDR_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index fc31903..d4ff907 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -24,6 +24,7 @@ #if !defined(__PRE_RAM__) #include <arch/barrier.h> +#include <arch/mpidr.h> #include <device/device.h> enum { @@ -62,6 +63,7 @@ struct cpu_info { unsigned int online; /* Current assumption is that id matches smp_processor_id(). */ unsigned int id; + uint64_t mpidr; }; /* Obtain cpu_info for current executing CPU. */ @@ -93,6 +95,7 @@ static inline int cpu_online(struct cpu_info *ci) static inline void cpu_mark_online(struct cpu_info *ci) { + ci->mpidr = read_affinity_mpidr(); store_release(&ci->online, 1); }

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New patch to review for coreboot: 99be110 serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9387 -gerrit commit 99be110287dd34d4f2d0e77226d79492af2500dc Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Oct 22 14:12:50 2014 -0700 serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32 We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/Config.in | 9 +- payloads/libpayload/configs/defconfig | 3 +- payloads/libpayload/configs/defconfig-arm | 3 +- payloads/libpayload/configs/defconfig-mips | 3 +- payloads/libpayload/drivers/Makefile.inc | 3 +- payloads/libpayload/drivers/serial/8250_mmio32.c | 113 ++++++++++++++++++++++ payloads/libpayload/drivers/serial/rk_serial.c | 115 ----------------------- payloads/libpayload/drivers/serial/tegra.c | 113 ---------------------- 8 files changed, 119 insertions(+), 243 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index cb1d529..2efd5d6 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -199,13 +199,8 @@ config S5P_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n -config TEGRA_SERIAL_CONSOLE - bool "Tegra SOC compatible serial port driver" - depends on SERIAL_CONSOLE - default n - -config RK_SERIAL_CONSOLE - bool "Rockchip SOC serial port driver" +config 8250_MMIO32_SERIAL_CONSOLE + bool "Memory-mapped 8250-compatible serial port driver with 32-bit regs" depends on SERIAL_CONSOLE default n diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index f5e13d5..556b619 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -41,8 +41,7 @@ CONFIG_LP_CBMEM_CONSOLE=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_8250_SERIAL_CONSOLE=y # CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set -# CONFIG_LP_RK_SERIAL_CONSOLE is not set +# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_PL011_SERIAL_CONSOLE is not set CONFIG_LP_SERIAL_IOBASE=0x3f8 diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index ea467ec..ff2225f 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -40,8 +40,7 @@ CONFIG_LP_CBMEM_CONSOLE=y CONFIG_LP_SERIAL_CONSOLE=y # CONFIG_LP_8250_SERIAL_CONSOLE is not set # CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set -# CONFIG_LP_RK_SERIAL_CONSOLE is not set +# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_SERIAL_SET_SPEED is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips index 0af1a91..76b8474 100644 --- a/payloads/libpayload/configs/defconfig-mips +++ b/payloads/libpayload/configs/defconfig-mips @@ -40,8 +40,7 @@ CONFIG_LP_CBMEM_CONSOLE=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_8250_SERIAL_CONSOLE=y # CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set -# CONFIG_LP_RK_SERIAL_CONSOLE is not set +# CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_PL011_SERIAL_CONSOLE is not set # CONFIG_LP_SERIAL_SET_SPEED is not set diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 6dc1403..f3b147d 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -35,9 +35,8 @@ libc-$(CONFIG_LP_SPEAKER) += speaker.c libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c -libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c +libc-$(CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE) += serial/8250_mmio32.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c -libc-$(CONFIG_LP_RK_SERIAL_CONSOLE) += serial/rk_serial.c libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/serial/8250_mmio32.c b/payloads/libpayload/drivers/serial/8250_mmio32.c new file mode 100644 index 0000000..285f7f6 --- /dev/null +++ b/payloads/libpayload/drivers/serial/8250_mmio32.c @@ -0,0 +1,113 @@ +/* + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <stdint.h> + +struct mmio32_uart { + union { + uint32_t thr; // Transmit holding register. + uint32_t rbr; // Receive buffer register. + uint32_t dll; // Divisor latch lsb. + }; + union { + uint32_t ier; // Interrupt enable register. + uint32_t dlm; // Divisor latch msb. + }; + union { + uint32_t iir; // Interrupt identification register. + uint32_t fcr; // FIFO control register. + }; + uint32_t lcr; // Line control register. + uint32_t mcr; // Modem control register. + uint32_t lsr; // Line status register. + uint32_t msr; // Modem status register. +} __attribute__ ((packed)); + +enum { + LSR_DR = 0x1 << 0, // Data ready. + LSR_OE = 0x1 << 1, // Overrun. + LSR_PE = 0x1 << 2, // Parity error. + LSR_FE = 0x1 << 3, // Framing error. + LSR_BI = 0x1 << 4, // Break. + LSR_THRE = 0x1 << 5, // Xmit holding register empty. + LSR_TEMT = 0x1 << 6, // Xmitter empty. + LSR_ERR = 0x1 << 7 // Error. +}; + +static struct mmio32_uart *uart = NULL; + +void serial_putchar(unsigned int c) +{ + while (!(readl(&uart->lsr) & LSR_THRE)) + /* wait for transmit register to clear */; + + writel((char)c, &uart->thr); + if (c == '\n') + serial_putchar('\r'); +} + +int serial_havechar(void) +{ + uint8_t lsr = readl(&uart->lsr); + return (lsr & LSR_DR) == LSR_DR; +} + +int serial_getchar(void) +{ + while (!serial_havechar()) + /* wait for character */; + + return readl(&uart->rbr); +} + +static struct console_output_driver mmio32_serial_output = { + .putchar = &serial_putchar +}; + +static struct console_input_driver mmio32_serial_input = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + return; + + uart = (struct mmio32_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr; +} + +void serial_console_init(void) +{ + serial_init(); + + if (uart) { + console_add_output_driver(&mmio32_serial_output); + console_add_input_driver(&mmio32_serial_input); + } +} diff --git a/payloads/libpayload/drivers/serial/rk_serial.c b/payloads/libpayload/drivers/serial/rk_serial.c deleted file mode 100644 index 91a6e1b..0000000 --- a/payloads/libpayload/drivers/serial/rk_serial.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Rockchip Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <libpayload-config.h> -#include <libpayload.h> -struct rk_uart { - union { - u32 uart_thr; /* Transmit holding register. */ - u32 uart_rbr; /* Receive buffer register. */ - u32 uart_dll; /* Divisor latch lsb. */ - }; - union { - u32 uart_ier; /* Interrupt enable register. */ - u32 uart_dlh; /* Divisor latch msb. */ - }; - union { - uint32_t uart_iir; /* Interrupt identification register. */ - uint32_t uart_fcr; /* FIFO control register. */ - }; - u32 uart_lcr; - u32 uart_mcr; - u32 uart_lsr; - u32 uart_msr; - u32 uart_scr; - u32 reserved1[(0x30 - 0x20) / 4]; - u32 uart_srbr[(0x70 - 0x30) / 4]; - u32 uart_far; - u32 uart_tfr; - u32 uart_rfw; - u32 uart_usr; - u32 uart_tfl; - u32 uart_rfl; - u32 uart_srr; - u32 uart_srts; - u32 uart_sbcr; - u32 uart_sdmam; - u32 uart_sfe; - u32 uart_srt; - u32 uart_stet; - u32 uart_htx; - u32 uart_dmasa; - u32 reserver2[(0xf4 - 0xac) / 4]; - u32 uart_cpr; - u32 uart_ucv; - u32 uart_ctr; -}; -enum { - UART_LSR_DR = 0x1 << 0, /* Data ready. */ - UART_LSR_OE = 0x1 << 1, /* Overrun. */ - UART_LSR_PE = 0x1 << 2, /* Parity error. */ - UART_LSR_FE = 0x1 << 3, /* Framing error. */ - UART_LSR_BI = 0x1 << 4, /* Break. */ - UART_LSR_THRE = 0x1 << 5, /* Xmit holding register empty. */ - UART_LSR_TEMT = 0x1 << 6, /* Xmitter empty. */ - UART_LSR_ERR = 0x1 << 7 /* Error. */ -}; - -static struct rk_uart *uart_regs; -void serial_putchar(unsigned int c) -{ - while (!(readl(&uart_regs->uart_lsr) & UART_LSR_THRE)); - writel((c & 0xff), &uart_regs->uart_thr); - if (c == '\n') - serial_putchar('\r'); -} - -int serial_havechar(void) -{ - uint8_t lsr = readl(&uart_regs->uart_lsr); - return (lsr & UART_LSR_DR) == UART_LSR_DR; -} - -int serial_getchar(void) -{ - while (!serial_havechar()); - return readl(&uart_regs->uart_rbr)&0xff; -} - -static struct console_input_driver consin = { - .havekey = &serial_havechar, - .getchar = &serial_getchar -}; - -static struct console_output_driver consout = {.putchar = &serial_putchar -}; - -void serial_init(void) -{ - if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) - return; - - uart_regs = (struct rk_uart *)lib_sysinfo.serial->baseaddr; -} - -void serial_console_init(void) -{ - serial_init(); - console_add_input_driver(&consin); - console_add_output_driver(&consout); -} diff --git a/payloads/libpayload/drivers/serial/tegra.c b/payloads/libpayload/drivers/serial/tegra.c deleted file mode 100644 index a3dad2b..0000000 --- a/payloads/libpayload/drivers/serial/tegra.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> -#include <stdint.h> - -struct tegra_uart { - union { - uint32_t thr; // Transmit holding register. - uint32_t rbr; // Receive buffer register. - uint32_t dll; // Divisor latch lsb. - }; - union { - uint32_t ier; // Interrupt enable register. - uint32_t dlm; // Divisor latch msb. - }; - union { - uint32_t iir; // Interrupt identification register. - uint32_t fcr; // FIFO control register. - }; - uint32_t lcr; // Line control register. - uint32_t mcr; // Modem control register. - uint32_t lsr; // Line status register. - uint32_t msr; // Modem status register. -} __attribute__ ((packed)); - -enum { - TEGRA_UART_LSR_DR = 0x1 << 0, // Data ready. - TEGRA_UART_LSR_OE = 0x1 << 1, // Overrun. - TEGRA_UART_LSR_PE = 0x1 << 2, // Parity error. - TEGRA_UART_LSR_FE = 0x1 << 3, // Framing error. - TEGRA_UART_LSR_BI = 0x1 << 4, // Break. - TEGRA_UART_LSR_THRE = 0x1 << 5, // Xmit holding register empty. - TEGRA_UART_LSR_TEMT = 0x1 << 6, // Xmitter empty. - TEGRA_UART_LSR_ERR = 0x1 << 7 // Error. -}; - -static struct tegra_uart *uart_regs; - -void serial_putchar(unsigned int c) -{ - while (!(readb(&uart_regs->lsr) & TEGRA_UART_LSR_THRE)); - writeb(c, &uart_regs->thr); - if (c == '\n') - serial_putchar('\r'); -} - -int serial_havechar(void) -{ - uint8_t lsr = readb(&uart_regs->lsr); - return (lsr & TEGRA_UART_LSR_DR) == TEGRA_UART_LSR_DR; -} - -int serial_getchar(void) -{ - while (!serial_havechar()) - {;} - - return readb(&uart_regs->rbr); -} - -static struct console_output_driver tegra_serial_output = -{ - .putchar = &serial_putchar -}; - -static struct console_input_driver tegra_serial_input = -{ - .havekey = &serial_havechar, - .getchar = &serial_getchar -}; - -void serial_init(void) -{ - if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) - return; - - uart_regs = (struct tegra_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr; -} - -void serial_console_init(void) -{ - serial_init(); - - if (uart_regs) { - console_add_output_driver(&tegra_serial_output); - console_add_input_driver(&tegra_serial_input); - } -}

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New patch to review for coreboot: d8461af armv7-m: set stack pointer to _estack
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9384 -gerrit commit d8461af6ca991889e2cf1e9249aee66dddb53fe7 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Oct 24 09:38:31 2014 -0700 armv7-m: set stack pointer to _estack this change sets the stack pointer to the value specified in memlayout.ld before jumping to the bootblock. BUG=none BRANCH=ToT TEST=Built cosmos and all other current boards. Change-Id: Ic1b790f27bce431124ba70cc2d3d3607c537564b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d50fd02db8bf10147fd808f3030e6297b9ca0aad Original-Change-Id: I4bb8cea7435d2a0e2c1ced050c3366d2e636cb8a Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225420 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/arm/armv7/bootblock_m.S | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S index 0a29a0b..2e46ca0 100644 --- a/src/arch/arm/armv7/bootblock_m.S +++ b/src/arch/arm/armv7/bootblock_m.S @@ -31,5 +31,20 @@ #include <arch/asm.h> ENTRY(_start) + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +call_bootblock: + ldr sp, =_estack /* Set up stack pointer */ bl main ENDPROC(_start)

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coreboot-gerrit April 2015