coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: a8945eb urara: bimgtool now uses CRC 16 instead of CRC x25.
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9415 -gerrit commit a8945eb83f167d8bf65cb730f5d5a1cfddbdd12a Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Oct 31 17:21:41 2014 +0000 urara: bimgtool now uses CRC 16 instead of CRC x25. Switched to CRC 16 as it's 40% faster than CRC x25. Both CRC 16 and CRC x25 are supported and either can be selected through define directives. BUG=chrome-os-partner:31438 TEST=built urara bootblock and verified content of bootblock.bin, observed expected content; ran it on Pistachio FPGA and observed that its content is read properly by bootrom. BRANCH=none Change-Id: I36dec6ec2d6616343f97cc8b6486c0a3e4ea49ba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6d9318097ca9270bc245e7de4aff5f78dfbc1606 Original-Change-Id: If1a78350e0b48d91bfe64ead45f852f44ba3cf9a Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226840 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/bimgtool/bimgtool.c | 98 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 90 insertions(+), 8 deletions(-) diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c index 72de6db..c8ab9bb 100644 --- a/util/bimgtool/bimgtool.c +++ b/util/bimgtool/bimgtool.c @@ -40,9 +40,18 @@ struct bimg_header { struct bimg_data_header { uint32_t size; uint32_t dest_addr; + uint16_t dummy; uint16_t crc; } __attribute__((packed)); +struct crc_t { + uint16_t (*crc_f)(uint16_t crc, void *void_buf, size_t size); + uint32_t crc_init; + uint16_t ver_major; + uint16_t ver_minor; +}; + + #define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ #define BIMG_OP_MASK (0xf << 0) @@ -52,7 +61,7 @@ struct bimg_data_header { #define MAX_RECORD_BYTES 0x8000 -#define CRC_INIT 0xffff +#define CRC_16 #define error(msg...) fprintf(stderr, "ERROR: " msg) @@ -80,6 +89,72 @@ static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) return crc; } +static uint16_t crc_16(uint16_t crc, void *void_buf, size_t size) +{ + /* + * CRC table for the CRC-16. + * The poly is 0x8005 (x^16 + x^15 + x^2 + 1) + */ + static const uint16_t crc16_table[256] = { + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 + }; + uint8_t *buf, data; + + for (buf = void_buf; size; size--) { + data = *buf++; + crc = (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff]; + } + + return crc; + +} + + +static struct crc_t crc_type = { +#if defined(CRC_16) + .crc_f = crc_16, + .crc_init = 0, + .ver_major = 2, + .ver_minor = 0 +#elif defined(CRC_X25) + .crc_f = crc_x25, + .crc_init = 0xffff, + .ver_major = 1, + .ver_minor = 0 +#endif +}; + static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) { static uint8_t file_buf[MAX_RECORD_BYTES]; @@ -88,8 +163,13 @@ static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) data_hdr.dest_addr = hdr->entry_addr; + /* + * The read binary data has to be split in chunks of max 64KB-1 bytes + * (SPI controller limitation). Each chunk will have its own header in + * order to respect the BIMG format. + */ while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { - data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, sizeof(data_hdr) - sizeof(data_hdr.crc)); if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) @@ -103,7 +183,8 @@ static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) data_hdr.dest_addr += n_written; hdr->data_size += sizeof(data_hdr) + n_written; - hdr->data_crc = crc_x25(hdr->data_crc, file_buf, n_written); + hdr->data_crc = crc_type.crc_f(hdr->data_crc, + file_buf, n_written); } if (ferror(in)) @@ -119,7 +200,7 @@ static int write_final(FILE *out, struct bimg_header *hdr) .dest_addr = ~0, }; - data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, sizeof(data_hdr) - sizeof(data_hdr.crc)); if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) @@ -153,10 +234,10 @@ int main(int argc, char *argv[]) int err; struct bimg_header hdr = { .magic = BIMG_MAGIC, - .ver_major = 1, - .ver_minor = 0, + .ver_major = crc_type.ver_major, + .ver_minor = crc_type.ver_minor, .flags = BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM, - .data_crc = CRC_INIT, + .data_crc = crc_type.crc_init, }; if (argc != 4) { @@ -197,7 +278,8 @@ int main(int argc, char *argv[]) goto out_err_close_out; } - hdr.crc = crc_x25(CRC_INIT, &hdr, sizeof(hdr) - sizeof(hdr.crc)); + hdr.crc = crc_type.crc_f(crc_type.crc_init, &hdr, + sizeof(hdr) - sizeof(hdr.crc)); if (fseek(out_file, 0, SEEK_SET)) { error("Failed to seek to header: %d\n", errno);

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New patch to review for coreboot: 4e53bcb gpio: compile gpio.c at all stages
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9414 -gerrit commit 4e53bcb45dbf8abcaa14acc0324e64c91867bd82 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:22:10 2014 -0800 gpio: compile gpio.c at all stages Since gpio.c is more generic now and will be used in various stages (ie for board_id()), compile it for all stages. BUG=none BRANCH=none TEST=compiled for peppy and veyron_pinky Change-Id: Ib5c73f68db92791dd6b42369f681f9159b7e1c22 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ef4e40ccf6510d63c4a54451bdfea8da695e387e Original-Change-Id: I77ec56a77e75e602e8b9406524d36a8f69ce9128 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228325 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index bcec089..d883760 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c @@ -34,6 +35,7 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c verstage-y += tlcl.c verstage-$(CONFIG_GENERIC_UDELAY) += timer.c +verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += prog_ops.c romstage-y += memchr.c @@ -49,6 +51,7 @@ romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c +romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

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New patch to review for coreboot: efdb47f gpio: decouple tristate gpio support from board ID
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9413 -gerrit commit efdb47fbdaf561342cb4b8f0e0ac996bd0d48224 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Nov 5 14:05:56 2014 -0800 gpio: decouple tristate gpio support from board ID This deprecates TERTIARY_BOARD_ID. Instead, a board will set BOARD_ID_SUPPORT (the ones affected already do) which will set GENERIC_GPIO_SUPPORT and compile the generic GPIO library. The user is expected to handle the details of how the ID is encoded. BUG=none BRANCH=none TEST=Compiled for peppy, nyan*, storm, and pinky Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228322 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/Kconfig | 17 +++++++++-------- src/lib/Makefile.inc | 2 +- src/mainboard/google/nyan_big/Kconfig | 1 - src/mainboard/google/nyan_blaze/Kconfig | 1 - src/mainboard/google/rush_ryu/Kconfig | 1 - src/mainboard/google/storm/Kconfig | 1 - 6 files changed, 10 insertions(+), 13 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cc87aec..60c3e7c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1107,22 +1107,23 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config GENERIC_GPIO_LIB + bool "Build generic GPIO library" + default n + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + config BOARD_ID_SUPPORT bool "Discover board ID and store it in coreboot table" default n + select GENERIC_GPIO_LIB help If enabled, coreboot discovers the board id of the hardware it is running on and reports it through the coreboot table to the rest of the system. -config TERTIARY_BOARD_ID - bool "Interpret board ID GPIOs as tertiary inputs" - default n - depends on BOARD_ID_SUPPORT - help - Consider each GPIO as being in one of three states: pulled down (0), - pulled up (1), or not connected (2) - endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f0f73f2..bcec089 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -88,7 +88,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c +ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 7334472..22958a9 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH - select TERTIARY_BOARD_ID config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 3495919..0902b4f 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B - select TERTIARY_BOARD_ID select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 6fb21fb..b1f4f32 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_4096 select VIRTUAL_DEV_SWITCH - select TERTIARY_BOARD_ID select ARCH_SPINTABLE config MAINBOARD_DIR diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3e1e016..5e010fc 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_BOOTBLOCK_INIT select SPI_FLASH select SPI_FLASH_SPANSION - select TERTIARY_BOARD_ID config BOARD_VARIANT_AP148 bool "pick this to build an image for ap148"

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New patch to review for coreboot: 6a1a0c7 gpio: add a function to read GPIO array as base-2 value
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9412 -gerrit commit 6a1a0c78fa762b1a81d3378f96d7af61c93b745e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:05:35 2014 -0800 gpio: add a function to read GPIO array as base-2 value This adds gpio_base2_value() which reads an array of 2-state GPIOs and returns a base-2 value, where gpio[0] represents the least significant bit. BUG=none BRANCH=none TEST=tested with follow-up patches for pinky Change-Id: I0d6bfac369da0d68079a38de0988c7b59d269a97 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 27873b7a9ea237d13f0cbafd10033a8d0f821cbe Original-Change-Id: Ia7ffc16eb60e93413c0812573b9cf0999b92828e Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228323 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/gpio.h | 9 +++++++++ src/lib/gpio.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h index e54b156..7b64ebf 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -36,6 +36,15 @@ void gpio_output(gpio_t gpio, int value); /* * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a base-2 digit (LOW = 0, HIGH = 1). + * + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. + * num_gpio: number of pins to read. + */ +int gpio_base2_value(gpio_t gpio[], int num_gpio); + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5 * BASE3() from <base3.h> can generate numbers to compare the result to. diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 3a646e0..0875538 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -22,6 +22,18 @@ #include <delay.h> #include <gpio.h> +int gpio_base2_value(gpio_t gpio[], int num_gpio) +{ + int i, result = 0; + + for (i = 0; i < num_gpio; i++) { + gpio_input(gpio[i]); + result |= gpio_get(gpio[i]) << i; + } + + return result; +} + int gpio_base3_value(gpio_t gpio[], int num_gpio) { /*

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New patch to review for coreboot: 091897f gpio: cosmetic changes to tristate_gpios.c
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9411 -gerrit commit 091897f664a3e55cb9e264c50fc28c6198675490 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:09:27 2014 -0800 gpio: cosmetic changes to tristate_gpios.c This patch makes a few cosmetic changes: - Rename tristate_gpios.c to gpio.c since it will soon be used for binary GPIOs as well. - Rename gpio_get_tristates() to gpio_base3_value() - The binary version will be called gpio_base2_value(). - Updates call sites. - Change the variable name "id" to something more generic. BUG=none BRANCH=none TEST=compiled for veyron_pinky and storm Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228324 --- src/include/gpio.h | 4 +- src/lib/Makefile.inc | 2 +- src/lib/gpio.c | 82 +++++++++++++++++++++++++++++++ src/lib/tristate_gpios.c | 82 ------------------------------- src/mainboard/google/nyan_big/boardid.c | 2 +- src/mainboard/google/nyan_blaze/boardid.c | 2 +- src/mainboard/google/rush_ryu/boardid.c | 2 +- src/mainboard/google/storm/boardid.c | 6 +-- 8 files changed, 91 insertions(+), 91 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h index b2a341d..e54b156 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -37,12 +37,12 @@ void gpio_output(gpio_t gpio, int value); /* * Read the value presented by the set of GPIOs, when each pin is interpreted * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). - * Example: X1 = Z, X2 = 1 -> gpio_get_tristates({GPIO(X1), GPIO(X2)}) = 5 + * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5 * BASE3() from <base3.h> can generate numbers to compare the result to. * * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -int gpio_get_tristates(gpio_t gpio[], int num_gpio); +int gpio_base3_value(gpio_t gpio[], int num_gpio); #endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e01d347..f0f73f2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -88,7 +88,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c +ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/lib/gpio.c b/src/lib/gpio.c new file mode 100644 index 0000000..3a646e0 --- /dev/null +++ b/src/lib/gpio.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <base3.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +int gpio_base3_value(gpio_t gpio[], int num_gpio) +{ + /* + * GPIOs which are tied to stronger external pull up or pull down + * will stay there regardless of the internal pull up or pull + * down setting. + * + * GPIOs which are floating will go to whatever level they're + * internally pulled to. + */ + + static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; + int temp; + int index; + int result = 0; + char value[num_gpio]; + + /* Enable internal pull up */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pullup(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* Get gpio values at internal pull up */ + for (index = 0; index < num_gpio; ++index) + value[index] = gpio_get(gpio[index]); + + /* Enable internal pull down */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pulldown(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* + * Get gpio values at internal pull down. + * Compare with gpio pull up value and then + * determine a gpio final value/state: + * 0: pull down + * 1: pull up + * 2: floating + */ + printk(BIOS_DEBUG, "Reading tristate GPIOs: "); + for (index = num_gpio - 1; index >= 0; --index) { + temp = gpio_get(gpio[index]); + temp |= ((value[index] ^ temp) << 1); + printk(BIOS_DEBUG, "%c ", tristate_char[temp]); + result = (result * 3) + temp; + } + printk(BIOS_DEBUG, "= %d\n", result); + + /* Disable pull up / pull down to conserve power */ + for (index = 0; index < num_gpio; ++index) + gpio_input(gpio[index]); + + return result; +} diff --git a/src/lib/tristate_gpios.c b/src/lib/tristate_gpios.c deleted file mode 100644 index 0967a8f..0000000 --- a/src/lib/tristate_gpios.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <base3.h> -#include <console/console.h> -#include <delay.h> -#include <gpio.h> - -int gpio_get_tristates(gpio_t gpio[], int num_gpio) -{ - /* - * GPIOs which are tied to stronger external pull up or pull down - * will stay there regardless of the internal pull up or pull - * down setting. - * - * GPIOs which are floating will go to whatever level they're - * internally pulled to. - */ - - static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; - int temp; - int index; - int id = 0; - char value[num_gpio]; - - /* Enable internal pull up */ - for (index = 0; index < num_gpio; ++index) - gpio_input_pullup(gpio[index]); - - /* Wait until signals become stable */ - udelay(10); - - /* Get gpio values at internal pull up */ - for (index = 0; index < num_gpio; ++index) - value[index] = gpio_get(gpio[index]); - - /* Enable internal pull down */ - for (index = 0; index < num_gpio; ++index) - gpio_input_pulldown(gpio[index]); - - /* Wait until signals become stable */ - udelay(10); - - /* - * Get gpio values at internal pull down. - * Compare with gpio pull up value and then - * determine a gpio final value/state: - * 0: pull down - * 1: pull up - * 2: floating - */ - printk(BIOS_DEBUG, "Reading tristate GPIOs: "); - for (index = num_gpio - 1; index >= 0; --index) { - temp = gpio_get(gpio[index]); - temp |= ((value[index] ^ temp) << 1); - printk(BIOS_DEBUG, "%c ", tristate_char[temp]); - id = (id * 3) + temp; - } - printk(BIOS_DEBUG, "= %d\n", id); - - /* Disable pull up / pull down to conserve power */ - for (index = 0; index < num_gpio; ++index) - gpio_input(gpio[index]); - - return id; -} diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index b420f5a..1905c79 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -29,7 +29,7 @@ uint8_t board_id(void) [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index b420f5a..1905c79 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -29,7 +29,7 @@ uint8_t board_id(void) [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index 37f6292..9c4d184 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -30,7 +30,7 @@ uint8_t board_id(void) if (id < 0) { gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); } return id; diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index c32567e..c4f54a5 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -25,8 +25,8 @@ /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 * and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by - * gpio_get_tristates(), whereas the other two pins are not connected - * and read as 'two'. This results in gpio_get_tristates() returning + * gpio_base3_value(), whereas the other two pins are not connected + * and read as 'two'. This results in gpio_base3_value() returning * 8 on proto0. * * Three tertitiary signals could represent 27 different values. To make @@ -45,7 +45,7 @@ static uint8_t get_board_id(void) gpio_t hw_rev_gpios[] = {[2] = 68, [1] = 30, [0] = 29}; /* 29 is LSB */ int offset = 19; - bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); + bid = gpio_base3_value(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); bid = (bid + offset) % 27; printk(BIOS_INFO, "Board ID %d\n", bid);

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New patch to review for coreboot: ff5a436 rk3288: Adjust CBFS header and ROM offsets
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9410 -gerrit commit ff5a43620150b3ed7237c2945dccec36b630bc71 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Nov 6 17:32:58 2014 -0800 rk3288: Adjust CBFS header and ROM offsets Our CBFS header offset on rk3288 was very low and overlapped with the end of the bootblock on recent Pinky builds. This can create all kinds of fun effects like BSS variables suddenly being initialized to something else than zero, in an effect that jumps somewhere else for every slightest code size change. This patch moves the CBFS header offset up a bit and the CBFS ROM offset down (because there's really no point in leaving such a large gap). This resolves our immediate booting problems, and I'll also start on a patch to add further checks somewhere that catch these overlaps in the future. BRANCH=None BUG=None TEST=Created a Pinky image from the exact same commit version as the official 6443.0.0 build, with a KERNELREVISION string of the exact same length as the builder (which for some arcane reason is different than running emerge locally, shifting the whole bootblock around with it). Confirmed that I saw the same "Not enough room for another sub-pagetable!" hang, and that this patch fixes it. Change-Id: I9e59a282b3cd0af3b0d224d64c10b7c4d312ad02 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a142cd2c51c6f51a1597c21ad513feb151e0938 Original-Change-Id: I8be5b7b7e87021cc1b3a91d336e8d233546ee188 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228326 Original-Reviewed-by: Gediminas Ramanauskas <gedis(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0865fe8..b2fd0fb 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -48,10 +48,10 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex - default 0x0008000 + default 0x0010000 config CBFS_ROM_OFFSET hex - default 0x0018000 + default 0x0010100 endif

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New patch to review for coreboot: 183c3ab rk3288: don't log LAST_TSHUT bit
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9409 -gerrit commit 183c3ab3e86a6644a206f1035148c3885c727b7b Author: huang lin <hl(a)rock-chips.com> Date: Fri Nov 7 10:56:35 2014 +0800 rk3288: don't log LAST_TSHUT bit Since the LAST_THSUT bit is uncertain value when it cold-reboot, we remove the printout about this status bit in coreboot. BUG=chrome-os-partner:33521 TEST=Boot on veyron_pinky rev2 Change-Id: I3b9791ffdffeff0721e3d86378db6255c5abc9ea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 16464d3229ad1001952ef1b50fe3e606d1583462 Original-Change-Id: I258750797e32c28f86e73a01eede005e890a6906 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228391 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/tsadc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index b7d8e9d..a2d6ec4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -88,11 +88,7 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - if (readl(&rk3288_tsadc->auto_con) & LAST_TSHUT) { - printk(BIOS_WARNING, "last shutdown/rebot was caused " - "by over-temperature hardware trigger!\n"); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); - } + setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); setbits_le32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 |

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New patch to review for coreboot: e76a6da rk3288: slowly raise to max cpu voltage to prevent overshoot
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9408 -gerrit commit e76a6daf073013d4f5b65f3d2d155bf69fab96f3 Author: huang lin <hl(a)rock-chips.com> Date: Fri Oct 31 16:40:42 2014 +0800 rk3288: slowly raise to max cpu voltage to prevent overshoot slowly raise to max cpu voltage to prevent overshoot, and in our experience,when cpu run in 1.8GHz,the vdd_cpu must up to 1.4V BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv and measure the overshoot is 1440mv Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2 Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226753 Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_pinky/bootblock.c | 13 +++++++++++-- src/soc/rockchip/rk3288/rk808.c | 1 - 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index b34199d..99719c4 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -27,16 +27,25 @@ #include <soc/rk808.h> #include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <delay.h> #include "board.h" void bootblock_mainboard_init(void) { - /* cpu frequency will up to 1.8GHz, so the buck1 must up to 1.3v */ + /* cpu frequency will up to 1.8GHz, + * in our experience the buck1 + * must up to 1.4v + */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); i2c_init(PMIC_BUS, 400*KHz); - rk808_configure_buck(PMIC_BUS, 1, 1300); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(PMIC_BUS, 1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(PMIC_BUS, 1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); /* i2c1 for tpm */ diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index aa39b8d..fea64e5 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -98,5 +98,4 @@ void rk808_configure_buck(uint8_t bus, int buck, int millivolts) } rk808_clrsetbits(bus, buck_reg, 0x3f, vsel); rk808_clrsetbits(bus, DCDC_EN, 0, 1 << (buck - 1)); - udelay(225);/* Must wait for voltage to stabilize */ }

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New patch to review for coreboot: 0aa6da3 ryu: update board id definitions
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9407 -gerrit commit 0aa6da35034ebc86d9fca662ec2a1e2b6f510586 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 5 14:10:56 2014 -0600 ryu: update board id definitions There are changes in upcoming board revs that need to take different action depending on board revision. Update the enumeration to reflect upcoming reality. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: Ib51393e04d3255bbd44e5d77a2a7903109beebf4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: de8d629678c0ae17af9f7145e04d95f43c927ee0 Original-Change-Id: I64cdeab806e7a665051f1d47bbf044413f7a1196 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227681 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/rush_ryu/gpio.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h index 2792ec3..839edc0 100644 --- a/src/mainboard/google/rush_ryu/gpio.h +++ b/src/mainboard/google/rush_ryu/gpio.h @@ -21,15 +21,27 @@ #define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ #include <gpio.h> +#include <base3.h> /* Board ID definitions. */ enum { - BOARD_ID_PROTO_0 = 0, - BOARD_ID_PROTO_1 = 1, - BOARD_ID_EVT = 2, - BOARD_ID_DVT = 3, - BOARD_ID_PVT = 4, - BOARD_ID_MP = 5, + BOARD_REV0 = BASE3(0, 0), + BOARD_REV1 = BASE3(0, 1), + BOARD_REV2 = BASE3(0, Z), + BOARD_REV3 = BASE3(1, 0), + BOARD_REV4 = BASE3(1, 1), + BOARD_REV5 = BASE3(1, Z), + BOARD_REV6 = BASE3(Z, 0), + BOARD_REV7 = BASE3(Z, 1), + BOARD_REV8 = BASE3(Z, Z), + + BOARD_ID_PROTO_0 = BOARD_REV0, + BOARD_ID_PROTO_1 = BOARD_REV1, + BOARD_ID_PROTO_3 = BOARD_REV2, + BOARD_ID_EVT = BOARD_REV3, + BOARD_ID_DVT = BOARD_REV4, + BOARD_ID_PVT = BOARD_REV5, + BOARD_ID_MP = BOARD_REV6, }; enum {

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New patch to review for coreboot: 888cb74 ryu: remove board id normalization
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9406 -gerrit commit 888cb740881a60366c44fec36bd24e97fd793f59 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 5 14:01:29 2014 -0600 ryu: remove board id normalization The gpio_get_tristates() function prints out the values observed while processing the GPIOs. Additionally, the values for the normalization were completely consecutive. Therefore, this indirection can be removed. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32 Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227680 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/rush_ryu/boardid.c | 36 ++------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index 5b4c1cd..37f6292 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -17,53 +17,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <base3.h> #include <boardid.h> #include <console/console.h> #include <stdlib.h> #include "gpio.h" -struct id_to_str { - const char *str; - int tri_state_value; - int normalized_id; -}; - -static const struct id_to_str bdid_map[] = { - { "PROTO 0", BASE3(0, 0), BOARD_ID_PROTO_0 }, - { "PROTO 1", BASE3(0, 1), BOARD_ID_PROTO_1 }, - { "EVT", BASE3(0, Z), BOARD_ID_EVT }, - { "DVT", BASE3(1, 0), BOARD_ID_DVT }, - { "PVT", BASE3(1, 1), BOARD_ID_PVT }, - { "MP", BASE3(1, Z), BOARD_ID_MP }, - { "Z0", BASE3(Z, 0), -1 }, - { "Z1", BASE3(Z, 1), -1 }, - { "ZZ", BASE3(Z, Z), -1 }, -}; - uint8_t board_id(void) { static int id = -1; if (id < 0) { - const char *idstr = "Unknown"; - int i; - int tristate_id; gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - tristate_id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); - - for (i = 0; i < ARRAY_SIZE(bdid_map); i++) { - if (tristate_id != bdid_map[i].tri_state_value) - continue; - idstr = bdid_map[i].str; - id = bdid_map[i].normalized_id; - break; - } - - printk(BIOS_SPEW, "Board ID: '%s' %d (%#x)\n", idstr, id, - tristate_id); + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); } + return id; }

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coreboot-gerrit April 2015