coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 63ac47c ryu: remove board id normalization
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9406 -gerrit commit 63ac47c5173d36d78f4aff61559dece0d4cce151 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 5 14:01:29 2014 -0600 ryu: remove board id normalization The gpio_get_tristates() function prints out the values observed while processing the GPIOs. Additionally, the values for the normalization were completely consecutive. Therefore, this indirection can be removed. BUG=chrome-os-partner:33578 BRANCH=None TEST=Built and booted. Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32 Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227680 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/rush_ryu/boardid.c | 36 ++------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index 5b4c1cd..37f6292 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -17,53 +17,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <base3.h> #include <boardid.h> #include <console/console.h> #include <stdlib.h> #include "gpio.h" -struct id_to_str { - const char *str; - int tri_state_value; - int normalized_id; -}; - -static const struct id_to_str bdid_map[] = { - { "PROTO 0", BASE3(0, 0), BOARD_ID_PROTO_0 }, - { "PROTO 1", BASE3(0, 1), BOARD_ID_PROTO_1 }, - { "EVT", BASE3(0, Z), BOARD_ID_EVT }, - { "DVT", BASE3(1, 0), BOARD_ID_DVT }, - { "PVT", BASE3(1, 1), BOARD_ID_PVT }, - { "MP", BASE3(1, Z), BOARD_ID_MP }, - { "Z0", BASE3(Z, 0), -1 }, - { "Z1", BASE3(Z, 1), -1 }, - { "ZZ", BASE3(Z, Z), -1 }, -}; - uint8_t board_id(void) { static int id = -1; if (id < 0) { - const char *idstr = "Unknown"; - int i; - int tristate_id; gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - tristate_id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); - - for (i = 0; i < ARRAY_SIZE(bdid_map); i++) { - if (tristate_id != bdid_map[i].tri_state_value) - continue; - idstr = bdid_map[i].str; - id = bdid_map[i].normalized_id; - break; - } - - printk(BIOS_SPEW, "Board ID: '%s' %d (%#x)\n", idstr, id, - tristate_id); + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); } + return id; }

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Patch set updated for coreboot: 050f988 tpm: allow 0 as valid i2c bus number
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9405 -gerrit commit 050f98888ded7c90ca80997c4c89f625297b491c Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Oct 29 11:14:53 2014 -0700 tpm: allow 0 as valid i2c bus number tpm driver uses bus=0 as indication of uninitialized tpm device. this change allows 0 as a valid i2c bus number. BUG=None BRANCH=ToT TEST=Built cosmos. Change-Id: Ie8d285abff11643cc3efc0fa30e4afcc3ca1c0d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 493077b68cf46b08f0d1ddfe57bf6064d714d537 Original-Change-Id: Iac55e88db4ef757a292270e7201d8fdd37a90b50 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226294 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/i2c/tpm/tpm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index bc36e35..dc4ab78 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -86,13 +86,14 @@ static const char * const chip_name[] = { /* Structure to store I2C TPM specific stuff */ struct tpm_inf_dev { - unsigned bus; + int bus; unsigned int addr; uint8_t buf[TPM_BUFSIZE + sizeof(uint8_t)]; // max. buffer size + addr enum i2c_chip_type chip_type; }; static struct tpm_inf_dev tpm_dev = { + .bus = -1, .addr = TPM_I2C_ADDR }; @@ -115,7 +116,7 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) int rc; int count; - if (!tpm_dev.bus) + if (tpm_dev.bus < 0) return -1; if ((tpm_dev.chip_type == SLB9635) || (tpm_dev.chip_type == UNKNOWN)) { /* slb9635 protocol should work in both cases */ @@ -186,7 +187,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, tpm_dev.buf[0] = addr; memcpy(&(tpm_dev.buf[1]), buffer, len); - if (!tpm_dev.bus) + if (tpm_dev.bus < 0) return -1; for (count = 0; count < max_count; count++) { rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,

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Patch set updated for coreboot: 5123f94 google/storm: Minor board ID changes
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9404 -gerrit commit 5123f94b3c3ea48cec036d12d0d2e639eb997ed1 Author: Dan Ehrenberg <dehrenberg(a)chromium.org> Date: Fri Oct 24 13:22:05 2014 -0700 google/storm: Minor board ID changes - Add the Whirlwind board ID to the enum - Replace comparisons of the board ID with 0 to the proto0 constant TEST=Booted Storm with this coreboot version BUG=none BRANCH=none Change-Id: I53be0b06c3444936a8bd67653e03b93bcb87e328 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7e055ef27ef1e07be09d80b2298384889214bf0d Original-Change-Id: I75c7c98732c3d4569611de54d7aa149dd3b0fb7d Original-Signed-off-by: Dan Ehrenberg <dehrenberg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225460 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 4 ++-- src/soc/qualcomm/ipq806x/include/soc/cdp.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 094eaef..32be579 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -75,7 +75,7 @@ static void setup_mmu(void) #define TPM_RESET_GPIO 22 static void setup_tpm(void) { - if (board_id() != 0) + if (board_id() != BOARD_ID_PROTO_0) return; /* Only proto0 have TPM reset connected to GPIO22 */ gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, @@ -93,7 +93,7 @@ static void setup_tpm(void) #define SW_RESET_GPIO 26 static void deassert_sw_reset(void) { - if (board_id() == 0) + if (board_id() == BOARD_ID_PROTO_0) return; /* diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index bb2151c..b705f3e 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -109,6 +109,7 @@ typedef struct { enum storm_board_id { BOARD_ID_PROTO_0 = 0, BOARD_ID_PROTO_0_2 = 1, + BOARD_ID_WHIRLWIND = 2, BOARD_ID_PROTO_0_2_NAND = 26, };

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Patch set updated for coreboot: 9374d42 chromeos: add another VPD access API
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9403 -gerrit commit 9374d4290a3ff040bad3dde51d7d85e3143a0e17 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Oct 22 17:39:24 2014 -0700 chromeos: add another VPD access API The new API allows to find VPD objects in the VPD cache. There is no need for the caller to allocate or free the per object memory. The existing API (cros_vpd_gets) now uses the new function as well. BRANCH=storm BUG=chrome-os-partner:32611 TEST=verified that MAC addresses still show up in the device tree on the booted storm device Change-Id: Id06be315981cdaa2285fc1ec61b96b62b1178a4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 99a34344448a5521cee8ad3918aefb1fde28417d Original-Change-Id: I6c0b11bb844d6235930124d642da632319142d88 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225258 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.c | 26 +++++++++++++++++++++----- src/vendorcode/google/chromeos/cros_vpd.h | 16 ++++++++++++++++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index df2b5bf..c0e4830 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -99,7 +99,7 @@ static int vpd_gets_callback(const uint8_t *key, int32_t key_len, return VPD_FAIL; } -char *cros_vpd_gets(const char *key, char *buffer, int size) +const void *cros_vpd_find(const char *key, int *size) { uint8_t *vpd_address = NULL; int32_t vpd_size = 0; @@ -121,10 +121,26 @@ char *cros_vpd_gets(const char *key, char *buffer, int size) if (!arg.matched) return NULL; - if (size < arg.value_len + 1) - size = arg.value_len + 1; - memcpy(buffer, arg.value, size - 1); - buffer[size - 1] = '\0'; + *size = arg.value_len; + return arg.value; +} + +char *cros_vpd_gets(const char *key, char *buffer, int size) +{ + const void *string_address; + int string_size; + + string_address = cros_vpd_find(key, &string_size); + + if (!string_address) + return NULL; + + if (size > (string_size + 1)) { + strcpy(buffer, string_address); + } else { + memcpy(buffer, string_address, size - 1); + buffer[size - 1] = '\0'; + } return buffer; } diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index 674dbf6..19658c2 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -18,4 +18,20 @@ */ char *cros_vpd_gets(const char *key, char *buffer, int size); +/* + * Find VPD value by key. + * + * Searches for a VPD entry in the VPD cache. If found, places the size of the + * entry into '*size' and returns the pointer to the entry data. + * + * This function presumes that VPD is cached in DRAM (which is the case in the + * current implementation) and as such returns the pointer into the cache. The + * user is not supposed to modify the data, and does not have to free the + * memory. + * + * Returns NULL if key is not found. + */ + +const void *cros_vpd_find(const char *key, int *size); + #endif /* __CROS_VPD_H__ */

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Patch set updated for coreboot: 2a66a76 storm: Initialize clock, pinmux for NAND if present on board
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9402 -gerrit commit 2a66a76f613444d700e5381d97bd27b963409e70 Author: Dan Ehrenberg <dehrenberg(a)chromium.org> Date: Thu Oct 23 17:46:39 2014 -0700 storm: Initialize clock, pinmux for NAND if present on board This patch runs basic NAND initialization code on Proto 0.2 boards which have been reworked for NAND. It makes sense to do this in coreboot for two reasons: - In general, it is reasonable for coreboot to initialize clocks and such in preparation for depthcharge's use. Waiting times can be pooled, and the initialization itself here is very fast. - There is a kernel bug which requires that the clock already be initialized before the kernel loads NAND support. Coreboot is a more sensible place to put a workaround than depthcharge because depthcharge initializes things lazily, but when booting from USB, depthcharge won't need to look at NAND. Partner bug 33270 This change involves bringing in an additional header file, ebi2.h, from uBoot. TEST=Booted a kernel from USB and verified that NAND came up without any depthcharge hacks, whereas previously a USB-booted kernel would be unable to access NAND even with the same drivers compiled in due to an initialization failure. BUG=chromium:403432 BRANCH=none Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c Original-Signed-off-by: Dan Ehrenberg <dehrenberg(a)chromium.org> Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c Original-Reviewed-on: https://chromium-review.googlesource.com/225277 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/storm/cdp.c | 28 +++++----- src/mainboard/google/storm/mainboard.c | 2 + src/soc/qualcomm/ipq806x/include/soc/cdp.h | 11 +++- src/soc/qualcomm/ipq806x/include/soc/ebi2.h | 80 +++++++++++++++++++++++++++++ 4 files changed, 107 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 78edb26..fd90689 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -3,7 +3,10 @@ #include <gpio.h> #include <soc/cdp.h> +#include <soc/ebi2.h> +#include <soc/clock.h> #include <types.h> +#include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) { @@ -204,6 +207,8 @@ void reset_cpu(ulong addr) for(;;); } +#endif + static void configure_nand_gpio(void) { /* EBI2 CS, CLE, ALE, WE, OE */ @@ -230,25 +235,22 @@ static void configure_nand_gpio(void) void board_nand_init(void) { struct ebi2cr_regs *ebi2_regs; - extern int ipq_spi_init(void); - if (gboard_param->flashdesc != NOR_MMC) { + if (board_id() != BOARD_ID_PROTO_0_2_NAND) + return; - ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE; + ebi2_regs = (struct ebi2cr_regs *) EBI2CR_BASE; - nand_clock_config(); - configure_nand_gpio(); + nand_clock_config(); + configure_nand_gpio(); - /* NAND Flash is connected to CS0 */ - clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, - CS0_CFG_SERIAL_FLASH_DEVICE); - - ipq_nand_init(IPQ_NAND_LAYOUT_LINUX); - } - - ipq_spi_init(); + /* NAND Flash is connected to CS0 */ + clrsetbits_le32(&ebi2_regs->chip_select_cfg0, CS0_CFG_MASK, + CS0_CFG_SERIAL_FLASH_DEVICE); } +#if 0 + void ipq_get_part_details(void) { int ret, i; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 59e7ce7..094eaef 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -114,6 +114,8 @@ static void mainboard_init(device_t dev) setup_usb(); deassert_sw_reset(); setup_tpm(); + /* Functionally a 0-cost no-op if NAND is not present */ + board_nand_init(); } static void mainboard_enable(device_t dev) diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h index c7de23f..bb2151c 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -106,6 +106,12 @@ typedef struct { #define IPQ_GMAC_NMACS 4 +enum storm_board_id { + BOARD_ID_PROTO_0 = 0, + BOARD_ID_PROTO_0_2 = 1, + BOARD_ID_PROTO_0_2_NAND = 26, +}; + /* Board specific parameters */ typedef struct { #if 0 @@ -136,4 +142,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) unsigned int get_board_index(unsigned machid); void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); -#endif + +void board_nand_init(void); + +#endif /* _IPQ806X_CDP_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h new file mode 100644 index 0000000..23333c2 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ +#ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ +#define __SOC_QUALCOMM_IPQ806X_EBI2_H_ + +#define EBI2CR_BASE (0x1A600000) + +struct ebi2cr_regs { + uint32_t chip_select_cfg0; /* 0x00000000 */ + uint32_t cfg; /* 0x00000004 */ + uint32_t hw_info; /* 0x00000008 */ + uint8_t reserved0[20]; + uint32_t lcd_cfg0; /* 0x00000020 */ + uint32_t lcd_cfg1; /* 0x00000024 */ + uint8_t reserved1[8]; + uint32_t arbiter_cfg; /* 0x00000030 */ + uint8_t reserved2[28]; + uint32_t debug_sel; /* 0x00000050 */ + uint32_t crc_cfg; /* 0x00000054 */ + uint32_t crc_reminder_cfg; /* 0x00000058 */ + uint32_t nand_adm_mux; /* 0x0000005C */ + uint32_t mutex_addr_offset; /* 0x00000060 */ + uint32_t misr_value; /* 0x00000064 */ + uint32_t clkon_cfg; /* 0x00000068 */ + uint32_t core_clkon_cfg; /* 0x0000006C */ +}; + +/* Register: EBI2_CHIP_SELECT_CFG0 */ +#define CS7_CFG_MASK 0x00001000 +#define CS7_CFG_DISABLE 0x00000000 +#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000 +#define CS7_CFG(i) ((i) << 12) + +#define CS6_CFG_MASK 0x00000800 +#define CS6_CFG_DISABLE 0x00000000 +#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800 +#define CS6_CFG(i) ((i) << 11) + +#define ETM_CS_CFG_MASK 0x00000400 +#define ETM_CS_CFG_DISABLE 0x00000000 +#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400 +#define ETM_CS_CFG(i) ((i) << 10) + +#define CS5_CFG_MASK 0x00000300 +#define CS5_CFG_DISABLE 0x00000000 +#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100 +#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200 +#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300 +#define CS5_CFG(i) ((i) << 8) + +#define CS4_CFG_MASK 0x000000c0 +#define CS4_CFG_DISABLE 0x00000000 +#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040 +#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0 +#define CS4_CFG(i) ((i) << 6) + +#define CS3_CFG_MASK 0x00000020 +#define CS3_CFG_DISABLE 0x00000000 +#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020 +#define CS3_CFG(i) ((i) << 5) + +#define CS2_CFG_MASK 0x00000010 +#define CS2_CFG_DISABLE 0x00000000 +#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010 +#define CS2_CFG(i) ((i) << 4) + +#define CS1_CFG_MASK 0x0000000c +#define CS1_CFG_DISABLE 0x00000000 +#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004 +#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008 +#define CS1_CFG(i) ((i) << 2) + +#define CS0_CFG_MASK 0x00000003 +#define CS0_CFG_DISABLE 0x00000000 +#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001 +#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002 +#define CS0_CFG(i) ((i) << 0) + +#endif

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Patch set updated for coreboot: 9ce4d8c gpio: Remove non-ternary tristate mode, make ternaries easier
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9401 -gerrit commit 9ce4d8c415b864bc4f87ca1278b70b148d5f800b Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Sep 24 15:40:49 2014 -0700 gpio: Remove non-ternary tristate mode, make ternaries easier The function to read board IDs from tristate GPIOs currently supports two output modes: a normal base-3 integer, or a custom format where every two bits represent one tristate pin. Each board decides which representation to use on its own, which is inconsistent and provides another possible gotcha to trip over when reading unfamiliar code. The two-bits-per-pin format creates the additional problem that a complete list of IDs (such as some boards use to build board-ID tables) necessarily has "holes" in them (since 0b11 does not correspond to a possible pin state), which makes them extremely tricky to write, read and expand. It's also very unintuitive in my opinion, although it was intended to make it easier to read individual pin states from a hex representation. This patch switches all boards over to base-3 and removes the other format to improve consistency. The tristate reading function will just print the pin states as they are read to make it easier to debug them, and we add a new BASE3() macro that can generate ternary numbers from pin states. Also change the order of all static initializers of board ID pin lists to write the most significant bit first, hoping that this can help clear up confusion about the endianness of the pins. CQ-DEPEND=CL:219902 BUG=None TEST=Booted on a Nyan_Blaze (with board ID 1, unfortunately the only one I have). Compiled on Daisy, Peach_Pit, Nyan, Nyan_Big, Nyan_Blaze, Rush, Rush_Ryu, Storm, Veryon_Pinky and Falco for good measure. Change-Id: I3ce5a0829f260db7d7df77e6788c2c6d13901b8f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2fa9545ac431c9af111ee4444d593ee4cf49554d Original-Change-Id: I6133cdaf01ed6590ae07e88d9e85a33dc013211a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219901 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/base3.h | 48 +++++++++++++++++++++++++++++ src/include/gpio.h | 14 +++------ src/lib/tristate_gpios.c | 15 +++++---- src/mainboard/google/nyan_big/boardid.c | 8 ++--- src/mainboard/google/nyan_blaze/boardid.c | 8 ++--- src/mainboard/google/rush_ryu/boardid.c | 46 ++++++++------------------- src/mainboard/google/storm/boardid.c | 4 +-- src/mainboard/google/veyron_pinky/boardid.c | 10 ++---- 8 files changed, 87 insertions(+), 66 deletions(-) diff --git a/src/include/base3.h b/src/include/base3.h new file mode 100644 index 0000000..e92cc8b --- /dev/null +++ b/src/include/base3.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SRC_INCLUDE_BASE3_H__ +#define __SRC_INCLUDE_BASE3_H__ + +/* We translate a floating pin (Z) as the ternary digit 2. */ +#define Z 2 + +/* + * This provides a variadic macro BASE3() that can be used to translate a set of + * pin states into its base-3 integer representation, even in the context of a + * static initializer. You can call it with any number of up to 6 arguments, + * e.g. BASE3(1, Z) -> 5 or BASE3(0, Z, 1, 0) -> 21. Just don't look too closely + * at how the sausage is made. (Pay extra attention to typos when expanding it!) + */ +#define _BASE3_IMPL_1(arg0, arg1, arg2, arg3, arg4, arg5) arg0 +#define _BASE3_IMPL_2(arg0, arg1, arg2, arg3, arg4, arg5) \ + (arg1 + (3 * _BASE3_IMPL_1(arg0, arg1, arg2, arg3, arg4, arg5))) +#define _BASE3_IMPL_3(arg0, arg1, arg2, arg3, arg4, arg5) \ + (arg2 + (3 * _BASE3_IMPL_2(arg0, arg1, arg2, arg3, arg4, arg5))) +#define _BASE3_IMPL_4(arg0, arg1, arg2, arg3, arg4, arg5) \ + (arg3 + (3 * _BASE3_IMPL_3(arg0, arg1, arg2, arg3, arg4, arg5))) +#define _BASE3_IMPL_5(arg0, arg1, arg2, arg3, arg4, arg5) \ + (arg4 + (3 * _BASE3_IMPL_4(arg0, arg1, arg2, arg3, arg4, arg5))) +#define _BASE3_IMPL_6(arg0, arg1, arg2, arg3, arg4, arg5) \ + (arg5 + (3 * _BASE3_IMPL_5(arg0, arg1, arg2, arg3, arg4, arg5))) +#define _BASE3_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, NARGS, ...) \ + _BASE3_IMPL##NARGS(arg0, arg1, arg2, arg3, arg4, arg5) +#define BASE3(...) _BASE3_IMPL(__VA_ARGS__, _6, _5, _4, _3, _2, _1) + +#endif /* __SRC_INCLUDE_BASE3_H__ */ diff --git a/src/include/gpio.h b/src/include/gpio.h index af06697..b2a341d 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -36,17 +36,13 @@ void gpio_output(gpio_t gpio, int value); /* * Read the value presented by the set of GPIOs, when each pin is interpreted - * as a number in 0..2 range depending on the external pullup situation. + * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). + * Example: X1 = Z, X2 = 1 -> gpio_get_tristates({GPIO(X1), GPIO(X2)}) = 5 + * BASE3() from <base3.h> can generate numbers to compare the result to. * - * Depending on the third parameter, the return value is either a set of two - * bit fields, each representing one GPIO value, or a number where each GPIO is - * included multiplied by 3^gpio_num, resulting in a true tertiary value. - * - * gpio[]: pin positions to read. little-endian (less significant value first). + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. - * tertiary: 1: pins are interpreted as a quad coded tertiary. - * 0: pins are interpreted as a set of two bit fields. */ -int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary); +int gpio_get_tristates(gpio_t gpio[], int num_gpio); #endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/lib/tristate_gpios.c b/src/lib/tristate_gpios.c index 5ee5580..0967a8f 100644 --- a/src/lib/tristate_gpios.c +++ b/src/lib/tristate_gpios.c @@ -17,10 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <base3.h> +#include <console/console.h> #include <delay.h> #include <gpio.h> -int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary) +int gpio_get_tristates(gpio_t gpio[], int num_gpio) { /* * GPIOs which are tied to stronger external pull up or pull down @@ -31,6 +33,7 @@ int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary) * internally pulled to. */ + static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; int temp; int index; int id = 0; @@ -62,14 +65,14 @@ int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary) * 1: pull up * 2: floating */ + printk(BIOS_DEBUG, "Reading tristate GPIOs: "); for (index = num_gpio - 1; index >= 0; --index) { - if (tertiary) - id *= 3; - else - id <<= 2; temp = gpio_get(gpio[index]); - id += ((value[index] ^ temp) << 1) | temp; + temp |= ((value[index] ^ temp) << 1); + printk(BIOS_DEBUG, "%c ", tristate_char[temp]); + id = (id * 3) + temp; } + printk(BIOS_DEBUG, "= %d\n", id); /* Disable pull up / pull down to conserve power */ for (index = 0; index < num_gpio; ++index) diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 00f646d..b420f5a 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -25,13 +25,13 @@ uint8_t board_id(void) { static int id = -1; + gpio_t gpio[] = {[3] = GPIO(X4), [2] = GPIO(X1), /* X4 is MSB */ + [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); - - printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); + printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } return id; diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 00f646d..b420f5a 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -25,13 +25,13 @@ uint8_t board_id(void) { static int id = -1; + gpio_t gpio[] = {[3] = GPIO(X4), [2] = GPIO(X1), /* X4 is MSB */ + [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); - - printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); + printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } return id; diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index ba3a4be..5b4c1cd 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -17,35 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <base3.h> #include <boardid.h> #include <console/console.h> #include <stdlib.h> #include "gpio.h" -/* - * +------------------+---------+ - * | BD_ID_STRAP[1:0] | PHASE | - * +------------------+---------+ - * | 00 | PROTO0 | - * +------------------+---------+ - * | 01 | PROTO1 | - * +------------------+---------+ - * | 0Z | EVT | - * +------------------+---------+ - * | 10 | DVT | - * +------------------+---------+ - * | 11 | PVT | - * +------------------+---------+ - * | 1Z | MP | - * +------------------+---------+ - * | Z0 | | - * +------------------+---------+ - * | Z1 | | - * +------------------+---------+ - * | ZZ | | - * +------------------+---------+ - */ struct id_to_str { const char *str; int tri_state_value; @@ -53,15 +31,15 @@ struct id_to_str { }; static const struct id_to_str bdid_map[] = { - { "PROTO 0", 0x00, BOARD_ID_PROTO_0 }, - { "PROTO 1", 0x01, BOARD_ID_PROTO_1 }, - { "EVT", 0x02, BOARD_ID_EVT }, - { "DVT", 0x04, BOARD_ID_DVT }, - { "PVT", 0x05, BOARD_ID_PVT }, - { "MP", 0x06, BOARD_ID_MP }, - { "Z0", 0x08, -1 }, - { "Z1", 0x09, -1 }, - { "ZZ", 0x0a, -1 }, + { "PROTO 0", BASE3(0, 0), BOARD_ID_PROTO_0 }, + { "PROTO 1", BASE3(0, 1), BOARD_ID_PROTO_1 }, + { "EVT", BASE3(0, Z), BOARD_ID_EVT }, + { "DVT", BASE3(1, 0), BOARD_ID_DVT }, + { "PVT", BASE3(1, 1), BOARD_ID_PVT }, + { "MP", BASE3(1, Z), BOARD_ID_MP }, + { "Z0", BASE3(Z, 0), -1 }, + { "Z1", BASE3(Z, 1), -1 }, + { "ZZ", BASE3(Z, Z), -1 }, }; uint8_t board_id(void) @@ -72,9 +50,9 @@ uint8_t board_id(void) const char *idstr = "Unknown"; int i; int tristate_id; - gpio_t gpio[] = { BD_ID0, BD_ID1 }; + gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - tristate_id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); + tristate_id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); for (i = 0; i < ARRAY_SIZE(bdid_map); i++) { if (tristate_id != bdid_map[i].tri_state_value) diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 878598b..c32567e 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -42,10 +42,10 @@ static int board_id_value = -1; static uint8_t get_board_id(void) { uint8_t bid; - gpio_t hw_rev_gpios[] = {29, 30, 68}; + gpio_t hw_rev_gpios[] = {[2] = 68, [1] = 30, [0] = 29}; /* 29 is LSB */ int offset = 19; - bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios), 1); + bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); bid = (bid + offset) % 27; printk(BIOS_INFO, "Board ID %d\n", bid); diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c index d8f4a3d..8d3e183 100644 --- a/src/mainboard/google/veyron_pinky/boardid.c +++ b/src/mainboard/google/veyron_pinky/boardid.c @@ -25,12 +25,8 @@ uint8_t board_id(void) { static int id = -1; - static const gpio_t pins[] = { - { .port = 2, .bank = GPIO_A, .idx = 0 }, - { .port = 2, .bank = GPIO_A, .idx = 1 }, - { .port = 2, .bank = GPIO_A, .idx = 2 }, - { .port = 2, .bank = GPIO_A, .idx = 7 }, - }; + static const gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ if (id < 0) { int i; @@ -40,7 +36,7 @@ uint8_t board_id(void) gpio_input(pins[i]); id |= gpio_get(pins[i]) << i; } - printk(BIOS_SPEW, "Board ID: %#x.\n", id); + printk(BIOS_SPEW, "Board ID: %d.\n", id); } return id;

1 0

Patch set updated for coreboot: c8a4380 gpio: Extend common GPIO header, simplify function names
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9400 -gerrit commit c8a43808bbe2846505622501206c4aa2e8cae055 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Sep 24 15:40:49 2014 -0700 gpio: Extend common GPIO header, simplify function names We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/gpio.h | 52 +++++++++++++++++++++++ src/include/gpiolib.h | 51 ---------------------- src/lib/tristate_gpios.c | 8 ++-- src/mainboard/google/nyan/boardid.c | 10 ++--- src/mainboard/google/nyan/bootblock.c | 2 +- src/mainboard/google/nyan/chromeos.c | 10 ++--- src/mainboard/google/nyan/early_configs.c | 2 +- src/mainboard/google/nyan/mainboard.c | 2 +- src/mainboard/google/nyan/reset.c | 2 +- src/mainboard/google/nyan_big/boardid.c | 4 +- src/mainboard/google/nyan_big/bootblock.c | 2 +- src/mainboard/google/nyan_big/chromeos.c | 10 ++--- src/mainboard/google/nyan_big/early_configs.c | 2 +- src/mainboard/google/nyan_big/mainboard.c | 2 +- src/mainboard/google/nyan_big/reset.c | 2 +- src/mainboard/google/nyan_blaze/boardid.c | 4 +- src/mainboard/google/nyan_blaze/bootblock.c | 2 +- src/mainboard/google/nyan_blaze/chromeos.c | 10 ++--- src/mainboard/google/nyan_blaze/early_configs.c | 2 +- src/mainboard/google/nyan_blaze/mainboard.c | 2 +- src/mainboard/google/nyan_blaze/reset.c | 2 +- src/mainboard/google/rush/boardid.c | 10 ++--- src/mainboard/google/rush/chromeos.c | 6 +-- src/mainboard/google/rush/reset.c | 2 +- src/mainboard/google/rush_ryu/boardid.c | 4 +- src/mainboard/google/rush_ryu/chromeos.c | 6 +-- src/mainboard/google/rush_ryu/gpio.h | 2 +- src/mainboard/google/rush_ryu/romstage.c | 2 +- src/mainboard/google/storm/boardid.c | 9 ++-- src/mainboard/google/storm/cdp.c | 2 +- src/mainboard/google/storm/mainboard.c | 13 +++--- src/mainboard/google/veyron_pinky/board.h | 2 +- src/mainboard/google/veyron_pinky/boardid.c | 4 +- src/mainboard/google/veyron_pinky/chromeos.c | 12 +++--- src/mainboard/google/veyron_pinky/mainboard.c | 6 +-- src/mainboard/google/veyron_pinky/reset.c | 2 +- src/mainboard/google/veyron_pinky/sdram_configs.c | 10 ++--- src/soc/nvidia/tegra/gpio.c | 23 +++++++--- src/soc/nvidia/tegra/gpio.h | 20 ++------- src/soc/nvidia/tegra/software_i2c.c | 6 +-- src/soc/nvidia/tegra124/chip.h | 2 +- src/soc/qualcomm/ipq806x/gpio.c | 6 +-- src/soc/qualcomm/ipq806x/include/soc/gpio.h | 4 +- src/soc/qualcomm/ipq806x/spi.c | 2 +- src/soc/qualcomm/ipq806x/uart.c | 2 +- src/soc/rockchip/rk3288/gpio.c | 6 +-- src/soc/rockchip/rk3288/include/soc/gpio.h | 8 +--- src/soc/rockchip/rk3288/soc.c | 2 +- src/soc/samsung/exynos5250/include/soc/gpio.h | 2 + src/soc/samsung/exynos5420/include/soc/gpio.h | 2 + 50 files changed, 177 insertions(+), 183 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h new file mode 100644 index 0000000..af06697 --- /dev/null +++ b/src/include/gpio.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SRC_INCLUDE_GPIO_H__ +#define __SRC_INCLUDE_GPIO_H__ + +#include <soc/gpio.h> +#include <types.h> + +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +_Static_assert(sizeof(gpio_t) <= sizeof(u32), "gpio_t doesn't fit in lb_gpio"); + +/* The following functions must be implemented by SoC/board code. */ +int gpio_get(gpio_t gpio); +void gpio_set(gpio_t gpio, int value); +void gpio_input_pulldown(gpio_t gpio); +void gpio_input_pullup(gpio_t gpio); +void gpio_input(gpio_t gpio); +void gpio_output(gpio_t gpio, int value); + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a number in 0..2 range depending on the external pullup situation. + * + * Depending on the third parameter, the return value is either a set of two + * bit fields, each representing one GPIO value, or a number where each GPIO is + * included multiplied by 3^gpio_num, resulting in a true tertiary value. + * + * gpio[]: pin positions to read. little-endian (less significant value first). + * num_gpio: number of pins to read. + * tertiary: 1: pins are interpreted as a quad coded tertiary. + * 0: pins are interpreted as a set of two bit fields. + */ +int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary); + +#endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/include/gpiolib.h b/src/include/gpiolib.h deleted file mode 100644 index 436f26a..0000000 --- a/src/include/gpiolib.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __SRC_INCLUDE_GPIOLIB_H__ -#define __SRC_INCLUDE_GPIOLIB_H__ - -/* A generic type, use accessor macros to actually access the hardware. */ -typedef unsigned gpio_t; - -/* - * Read the value presented by the set of GPIOs, when each pin is interpreted - * as a number in 0..2 range depending on the external pullup situation. - * - * Depending on the third parameter, the return value is either a set of two - * bit fields, each representing one GPIO value, or a number where each GPIO is - * included multiplied by 3^gpio_num, resulting in a true tertiary value. - * - * gpio[]: pin positions to read. little-endian (less significant value first). - * num_gpio: number of pins to read. - * tertiary: 1: pins are interpreted as a quad coded tertiary. - * 0: pins are interpreted as a set of two bit fields. - */ -int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int tertiary); - -/* - * The following functions are not provided by the common library, but must be - * implemented by the appropriate SOC/board instead. - */ -int gpio_get_in_value(gpio_t gpio); -void gpio_set_out_value(gpio_t gpio, int value); -void gpio_input_pulldown(gpio_t gpio); -void gpio_input_pullup(gpio_t gpio); -void gpio_input(gpio_t gpio); - -#endif diff --git a/src/lib/tristate_gpios.c b/src/lib/tristate_gpios.c index 8e93e37..5ee5580 100644 --- a/src/lib/tristate_gpios.c +++ b/src/lib/tristate_gpios.c @@ -18,9 +18,9 @@ */ #include <delay.h> -#include <gpiolib.h> +#include <gpio.h> -int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int tertiary) +int gpio_get_tristates(gpio_t gpio[], int num_gpio, int tertiary) { /* * GPIOs which are tied to stronger external pull up or pull down @@ -45,7 +45,7 @@ int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int tertiary) /* Get gpio values at internal pull up */ for (index = 0; index < num_gpio; ++index) - value[index] = gpio_get_in_value(gpio[index]); + value[index] = gpio_get(gpio[index]); /* Enable internal pull down */ for (index = 0; index < num_gpio; ++index) @@ -67,7 +67,7 @@ int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int tertiary) id *= 3; else id <<= 2; - temp = gpio_get_in_value(gpio[index]); + temp = gpio_get(gpio[index]); id += ((value[index] ^ temp) << 1) | temp; } diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c index 4628cb6..85a55fc 100644 --- a/src/mainboard/google/nyan/boardid.c +++ b/src/mainboard/google/nyan/boardid.c @@ -19,17 +19,17 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> uint8_t board_id(void) { static int id = -1; if (id < 0) { - id = gpio_get_in_value(GPIO(Q3)) << 0 | - gpio_get_in_value(GPIO(T1)) << 1 | - gpio_get_in_value(GPIO(X1)) << 2 | - gpio_get_in_value(GPIO(X4)) << 3; + id = gpio_get(GPIO(Q3)) << 0 | + gpio_get(GPIO(T1)) << 1 | + gpio_get(GPIO(X1)) << 2 | + gpio_get(GPIO(X4)) << 3; printk(BIOS_SPEW, "Board ID: %#x.\n", id); } diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 1f23d43..bc3cd3e 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -21,10 +21,10 @@ #include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/pinmux.h> #include <soc/spi.h> /* FIXME: move back to soc code? */ diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 1210f75..91a3f13 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_R1_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + gpios->gpios[count].value = gpio_get(GPIO(R1)); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -49,14 +49,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = GPIO_R4_INDEX; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R4)); + gpios->gpios[count].value = gpio_get(GPIO(R4)); strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; /* Power: active low */ gpios->gpios[count].port = GPIO_Q0_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0)); + gpios->gpios[count].value = gpio_get(GPIO(Q0)); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -91,5 +91,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO(R1)); + return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/nyan/early_configs.c b/src/mainboard/google/nyan/early_configs.c index 046e2bd..de9fe8e 100644 --- a/src/mainboard/google/nyan/early_configs.c +++ b/src/mainboard/google/nyan/early_configs.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/early_configs.h> -#include <soc/gpio.h> #include <soc/nvidia/tegra/i2c.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index f4aa93a..dce4cbc 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -21,10 +21,10 @@ #include <device/device.h> #include <elog.h> #include <boot/coreboot_tables.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/clk_rst.h> -#include <soc/gpio.h> #include <soc/mc.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra/usb.h> diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c index de096c6..e58890e 100644 --- a/src/mainboard/google/nyan/reset.c +++ b/src/mainboard/google/nyan/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <reset.h> void hard_reset(void) diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 335da87..00f646d 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -19,7 +19,7 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> #include <stdlib.h> uint8_t board_id(void) @@ -29,7 +29,7 @@ uint8_t board_id(void) if (id < 0) { gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; - id = gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), 0); + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); } diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c index b24862e..c471cb8 100644 --- a/src/mainboard/google/nyan_big/bootblock.c +++ b/src/mainboard/google/nyan_big/bootblock.c @@ -21,10 +21,10 @@ #include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/pinmux.h> #include <soc/spi.h> /* FIXME: move back to soc code? */ diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 28da053..7073198 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_R1_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + gpios->gpios[count].value = gpio_get(GPIO(R1)); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -49,14 +49,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = GPIO_R4_INDEX; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R4)); + gpios->gpios[count].value = gpio_get(GPIO(R4)); strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; /* Power: active low */ gpios->gpios[count].port = GPIO_Q0_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0)); + gpios->gpios[count].value = gpio_get(GPIO(Q0)); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -91,5 +91,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO(R1)); + return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/nyan_big/early_configs.c b/src/mainboard/google/nyan_big/early_configs.c index 046e2bd..de9fe8e 100644 --- a/src/mainboard/google/nyan_big/early_configs.c +++ b/src/mainboard/google/nyan_big/early_configs.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/early_configs.h> -#include <soc/gpio.h> #include <soc/nvidia/tegra/i2c.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 63d9d5c..712269a 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -21,10 +21,10 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <elog.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/mc.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/pmc.h> diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c index de096c6..e58890e 100644 --- a/src/mainboard/google/nyan_big/reset.c +++ b/src/mainboard/google/nyan_big/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <reset.h> void hard_reset(void) diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 335da87..00f646d 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -19,7 +19,7 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> #include <stdlib.h> uint8_t board_id(void) @@ -29,7 +29,7 @@ uint8_t board_id(void) if (id < 0) { gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)}; - id = gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), 0); + id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id); } diff --git a/src/mainboard/google/nyan_blaze/bootblock.c b/src/mainboard/google/nyan_blaze/bootblock.c index b24862e..c471cb8 100644 --- a/src/mainboard/google/nyan_blaze/bootblock.c +++ b/src/mainboard/google/nyan_blaze/bootblock.c @@ -21,10 +21,10 @@ #include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/pinmux.h> #include <soc/spi.h> /* FIXME: move back to soc code? */ diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 0b944d1..7718849 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_R1_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + gpios->gpios[count].value = gpio_get(GPIO(R1)); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -53,14 +53,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = GPIO_R4_INDEX; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R4)); + gpios->gpios[count].value = gpio_get(GPIO(R4)); strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; /* Power: active low */ gpios->gpios[count].port = GPIO_Q0_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0)); + gpios->gpios[count].value = gpio_get(GPIO(Q0)); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -95,5 +95,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO(R1)); + return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/nyan_blaze/early_configs.c b/src/mainboard/google/nyan_blaze/early_configs.c index 020f3fd..de9fe8e 100644 --- a/src/mainboard/google/nyan_blaze/early_configs.c +++ b/src/mainboard/google/nyan_blaze/early_configs.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/early_configs.h> #include <soc/nvidia/tegra/i2c.h> diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index da49377..9daa2bb 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -21,10 +21,10 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <elog.h> +#include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/clk_rst.h> -#include <soc/gpio.h> #include <soc/mc.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra/usb.h> diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c index de096c6..e58890e 100644 --- a/src/mainboard/google/nyan_blaze/reset.c +++ b/src/mainboard/google/nyan_blaze/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <reset.h> void hard_reset(void) diff --git a/src/mainboard/google/rush/boardid.c b/src/mainboard/google/rush/boardid.c index 7ed2b53..0c9d2c5 100644 --- a/src/mainboard/google/rush/boardid.c +++ b/src/mainboard/google/rush/boardid.c @@ -19,17 +19,17 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> uint8_t board_id(void) { static int id = -1; if (id < 0) { - id = gpio_get_in_value(GPIO(Q3)) << 0 | - gpio_get_in_value(GPIO(T1)) << 1 | - gpio_get_in_value(GPIO(X1)) << 2 | - gpio_get_in_value(GPIO(X4)) << 3; + id = gpio_get(GPIO(Q3)) << 0 | + gpio_get(GPIO(T1)) << 1 | + gpio_get(GPIO(X1)) << 2 | + gpio_get(GPIO(X4)) << 3; printk(BIOS_SPEW, "Board ID: %#x.\n", id); } diff --git a/src/mainboard/google/rush/chromeos.c b/src/mainboard/google/rush/chromeos.c index 5232344..1a017f5 100644 --- a/src/mainboard/google/rush/chromeos.c +++ b/src/mainboard/google/rush/chromeos.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -32,7 +32,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_R1_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + gpios->gpios[count].value = gpio_get(GPIO(R1)); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -90,5 +90,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO(R1)); + return !gpio_get(GPIO(R1)); } diff --git a/src/mainboard/google/rush/reset.c b/src/mainboard/google/rush/reset.c index dbaed0d..0fc6320 100644 --- a/src/mainboard/google/rush/reset.c +++ b/src/mainboard/google/rush/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <reset.h> void hard_reset(void) diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index 9d99b90..ba3a4be 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -19,7 +19,6 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> #include <stdlib.h> #include "gpio.h" @@ -75,8 +74,7 @@ uint8_t board_id(void) int tristate_id; gpio_t gpio[] = { BD_ID0, BD_ID1 }; - tristate_id = gpio_get_in_tristate_values(gpio, - ARRAY_SIZE(gpio), 0); + tristate_id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio), 0); for (i = 0; i < ARRAY_SIZE(bdid_map); i++) { if (tristate_id != bdid_map[i].tri_state_value) diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c index 521fe59..f752aee 100644 --- a/src/mainboard/google/rush_ryu/chromeos.c +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = WRITE_PROTECT_L_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(WRITE_PROTECT_L); + gpios->gpios[count].value = gpio_get(WRITE_PROTECT_L); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -51,7 +51,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Power: active low */ gpios->gpios[count].port = POWER_BUTTON_INDEX, gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(POWER_BUTTON); + gpios->gpios[count].value = gpio_get(POWER_BUTTON); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -86,5 +86,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(WRITE_PROTECT_L); + return !gpio_get(WRITE_PROTECT_L); } diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h index 9c67420..2792ec3 100644 --- a/src/mainboard/google/rush_ryu/gpio.h +++ b/src/mainboard/google/rush_ryu/gpio.h @@ -20,7 +20,7 @@ #ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ #define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ -#include <soc/gpio.h> +#include <gpio.h> /* Board ID definitions. */ enum { diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index 41c9149..fc2379f 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -69,7 +69,7 @@ static void lte_modem_init(void) int mdm_det; /* A LTE modem is present if MDM_DET is pulled down by the modem */ - mdm_det = gpio_get_in_value(MDM_DET); + mdm_det = gpio_get(MDM_DET); if (mdm_det == 1) return; diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index a8dd844..878598b 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -18,15 +18,15 @@ */ #include <boardid.h> -#include <gpiolib.h> +#include <gpio.h> #include <console/console.h> #include <stdlib.h> /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 * and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by - * gpio_get_in_tristate_values(), whereas the other two pins are not connected - * and read as 'two'. This results in gpio_get_in_tristate_values() returning + * gpio_get_tristates(), whereas the other two pins are not connected + * and read as 'two'. This results in gpio_get_tristates() returning * 8 on proto0. * * Three tertitiary signals could represent 27 different values. To make @@ -45,8 +45,7 @@ static uint8_t get_board_id(void) gpio_t hw_rev_gpios[] = {29, 30, 68}; int offset = 19; - bid = gpio_get_in_tristate_values(hw_rev_gpios, - ARRAY_SIZE(hw_rev_gpios), 1); + bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios), 1); bid = (bid + offset) % 27; printk(BIOS_INFO, "Board ID %d\n", bid); diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 7e1aeb6..78edb26 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.* */ -#include <soc/gpio.h> +#include <gpio.h> #include <soc/cdp.h> #include <types.h> diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 552f968..59e7ce7 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -23,9 +23,8 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <gpiolib.h> +#include <gpio.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/usb.h> #include <string.h> #include <symbols.h> @@ -46,7 +45,7 @@ static void setup_usb(void) #if !CONFIG_BOARD_VARIANT_AP148 gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); - gpio_set_out_value(USB_ENABLE_GPIO, 1); + gpio_set(USB_ENABLE_GPIO, 1); #endif usb_clock_config(); @@ -86,9 +85,9 @@ static void setup_tpm(void) * make it twice as long. If the output was driven low originally, the * reset pulse will be even longer. */ - gpio_set_out_value(TPM_RESET_GPIO, 0); + gpio_set(TPM_RESET_GPIO, 0); udelay(160); - gpio_set_out_value(TPM_RESET_GPIO, 1); + gpio_set(TPM_RESET_GPIO, 1); } #define SW_RESET_GPIO 26 @@ -106,7 +105,7 @@ static void deassert_sw_reset(void) gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); - gpio_set_out_value(SW_RESET_GPIO, 0); + gpio_set(SW_RESET_GPIO, 0); } static void mainboard_init(device_t dev) @@ -148,7 +147,7 @@ static int read_gpio(gpio_t gpio_num) gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); udelay(10); /* Should be enough to settle. */ - return gpio_get_in_value(gpio_num); + return gpio_get(gpio_num); } void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h index 8d452c8..73eb5ef 100644 --- a/src/mainboard/google/veyron_pinky/board.h +++ b/src/mainboard/google/veyron_pinky/board.h @@ -21,7 +21,7 @@ #define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H #include <boardid.h> -#include <soc/gpio.h> +#include <gpio.h> #define PMIC_BUS 0 diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c index 01e92a3..d8f4a3d 100644 --- a/src/mainboard/google/veyron_pinky/boardid.c +++ b/src/mainboard/google/veyron_pinky/boardid.c @@ -19,7 +19,7 @@ #include <boardid.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> #include <stdlib.h> uint8_t board_id(void) @@ -38,7 +38,7 @@ uint8_t board_id(void) id = 0; for (i = 0; i < ARRAY_SIZE(pins); i++) { gpio_input(pins[i]); - id |= gpio_get_in_value(pins[i]) << i; + id |= gpio_get(pins[i]) << i; } printk(BIOS_SPEW, "Board ID: %#x.\n", id); } diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 30cd277..dc224a5 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -47,7 +47,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_WP.raw; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO_WP); + gpios->gpios[count].value = gpio_get(GPIO_WP); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -63,14 +63,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = GPIO_LID.raw; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO_LID); + gpios->gpios[count].value = gpio_get(GPIO_LID); strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; /* Power:GPIO active high */ gpios->gpios[count].port = GPIO_POWER.raw; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO_POWER); + gpios->gpios[count].value = gpio_get(GPIO_POWER); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -99,7 +99,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!gpio_get_in_value(GPIO_RECOVERY)) + if (!gpio_get(GPIO_RECOVERY)) return 1; ec_events = google_chromeec_get_events_b(); @@ -109,6 +109,6 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO_WP); + return !gpio_get(GPIO_WP); } diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index a8cc3c3..2442472 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -19,13 +19,13 @@ #include <arch/cache.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <edid.h> -#include <boot/coreboot_tables.h> #include <device/i2c.h> -#include <soc/gpio.h> +#include <edid.h> +#include <gpio.h> #include <soc/grf.h> #include <soc/soc.h> #include <soc/pmu.h> diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c index a2777f8..9cbe9c1 100644 --- a/src/mainboard/google/veyron_pinky/reset.c +++ b/src/mainboard/google/veyron_pinky/reset.c @@ -18,7 +18,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <reset.h> #include "board.h" diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c index 1a331ce..a58c6dd 100644 --- a/src/mainboard/google/veyron_pinky/sdram_configs.c +++ b/src/mainboard/google/veyron_pinky/sdram_configs.c @@ -18,8 +18,8 @@ */ #include <arch/io.h> #include <console/console.h> +#include <gpio.h> #include <soc/sdram.h> -#include <soc/gpio.h> #include <string.h> #include <types.h> @@ -56,10 +56,10 @@ u32 sdram_get_ram_code(void) gpio_input(GPIO_RAMCODE2); gpio_input(GPIO_RAMCODE3); - code = gpio_get_in_value(GPIO_RAMCODE3) << 3 - | gpio_get_in_value(GPIO_RAMCODE2) << 2 - | gpio_get_in_value(GPIO_RAMCODE1) << 1 - | gpio_get_in_value(GPIO_RAMCODE0) << 0; + code = gpio_get(GPIO_RAMCODE3) << 3 + | gpio_get(GPIO_RAMCODE2) << 2 + | gpio_get(GPIO_RAMCODE1) << 1 + | gpio_get(GPIO_RAMCODE0) << 0; return code; } diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 9f09f24..009334f 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -19,16 +19,15 @@ #include <arch/io.h> #include <console/console.h> +#include <gpio.h> #include <soc/addressmap.h> #include <stddef.h> #include <stdint.h> #include <delay.h> -#include <gpiolib.h> -#include "gpio.h" #include "pinmux.h" -void __gpio_input(gpio_t gpio, u32 pull) +static void __gpio_input(gpio_t gpio, u32 pull) { u32 pinmux_config = PINMUX_INPUT_ENABLE | pull; @@ -38,10 +37,10 @@ void __gpio_input(gpio_t gpio, u32 pull) pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config); } -void __gpio_output(gpio_t gpio, int value, u32 od) +static void __gpio_output(gpio_t gpio, int value, u32 od) { gpio_set_int_enable(gpio, 0); - gpio_set_out_value(gpio, value); + gpio_set(gpio, value); gpio_set_out_enable(gpio, 1); gpio_set_mode(gpio, GPIO_MODE_GPIO); pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE | od); @@ -121,7 +120,7 @@ int gpio_get_out_enable(gpio_t gpio) return (port & (1 << bit)) != 0; } -void gpio_set_out_value(gpio_t gpio, int value) +void gpio_set(gpio_t gpio, int value) { int bit = gpio % GPIO_GPIOS_PER_PORT; gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), @@ -137,7 +136,7 @@ int gpio_get_out_value(gpio_t gpio) return (port & (1 << bit)) != 0; } -int gpio_get_in_value(gpio_t gpio) +int gpio_get(gpio_t gpio) { int bit = gpio % GPIO_GPIOS_PER_PORT; u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), @@ -212,3 +211,13 @@ void gpio_input(gpio_t gpio) { __gpio_input(gpio, PINMUX_PULL_NONE); } + +void gpio_output(gpio_t gpio, int value) +{ + __gpio_output(gpio, value, 0); +} + +void gpio_output_open_drain(gpio_t gpio, int value) +{ + __gpio_output(gpio, value, PINMUX_OPEN_DRAIN); +} diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index 2ad3ab3..72c7179 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -21,29 +21,15 @@ #define __SOC_NVIDIA_TEGRA_GPIO_H__ #include <stdint.h> -#include <gpiolib.h> #include "pinmux.h" +typedef u32 gpio_t; + #define GPIO_PINMUX_SHIFT 16 #define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) -void __gpio_output(gpio_t gpio, int value, u32 open_drain); -void __gpio_input(gpio_t gpio, u32 pull); - -/* Higher level function wrappers for common GPIO configurations. */ - -static inline void gpio_output(gpio_t gpio, int value) -{ - __gpio_output(gpio, value, 0); -} - -static inline void gpio_output_open_drain(gpio_t gpio, int value) -{ - __gpio_output(gpio, value, PINMUX_OPEN_DRAIN); -} - /* Functions to modify specific GPIO control values. */ enum gpio_mode { @@ -72,6 +58,8 @@ void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta); void gpio_set_int_clear(gpio_t gpio); +void gpio_output_open_drain(gpio_t gpio, int value); + /* Hardware definitions. */ enum { diff --git a/src/soc/nvidia/tegra/software_i2c.c b/src/soc/nvidia/tegra/software_i2c.c index 35fc1af..d1172bc 100644 --- a/src/soc/nvidia/tegra/software_i2c.c +++ b/src/soc/nvidia/tegra/software_i2c.c @@ -18,7 +18,7 @@ */ #include <device/i2c.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/pinmux.h> #include "i2c.h" @@ -58,12 +58,12 @@ static void tegra_set_scl(unsigned bus, int high) static int tegra_get_sda(unsigned bus) { - return gpio_get_in_value(pins[bus].sda); + return gpio_get(pins[bus].sda); } static int tegra_get_scl(unsigned bus) { - return gpio_get_in_value(pins[bus].scl); + return gpio_get(pins[bus].scl); } static struct software_i2c_ops tegra_ops = { diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index c3652a1..acabd37 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -20,8 +20,8 @@ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ #include <arch/cache.h> +#include <gpio.h> #include <soc/addressmap.h> -#include <soc/gpio.h> #define EFAULT 1 #define EINVAL 2 diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 46dca4e..a0a3df9 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -29,7 +29,7 @@ */ #include <arch/io.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/iomap.h> /******************************************************* @@ -116,7 +116,7 @@ unsigned *out - Value of GPIO output Return : None *******************************************************/ -int gpio_get_in_value(gpio_t gpio) +int gpio_get(gpio_t gpio) { if (gpio_not_valid(gpio)) return -1; @@ -126,7 +126,7 @@ int gpio_get_in_value(gpio_t gpio) GPIO_IO_IN_MASK; } -void gpio_set_out_value(gpio_t gpio, int value) +void gpio_set(gpio_t gpio, int value) { if (gpio_not_valid(gpio)) return; diff --git a/src/soc/qualcomm/ipq806x/include/soc/gpio.h b/src/soc/qualcomm/ipq806x/include/soc/gpio.h index 276022c..3542991 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/soc/gpio.h @@ -33,7 +33,7 @@ #ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ #define __SOC_QUALCOMM_IPQ806X_GPIO_H_ -#include <gpiolib.h> +#include <types.h> #define GPIO_FUNC_ENABLE 1 #define GPIO_FUNC_DISABLE 0 @@ -90,6 +90,8 @@ #define GPIO_IO_IN_SHIFT 0 #define GPIO_IO_OUT_SHIFT 1 +typedef u32 gpio_t; + void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, unsigned int pull, unsigned int drvstr, unsigned int enable); diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 4cf64eb..0f72cac 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -4,7 +4,7 @@ #include <arch/io.h> #include <delay.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3e8e187..0a19e9a 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -36,8 +36,8 @@ #include <console/console.h> #include <console/uart.h> #include <delay.h> +#include <gpio.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/gsbi.h> #include <soc/ipq_uart.h> #include <stdint.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index c3784ec..b84d6a0 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -19,10 +19,10 @@ #include <arch/io.h> #include <console/console.h> -#include <soc/soc.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/grf.h> #include <soc/pmu.h> +#include <soc/soc.h> #include <stdlib.h> struct rk3288_gpio_regs *gpio_port[] = { @@ -72,7 +72,7 @@ void gpio_input_pullup(gpio_t gpio) __gpio_input(gpio, PULLUP); } -int gpio_get_in_value(gpio_t gpio) +int gpio_get(gpio_t gpio) { return (readl(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1; } diff --git a/src/soc/rockchip/rk3288/include/soc/gpio.h b/src/soc/rockchip/rk3288/include/soc/gpio.h index c459de9..6a0055e 100644 --- a/src/soc/rockchip/rk3288/include/soc/gpio.h +++ b/src/soc/rockchip/rk3288/include/soc/gpio.h @@ -67,10 +67,4 @@ enum { GPIO_D, }; -void gpio_input(gpio_t gpio); -void gpio_input_pulldown(gpio_t gpio); -void gpio_input_pullup(gpio_t gpio); -void gpio_output(gpio_t gpio, int value); -int gpio_get_in_value(gpio_t gpio); - -#endif /* _ASM_ROCKCHIP_GPIO_H_ */ +#endif /* __SOC_ROCKCHIP_RK3288_GPIO_H__ */ diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index f5e52eb..e74dbd4 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/soc.h> #include <stddef.h> #include <stdlib.h> diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index bbe97a1..398e7b0 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -22,6 +22,8 @@ #include <soc/cpu.h> +/* TODO: Align interface to src/include/gpio.h! */ + struct gpio_bank { unsigned int con; unsigned int dat; diff --git a/src/soc/samsung/exynos5420/include/soc/gpio.h b/src/soc/samsung/exynos5420/include/soc/gpio.h index 1c6a77b..ee34bc3 100644 --- a/src/soc/samsung/exynos5420/include/soc/gpio.h +++ b/src/soc/samsung/exynos5420/include/soc/gpio.h @@ -22,6 +22,8 @@ #include <soc/cpu.h> +/* TODO: Align interface to src/include/gpio.h! */ + struct gpio_bank { unsigned int con; unsigned int dat;

1 0

Patch set updated for coreboot: 3fbfecf storm: retrieve MAC address from VPD
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9399 -gerrit commit 3fbfecf856dc6c6697dba8d9f577ec2d0cf7f009 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Oct 16 13:26:59 2014 -0700 storm: retrieve MAC address from VPD Retrieving MAC address from VPD should be the board responsibility, add a call to the recently introduced function. BRANCH=storm BUG=chromium:417117 TEST=verified that MAC addresses still show up in the device tree on storm Change-Id: Ib8ddc88ccd859e0b36e65aaaeb5c9473077c8c02 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 285cb256e619ef41c7f11680b3fa5310b1d93cf1 Original-Change-Id: I3913b10a425d8e8621b832567871ed4861756381 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223797 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index acadce5..552f968 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -136,6 +136,11 @@ void lb_board(struct lb_header *header) dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = _dma_coherent_size; + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Retrieve the switch interface MAC addressses. */ + lb_table_add_macs_from_vpd(header); +#endif } static int read_gpio(gpio_t gpio_num)

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Patch set updated for coreboot: 37465b5 rk3288: slowly raise to max cpu voltage to prevent overshoot
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9408 -gerrit commit 37465b5014c6fa31b1df799adfe54bfcb202c97b Author: huang lin <hl(a)rock-chips.com> Date: Fri Oct 31 16:40:42 2014 +0800 rk3288: slowly raise to max cpu voltage to prevent overshoot slowly raise to max cpu voltage to prevent overshoot, and in our experience,when cpu run in 1.8GHz,the vdd_cpu must up to 1.4V BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv and measure the overshoot is 1440mv Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2 Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226753 Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_pinky/bootblock.c | 13 +++++++++++-- src/soc/rockchip/rk3288/rk808.c | 1 - 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index b34199d..99719c4 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -27,16 +27,25 @@ #include <soc/rk808.h> #include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <delay.h> #include "board.h" void bootblock_mainboard_init(void) { - /* cpu frequency will up to 1.8GHz, so the buck1 must up to 1.3v */ + /* cpu frequency will up to 1.8GHz, + * in our experience the buck1 + * must up to 1.4v + */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); i2c_init(PMIC_BUS, 400*KHz); - rk808_configure_buck(PMIC_BUS, 1, 1300); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(PMIC_BUS, 1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(PMIC_BUS, 1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); /* i2c1 for tpm */ diff --git a/src/soc/rockchip/rk3288/rk808.c b/src/soc/rockchip/rk3288/rk808.c index aa39b8d..fea64e5 100644 --- a/src/soc/rockchip/rk3288/rk808.c +++ b/src/soc/rockchip/rk3288/rk808.c @@ -98,5 +98,4 @@ void rk808_configure_buck(uint8_t bus, int buck, int millivolts) } rk808_clrsetbits(bus, buck_reg, 0x3f, vsel); rk808_clrsetbits(bus, DCDC_EN, 0, 1 << (buck - 1)); - udelay(225);/* Must wait for voltage to stabilize */ }

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Patch set updated for coreboot: e6e694f rk3288: don't log LAST_TSHUT bit
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9409 -gerrit commit e6e694fc0d45ae19038d8cd5c4bf8b6a33ee36be Author: huang lin <hl(a)rock-chips.com> Date: Fri Nov 7 10:56:35 2014 +0800 rk3288: don't log LAST_TSHUT bit Since the LAST_THSUT bit is uncertain value when it cold-reboot, we remove the printout about this status bit in coreboot. BUG=chrome-os-partner:33521 TEST=Boot on veyron_pinky rev2 Change-Id: I3b9791ffdffeff0721e3d86378db6255c5abc9ea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 16464d3229ad1001952ef1b50fe3e606d1583462 Original-Change-Id: I258750797e32c28f86e73a01eede005e890a6906 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228391 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/tsadc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index b7d8e9d..a2d6ec4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -88,11 +88,7 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - if (readl(&rk3288_tsadc->auto_con) & LAST_TSHUT) { - printk(BIOS_WARNING, "last shutdown/rebot was caused " - "by over-temperature hardware trigger!\n"); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); - } + setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); setbits_le32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 |

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coreboot-gerrit April 2015