coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: bb4c174 rk3288: Adjust CBFS header and ROM offsets
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9410 -gerrit commit bb4c1745f051e92f7c0b2cc1f3c480a76f695c5e Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Nov 6 17:32:58 2014 -0800 rk3288: Adjust CBFS header and ROM offsets Our CBFS header offset on rk3288 was very low and overlapped with the end of the bootblock on recent Pinky builds. This can create all kinds of fun effects like BSS variables suddenly being initialized to something else than zero, in an effect that jumps somewhere else for every slightest code size change. This patch moves the CBFS header offset up a bit and the CBFS ROM offset down (because there's really no point in leaving such a large gap). This resolves our immediate booting problems, and I'll also start on a patch to add further checks somewhere that catch these overlaps in the future. BRANCH=None BUG=None TEST=Created a Pinky image from the exact same commit version as the official 6443.0.0 build, with a KERNELREVISION string of the exact same length as the builder (which for some arcane reason is different than running emerge locally, shifting the whole bootblock around with it). Confirmed that I saw the same "Not enough room for another sub-pagetable!" hang, and that this patch fixes it. Change-Id: I9e59a282b3cd0af3b0d224d64c10b7c4d312ad02 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a142cd2c51c6f51a1597c21ad513feb151e0938 Original-Change-Id: I8be5b7b7e87021cc1b3a91d336e8d233546ee188 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228326 Original-Reviewed-by: Gediminas Ramanauskas <gedis(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/rockchip/rk3288/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0865fe8..b2fd0fb 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -48,10 +48,10 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex - default 0x0008000 + default 0x0010000 config CBFS_ROM_OFFSET hex - default 0x0018000 + default 0x0010100 endif

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Patch set updated for coreboot: 80eb577 gpio: cosmetic changes to tristate_gpios.c
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9411 -gerrit commit 80eb57750cec0777eaa33aac76a95b603d057f39 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:09:27 2014 -0800 gpio: cosmetic changes to tristate_gpios.c This patch makes a few cosmetic changes: - Rename tristate_gpios.c to gpio.c since it will soon be used for binary GPIOs as well. - Rename gpio_get_tristates() to gpio_base3_value() - The binary version will be called gpio_base2_value(). - Updates call sites. - Change the variable name "id" to something more generic. BUG=none BRANCH=none TEST=compiled for veyron_pinky and storm Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228324 --- src/include/gpio.h | 4 +- src/lib/Makefile.inc | 2 +- src/lib/gpio.c | 82 +++++++++++++++++++++++++++++++ src/lib/tristate_gpios.c | 82 ------------------------------- src/mainboard/google/nyan_big/boardid.c | 2 +- src/mainboard/google/nyan_blaze/boardid.c | 2 +- src/mainboard/google/rush_ryu/boardid.c | 2 +- src/mainboard/google/storm/boardid.c | 6 +-- 8 files changed, 91 insertions(+), 91 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h index b2a341d..e54b156 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -37,12 +37,12 @@ void gpio_output(gpio_t gpio, int value); /* * Read the value presented by the set of GPIOs, when each pin is interpreted * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). - * Example: X1 = Z, X2 = 1 -> gpio_get_tristates({GPIO(X1), GPIO(X2)}) = 5 + * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5 * BASE3() from <base3.h> can generate numbers to compare the result to. * * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -int gpio_get_tristates(gpio_t gpio[], int num_gpio); +int gpio_base3_value(gpio_t gpio[], int num_gpio); #endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e01d347..f0f73f2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -88,7 +88,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c +ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/lib/gpio.c b/src/lib/gpio.c new file mode 100644 index 0000000..3a646e0 --- /dev/null +++ b/src/lib/gpio.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <base3.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +int gpio_base3_value(gpio_t gpio[], int num_gpio) +{ + /* + * GPIOs which are tied to stronger external pull up or pull down + * will stay there regardless of the internal pull up or pull + * down setting. + * + * GPIOs which are floating will go to whatever level they're + * internally pulled to. + */ + + static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; + int temp; + int index; + int result = 0; + char value[num_gpio]; + + /* Enable internal pull up */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pullup(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* Get gpio values at internal pull up */ + for (index = 0; index < num_gpio; ++index) + value[index] = gpio_get(gpio[index]); + + /* Enable internal pull down */ + for (index = 0; index < num_gpio; ++index) + gpio_input_pulldown(gpio[index]); + + /* Wait until signals become stable */ + udelay(10); + + /* + * Get gpio values at internal pull down. + * Compare with gpio pull up value and then + * determine a gpio final value/state: + * 0: pull down + * 1: pull up + * 2: floating + */ + printk(BIOS_DEBUG, "Reading tristate GPIOs: "); + for (index = num_gpio - 1; index >= 0; --index) { + temp = gpio_get(gpio[index]); + temp |= ((value[index] ^ temp) << 1); + printk(BIOS_DEBUG, "%c ", tristate_char[temp]); + result = (result * 3) + temp; + } + printk(BIOS_DEBUG, "= %d\n", result); + + /* Disable pull up / pull down to conserve power */ + for (index = 0; index < num_gpio; ++index) + gpio_input(gpio[index]); + + return result; +} diff --git a/src/lib/tristate_gpios.c b/src/lib/tristate_gpios.c deleted file mode 100644 index 0967a8f..0000000 --- a/src/lib/tristate_gpios.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <base3.h> -#include <console/console.h> -#include <delay.h> -#include <gpio.h> - -int gpio_get_tristates(gpio_t gpio[], int num_gpio) -{ - /* - * GPIOs which are tied to stronger external pull up or pull down - * will stay there regardless of the internal pull up or pull - * down setting. - * - * GPIOs which are floating will go to whatever level they're - * internally pulled to. - */ - - static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; - int temp; - int index; - int id = 0; - char value[num_gpio]; - - /* Enable internal pull up */ - for (index = 0; index < num_gpio; ++index) - gpio_input_pullup(gpio[index]); - - /* Wait until signals become stable */ - udelay(10); - - /* Get gpio values at internal pull up */ - for (index = 0; index < num_gpio; ++index) - value[index] = gpio_get(gpio[index]); - - /* Enable internal pull down */ - for (index = 0; index < num_gpio; ++index) - gpio_input_pulldown(gpio[index]); - - /* Wait until signals become stable */ - udelay(10); - - /* - * Get gpio values at internal pull down. - * Compare with gpio pull up value and then - * determine a gpio final value/state: - * 0: pull down - * 1: pull up - * 2: floating - */ - printk(BIOS_DEBUG, "Reading tristate GPIOs: "); - for (index = num_gpio - 1; index >= 0; --index) { - temp = gpio_get(gpio[index]); - temp |= ((value[index] ^ temp) << 1); - printk(BIOS_DEBUG, "%c ", tristate_char[temp]); - id = (id * 3) + temp; - } - printk(BIOS_DEBUG, "= %d\n", id); - - /* Disable pull up / pull down to conserve power */ - for (index = 0; index < num_gpio; ++index) - gpio_input(gpio[index]); - - return id; -} diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index b420f5a..1905c79 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -29,7 +29,7 @@ uint8_t board_id(void) [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index b420f5a..1905c79 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -29,7 +29,7 @@ uint8_t board_id(void) [1] = GPIO(T1), [0] = GPIO(Q3),}; /* Q3 is LSB */ if (id < 0) { - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); printk(BIOS_SPEW, "Board TRISTATE ID: %d.\n", id); } diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c index 37f6292..9c4d184 100644 --- a/src/mainboard/google/rush_ryu/boardid.c +++ b/src/mainboard/google/rush_ryu/boardid.c @@ -30,7 +30,7 @@ uint8_t board_id(void) if (id < 0) { gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - id = gpio_get_tristates(gpio, ARRAY_SIZE(gpio)); + id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); } return id; diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index c32567e..c4f54a5 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -25,8 +25,8 @@ /* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 * and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by - * gpio_get_tristates(), whereas the other two pins are not connected - * and read as 'two'. This results in gpio_get_tristates() returning + * gpio_base3_value(), whereas the other two pins are not connected + * and read as 'two'. This results in gpio_base3_value() returning * 8 on proto0. * * Three tertitiary signals could represent 27 different values. To make @@ -45,7 +45,7 @@ static uint8_t get_board_id(void) gpio_t hw_rev_gpios[] = {[2] = 68, [1] = 30, [0] = 29}; /* 29 is LSB */ int offset = 19; - bid = gpio_get_tristates(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); + bid = gpio_base3_value(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios)); bid = (bid + offset) % 27; printk(BIOS_INFO, "Board ID %d\n", bid);

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Patch set updated for coreboot: a7ae1d6 gpio: add a function to read GPIO array as base-2 value
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9412 -gerrit commit a7ae1d6f1f63a0315aab5304c53760ed2c78cbbd Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:05:35 2014 -0800 gpio: add a function to read GPIO array as base-2 value This adds gpio_base2_value() which reads an array of 2-state GPIOs and returns a base-2 value, where gpio[0] represents the least significant bit. BUG=none BRANCH=none TEST=tested with follow-up patches for pinky Change-Id: I0d6bfac369da0d68079a38de0988c7b59d269a97 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 27873b7a9ea237d13f0cbafd10033a8d0f821cbe Original-Change-Id: Ia7ffc16eb60e93413c0812573b9cf0999b92828e Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228323 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/gpio.h | 9 +++++++++ src/lib/gpio.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h index e54b156..7b64ebf 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -36,6 +36,15 @@ void gpio_output(gpio_t gpio, int value); /* * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a base-2 digit (LOW = 0, HIGH = 1). + * + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. + * num_gpio: number of pins to read. + */ +int gpio_base2_value(gpio_t gpio[], int num_gpio); + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2). * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5 * BASE3() from <base3.h> can generate numbers to compare the result to. diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 3a646e0..0875538 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -22,6 +22,18 @@ #include <delay.h> #include <gpio.h> +int gpio_base2_value(gpio_t gpio[], int num_gpio) +{ + int i, result = 0; + + for (i = 0; i < num_gpio; i++) { + gpio_input(gpio[i]); + result |= gpio_get(gpio[i]) << i; + } + + return result; +} + int gpio_base3_value(gpio_t gpio[], int num_gpio) { /*

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Patch set updated for coreboot: e517331 gpio: decouple tristate gpio support from board ID
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9413 -gerrit commit e517331eff58f197fe68c8ddbdaeb502ea320ee1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Nov 5 14:05:56 2014 -0800 gpio: decouple tristate gpio support from board ID This deprecates TERTIARY_BOARD_ID. Instead, a board will set BOARD_ID_SUPPORT (the ones affected already do) which will set GENERIC_GPIO_SUPPORT and compile the generic GPIO library. The user is expected to handle the details of how the ID is encoded. BUG=none BRANCH=none TEST=Compiled for peppy, nyan*, storm, and pinky Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228322 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/Kconfig | 17 +++++++++-------- src/lib/Makefile.inc | 2 +- src/mainboard/google/nyan_big/Kconfig | 1 - src/mainboard/google/nyan_blaze/Kconfig | 1 - src/mainboard/google/rush_ryu/Kconfig | 1 - src/mainboard/google/storm/Kconfig | 1 - 6 files changed, 10 insertions(+), 13 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cc87aec..60c3e7c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1107,22 +1107,23 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config GENERIC_GPIO_LIB + bool "Build generic GPIO library" + default n + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + config BOARD_ID_SUPPORT bool "Discover board ID and store it in coreboot table" default n + select GENERIC_GPIO_LIB help If enabled, coreboot discovers the board id of the hardware it is running on and reports it through the coreboot table to the rest of the system. -config TERTIARY_BOARD_ID - bool "Interpret board ID GPIOs as tertiary inputs" - default n - depends on BOARD_ID_SUPPORT - help - Consider each GPIO as being in one of three states: pulled down (0), - pulled up (1), or not connected (2) - endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f0f73f2..bcec089 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -88,7 +88,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -ramstage-$(CONFIG_TERTIARY_BOARD_ID) += gpio.c +ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 7334472..22958a9 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH - select TERTIARY_BOARD_ID config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 3495919..0902b4f 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B - select TERTIARY_BOARD_ID select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 6fb21fb..b1f4f32 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_4096 select VIRTUAL_DEV_SWITCH - select TERTIARY_BOARD_ID select ARCH_SPINTABLE config MAINBOARD_DIR diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3e1e016..5e010fc 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_BOOTBLOCK_INIT select SPI_FLASH select SPI_FLASH_SPANSION - select TERTIARY_BOARD_ID config BOARD_VARIANT_AP148 bool "pick this to build an image for ap148"

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Patch set updated for coreboot: eb9dc6a gpio: compile gpio.c at all stages
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9414 -gerrit commit eb9dc6aa2029f8e328f03c33b7ef73d317499e00 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 6 15:22:10 2014 -0800 gpio: compile gpio.c at all stages Since gpio.c is more generic now and will be used in various stages (ie for board_id()), compile it for all stages. BUG=none BRANCH=none TEST=compiled for peppy and veyron_pinky Change-Id: Ib5c73f68db92791dd6b42369f681f9159b7e1c22 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ef4e40ccf6510d63c4a54451bdfea8da695e387e Original-Change-Id: I77ec56a77e75e602e8b9406524d36a8f69ce9128 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228325 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index bcec089..d883760 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c @@ -34,6 +35,7 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c verstage-y += tlcl.c verstage-$(CONFIG_GENERIC_UDELAY) += timer.c +verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += prog_ops.c romstage-y += memchr.c @@ -49,6 +51,7 @@ romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c +romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

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Patch set updated for coreboot: 505df3b urara: bimgtool now uses CRC 16 instead of CRC x25.
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9415 -gerrit commit 505df3b30c24959c15afe2248e6ce8a31dfaa241 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Oct 31 17:21:41 2014 +0000 urara: bimgtool now uses CRC 16 instead of CRC x25. Switched to CRC 16 as it's 40% faster than CRC x25. Both CRC 16 and CRC x25 are supported and either can be selected through define directives. BUG=chrome-os-partner:31438 TEST=built urara bootblock and verified content of bootblock.bin, observed expected content; ran it on Pistachio FPGA and observed that its content is read properly by bootrom. BRANCH=none Change-Id: I36dec6ec2d6616343f97cc8b6486c0a3e4ea49ba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6d9318097ca9270bc245e7de4aff5f78dfbc1606 Original-Change-Id: If1a78350e0b48d91bfe64ead45f852f44ba3cf9a Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226840 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/bimgtool/bimgtool.c | 98 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 90 insertions(+), 8 deletions(-) diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c index 72de6db..c8ab9bb 100644 --- a/util/bimgtool/bimgtool.c +++ b/util/bimgtool/bimgtool.c @@ -40,9 +40,18 @@ struct bimg_header { struct bimg_data_header { uint32_t size; uint32_t dest_addr; + uint16_t dummy; uint16_t crc; } __attribute__((packed)); +struct crc_t { + uint16_t (*crc_f)(uint16_t crc, void *void_buf, size_t size); + uint32_t crc_init; + uint16_t ver_major; + uint16_t ver_minor; +}; + + #define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ #define BIMG_OP_MASK (0xf << 0) @@ -52,7 +61,7 @@ struct bimg_data_header { #define MAX_RECORD_BYTES 0x8000 -#define CRC_INIT 0xffff +#define CRC_16 #define error(msg...) fprintf(stderr, "ERROR: " msg) @@ -80,6 +89,72 @@ static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) return crc; } +static uint16_t crc_16(uint16_t crc, void *void_buf, size_t size) +{ + /* + * CRC table for the CRC-16. + * The poly is 0x8005 (x^16 + x^15 + x^2 + 1) + */ + static const uint16_t crc16_table[256] = { + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 + }; + uint8_t *buf, data; + + for (buf = void_buf; size; size--) { + data = *buf++; + crc = (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff]; + } + + return crc; + +} + + +static struct crc_t crc_type = { +#if defined(CRC_16) + .crc_f = crc_16, + .crc_init = 0, + .ver_major = 2, + .ver_minor = 0 +#elif defined(CRC_X25) + .crc_f = crc_x25, + .crc_init = 0xffff, + .ver_major = 1, + .ver_minor = 0 +#endif +}; + static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) { static uint8_t file_buf[MAX_RECORD_BYTES]; @@ -88,8 +163,13 @@ static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) data_hdr.dest_addr = hdr->entry_addr; + /* + * The read binary data has to be split in chunks of max 64KB-1 bytes + * (SPI controller limitation). Each chunk will have its own header in + * order to respect the BIMG format. + */ while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { - data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, sizeof(data_hdr) - sizeof(data_hdr.crc)); if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) @@ -103,7 +183,8 @@ static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) data_hdr.dest_addr += n_written; hdr->data_size += sizeof(data_hdr) + n_written; - hdr->data_crc = crc_x25(hdr->data_crc, file_buf, n_written); + hdr->data_crc = crc_type.crc_f(hdr->data_crc, + file_buf, n_written); } if (ferror(in)) @@ -119,7 +200,7 @@ static int write_final(FILE *out, struct bimg_header *hdr) .dest_addr = ~0, }; - data_hdr.crc = crc_x25(CRC_INIT, &data_hdr, + data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, sizeof(data_hdr) - sizeof(data_hdr.crc)); if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) @@ -153,10 +234,10 @@ int main(int argc, char *argv[]) int err; struct bimg_header hdr = { .magic = BIMG_MAGIC, - .ver_major = 1, - .ver_minor = 0, + .ver_major = crc_type.ver_major, + .ver_minor = crc_type.ver_minor, .flags = BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM, - .data_crc = CRC_INIT, + .data_crc = crc_type.crc_init, }; if (argc != 4) { @@ -197,7 +278,8 @@ int main(int argc, char *argv[]) goto out_err_close_out; } - hdr.crc = crc_x25(CRC_INIT, &hdr, sizeof(hdr) - sizeof(hdr.crc)); + hdr.crc = crc_type.crc_f(crc_type.crc_init, &hdr, + sizeof(hdr) - sizeof(hdr.crc)); if (fseek(out_file, 0, SEEK_SET)) { error("Failed to seek to header: %d\n", errno);

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New patch to review for coreboot: c57610a AMD Avalon: add firmwares
by WANG Siyuan 08 Apr '15

08 Apr '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9416 -gerrit commit c57610a6be04a7b53eb02baf15fe3c8db7208ee4 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 8 18:51:15 2015 +0800 AMD Avalon: add firmwares trustlets.bin and Trustlet.tkn.cert are necessary for binary PI <Change-Id: I7c413c> Change-Id: I03c612fc49ddc77777a70cc7a1a8d297b9786bc8 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 32 +++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c66d541..de172fb 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -207,10 +207,22 @@ SMUFWM_POS=$(call int-align, \ $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) +## 12 +CONFIG_TRUSTLET_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLET_POS=$(call int-align, \ + $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_SIZE=$(call file-size,$(CONFIG_TRUSTLET_FILE)) +## 13 +CONFIG_TRUSTLET_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +TRUSTLET_KEY_POS=$(call int-align, \ + $(call int-add,$(TRUSTLET_POS) $(TRUSTLET_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_KEY_SIZE=$(call file-size,$(CONFIG_TRUSTLET_KEY_FILE)) CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(TRUSTLET_KEY_POS) $(TRUSTLET_KEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) @@ -241,6 +253,12 @@ $(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp + for fwm in 12 $(TRUSTLET_SIZE) $(TRUSTLET_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp + for fwm in 13 $(TRUSTLET_KEY_SIZE) $(TRUSTLET_KEY_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp @@ -300,6 +318,18 @@ apu/smufwm-file := $(CONFIG_SMUFWM_FILE) apu/smufwm-position := $(SMUFWM_POS) apu/smufwm-type := raw +#12 +cbfs-files-y += apu/trustlet +apu/trustlet-file := $(CONFIG_TRUSTLET_FILE) +apu/trustlet-position := $(TRUSTLET_POS) +apu/trustlet-type := raw + +#13 +cbfs-files-y += apu/trustlet_key +apu/trustlet_key-file := $(CONFIG_TRUSTLET_KEY_FILE) +apu/trustlet_key-position := $(TRUSTLET_KEY_POS) +apu/trustlet_key-type := raw + cbfs-files-y += apu/smuscs apu/smuscs-file := $(CONFIG_SMUSCS_FILE) apu/smuscs-position := $(SMUSCS_POS)

1 0

Patch set updated for coreboot: 9ecaa77 armv7-m: set stack pointer to _estack
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9384 -gerrit commit 9ecaa773b147c2f0cadde021291c1adc6e841809 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Oct 24 09:38:31 2014 -0700 armv7-m: set stack pointer to _estack this change sets the stack pointer to the value specified in memlayout.ld before jumping to the bootblock. BUG=none BRANCH=ToT TEST=Built cosmos and all other current boards. Change-Id: Ic1b790f27bce431124ba70cc2d3d3607c537564b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d50fd02db8bf10147fd808f3030e6297b9ca0aad Original-Change-Id: I4bb8cea7435d2a0e2c1ced050c3366d2e636cb8a Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225420 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/arm/armv7/bootblock_m.S | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S index 0a29a0b..2e46ca0 100644 --- a/src/arch/arm/armv7/bootblock_m.S +++ b/src/arch/arm/armv7/bootblock_m.S @@ -31,5 +31,20 @@ #include <arch/asm.h> ENTRY(_start) + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +call_bootblock: + ldr sp, =_estack /* Set up stack pointer */ bl main ENDPROC(_start)

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Patch set updated for coreboot: 32b166a armv7-m: add bootblock entry point
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9382 -gerrit commit 32b166ae626bb451e5404a26e807bc3d90d46dd7 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 23 11:51:18 2014 -0700 armv7-m: add bootblock entry point this adds an entry point jumping to main for the bootblock. BUG=None BRANCH=ToT TEST=Built coreboot for cosmos Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I1c9ea6ba63a1058e09613d969fe00308260037be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 662d0083f25008b55b9bc5fbce9e30e6b80c2c65 Original-Change-Id: I74f2f5e3b3961ab54a7913e6b3a3ab0e6fd813a3 Original-Reviewed-on: https://chromium-review.googlesource.com/225205 Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 1 + src/arch/arm/armv7/bootblock_m.S | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index ab7f554..ba962e9 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -51,6 +51,7 @@ bootblock-c-ccopts += $(armv7-m_flags) bootblock-S-ccopts += $(armv7-m_asm_flags) ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) +bootblock-y += bootblock_m.S bootblock-y += bootblock_simple.c endif bootblock-y += exception_m.c diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S new file mode 100644 index 0000000..0a29a0b --- /dev/null +++ b/src/arch/arm/armv7/bootblock_m.S @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <arch/asm.h> + +ENTRY(_start) + bl main +ENDPROC(_start)

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Patch set updated for coreboot: affd648 armv7-m: add empty cache routines
by Patrick Georgi 08 Apr '15

08 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9383 -gerrit commit affd64809ca4f5f30ab1f1519831bcc4c5c6e30b Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Oct 23 12:39:11 2014 -0700 armv7-m: add empty cache routines armv7-m does not have cache but adding empty cache functions allow us to transparently use code handling entering and leaving stages. BUG=none BRANCH=ToT TEST=Built coreboot for cosmos Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I23415b273c90401cd81f2bc94b2d69958f134c6a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 960453bf5d5fbf7dc75343b1cccaa62b6b8ec30c Original-Change-Id: Ief0c8a949e7e14d68473e7a093a8642d6058ccc6 Original-Reviewed-on: https://chromium-review.googlesource.com/225206 Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 3 +- src/arch/arm/armv7/cache_m.c | 79 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 951118a..ab7f554 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -52,8 +52,9 @@ bootblock-S-ccopts += $(armv7-m_asm_flags) ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock_simple.c -bootblock-y += exception_m.c endif +bootblock-y += exception_m.c +bootblock-y += cache_m.c endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c new file mode 100644 index 0000000..ec8a970 --- /dev/null +++ b/src/arch/arm/armv7/cache_m.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-M + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ +} + +void dcache_clean_all(void) +{ +} + +void dcache_clean_invalidate_all(void) +{ +} + +void dcache_invalidate_all(void) +{ +} + +unsigned int dcache_line_bytes(void) +{ + return 0; +} + +void dcache_clean_by_mva(void const *addr, size_t len) +{ +} + +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_mmu_disable(void) +{ +} + +void dcache_mmu_enable(void) +{ +} + +void cache_sync_instructions(void) +{ +}

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coreboot-gerrit April 2015