the following patch was just integrated into master:
commit e5e36306a9a5bf96ab8cc990d93bbd62030e635f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Sep 25 10:05:15 2014 -0500
timer: Add generic udelay() implementation
Add GENERIC_UDELAY Kconfig option so that a generic
udelay() implementation is provided utilizing the
monotonic timer. That way each board/chipset doesn't
need to duplicate the same udelay(). Additionally,
assume that GENERIC_UDELAY implies init_timer()
is not required.
BUG=None
BRANCH=None
TEST=Built nyan, ryu, and rambi. May need help testing.
Change-Id: I7f511a2324b5aa5d1b2959f4519be85a6a7360e8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 1a85fbcad778933d13eaef545135abe7e4de46ed
Original-Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219719
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9334 for details.
-gerrit
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9432
-gerrit
commit 29e25254b0945dd965b41c8cbbdcca03c8b0dad2
Author: Furquan Shaikh <furquan(a)google.com>
Date: Sat Oct 4 17:05:50 2014 -0700
rush: Add vboot2 support
CQ-DEPEND=CL:221601, CL:*178568
BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: I50d0475dbe1390b640a726c259364f36abcbebe0
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221579
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
(cherry picked from commit 14e348721399f13a52258faa16769b0ebb5b511f)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I2683cb29c7a93f3f4aba0d7b9a56a1ca209518a0
---
src/mainboard/google/rush/Kconfig | 5 +++-
src/mainboard/google/rush/Makefile.inc | 5 ++++
src/mainboard/google/rush/memlayout.ld | 4 +++
src/mainboard/google/rush/verstage.c | 51 ++++++++++++++++++++++++++++++++++
4 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index 94cbed1..95597b0 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -78,9 +78,12 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
help
Which chip select to use for boot media.
+# For rush, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x3
config DRIVER_TPM_I2C_BUS
hex
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index e41745f..a4d0135 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -31,6 +31,10 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
+verstage-y += verstage.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -44,3 +48,4 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 85f4a97..5bd72e5 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1 +1,5 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
#include <soc/memlayout_vboot.ld>
+#endif
diff --git a/src/mainboard/google/rush/verstage.c b/src/mainboard/google/rush/verstage.c
new file mode 100644
index 0000000..0150e46
--- /dev/null
+++ b/src/mainboard/google/rush/verstage.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/verstage.h>
+#include <soc/nvidia/tegra/i2c.h>
+
+static const struct pad_config i2cpad[] = {
+ /* TPM I2C */
+ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct pad_config spipad[] = {
+ /* EC on SPI1: mosi, miso, clk, cs */
+ PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
+};
+
+static const struct funit_cfg funitcfgs[] = {
+ FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
+ FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
+};
+
+void verstage_mainboard_init(void)
+{
+ soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
+
+ /* TPM I2C bus */
+ i2c_init(2);
+}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9431
-gerrit
commit a28ddd35c71a0b985f461d27337978a96762b365
Author: Furquan Shaikh <furquan(a)google.com>
Date: Sat Oct 4 17:01:48 2014 -0700
ryu: Add vboot2 support
CQ-DEPEND=CL:221598, CL:*178568
BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles and boots to kernel prompt
Original-Change-Id: If7c725333b45a92f951ab674c3e4bd6a51c180c2
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221577
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
(cherry picked from commit 9f5a6ae8cb6e7136ab0f0158a864dfc8ccf5c24f)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: If83dece2b4f2aa7d1457c723131efaa9b1169009
---
src/mainboard/google/rush_ryu/Kconfig | 5 ++-
src/mainboard/google/rush_ryu/Makefile.inc | 5 +++
src/mainboard/google/rush_ryu/memlayout.ld | 4 +++
src/mainboard/google/rush_ryu/verstage.c | 53 ++++++++++++++++++++++++++++++
4 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig
index 6fb21fb..a824f2e 100644
--- a/src/mainboard/google/rush_ryu/Kconfig
+++ b/src/mainboard/google/rush_ryu/Kconfig
@@ -76,9 +76,12 @@ config BOOT_MEDIA_SPI_CHIP_SELECT
help
Which chip select to use for boot media.
+# For ryu, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
config VBOOT_RAMSTAGE_INDEX
hex
- default 0x2
+ default 0x3
config DRIVER_TPM_I2C_BUS
hex
diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc
index 67a3fac..3b71c79 100644
--- a/src/mainboard/google/rush_ryu/Makefile.inc
+++ b/src/mainboard/google/rush_ryu/Makefile.inc
@@ -31,6 +31,10 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
+verstage-y += verstage.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
romstage-y += chromeos.c
romstage-y += pmic.c
romstage-y += reset.c
@@ -45,3 +49,4 @@ ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index 85f4a97..5bd72e5 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1 +1,5 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
#include <soc/memlayout_vboot.ld>
+#endif
diff --git a/src/mainboard/google/rush_ryu/verstage.c b/src/mainboard/google/rush_ryu/verstage.c
new file mode 100644
index 0000000..ed83f03
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/verstage.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/verstage.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include "gpio.h"
+#include "pmic.h"
+
+static const struct pad_config tpm_pads[] = {
+ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+static const struct pad_config ec_i2c_pads[] = {
+ PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
+ PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
+};
+
+static const struct funit_cfg funits[] = {
+ /* TPM on I2C3 @ 400kHz */
+ FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
+ /* EC on I2C2 - pulled to 3.3V @ 100kHz */
+ FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
+};
+
+void verstage_mainboard_init(void)
+{
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
+
+ /* TPM */
+ i2c_init(I2C3_BUS);
+ /* EC */
+ i2c_init(I2C2_BUS);
+}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9430
-gerrit
commit 4225d9368290324c06fb151cff3aed4e3c81a6b8
Author: Furquan Shaikh <furquan(a)google.com>
Date: Sat Oct 4 17:00:56 2014 -0700
t132: Add vboot2 support
BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt using vboot2
Original-Change-Id: Ibf7666d273e4d1af719c60d3f02bddcb4461f4bd
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/221576
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
(cherry picked from commit 8335915940ae9ba9e51e360df6963a27b05d6324)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I7d3d5cda4c4be945931d9133ab18680dac1dcefe
---
src/mainboard/google/rush/memlayout.ld | 2 +-
src/mainboard/google/rush_ryu/memlayout.ld | 2 +-
src/soc/nvidia/tegra132/Makefile.inc | 14 +++++++
src/soc/nvidia/tegra132/include/soc/memlayout.ld | 44 ---------------------
.../nvidia/tegra132/include/soc/memlayout_vboot.ld | 43 ++++++++++++++++++++
.../tegra132/include/soc/memlayout_vboot2.ld | 46 ++++++++++++++++++++++
src/soc/nvidia/tegra132/include/soc/verstage.h | 25 ++++++++++++
src/soc/nvidia/tegra132/verstage.c | 39 ++++++++++++++++++
8 files changed, 169 insertions(+), 46 deletions(-)
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index ead7f47..85f4a97 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1 +1 @@
-#include <soc/memlayout.ld>
+#include <soc/memlayout_vboot.ld>
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index ead7f47..85f4a97 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1 +1 @@
-#include <soc/memlayout.ld>
+#include <soc/memlayout_vboot.ld>
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 81d08f5..2806ead 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -21,6 +21,20 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
+verstage-y += verstage.c
+verstage-y += cbfs.c
+verstage-y += dma.c
+verstage-y += monotonic_timer.c
+verstage-y += spi.c
+verstage-y += padconfig.c
+verstage-y += funitcfg.c
+verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
+verstage-y += ../tegra/gpio.c
+verstage-y += ../tegra/i2c.c
+verstage-y += ../tegra/pinmux.c
+verstage-y += clock.c
+verstage-y += i2c.c
+
romstage-y += 32bit_reset.S
romstage-y += romstage_asm.S
romstage-y += addressmap.c
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
deleted file mode 100644
index 63cf4f0..0000000
--- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
- * so the bootblock loading address must be placed after that. After the
- * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
- * TODO: Did this change on Tegra132? What's the new valid range?
- */
-
-SECTIONS
-{
- SRAM_START(0x40000000)
- /* 16K hole */
- PRERAM_CBMEM_CONSOLE(0x40004000, 8K)
- CBFS_CACHE(0x40006000, 88K)
- STACK(0x4001C000, 16K)
- BOOTBLOCK(0x40020000, 20K)
- ROMSTAGE(0x40025000, 108K)
- SRAM_END(0x40040000)
-
- DRAM_START(0x80000000)
- RAMSTAGE(0x80200000, 192K)
-}
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
new file mode 100644
index 0000000..c097c3c
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that. After the
+ * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
+ * TODO: Did this change on Tegra132? What's the new valid range?
+ */
+
+SECTIONS
+{
+ SRAM_START(0x40000000)
+ PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
+ CBFS_CACHE(0x40002000, 88K)
+ STACK(0x40018000, 16K)
+ BOOTBLOCK(0x4001C000, 20K)
+ ROMSTAGE(0x40021000, 124K)
+ SRAM_END(0x40040000)
+
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80200000, 192K)
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
new file mode 100644
index 0000000..8743268
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
+ * so the bootblock loading address must be placed after that. After the
+ * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
+ * TODO: Did this change on Tegra132? What's the new valid range?
+ */
+
+SECTIONS
+{
+ SRAM_START(0x40000000)
+ PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
+ CBFS_CACHE(0x40002000, 72K)
+ VBOOT2_WORK(0x40014000, 16K)
+ STACK(0x40018000, 8K)
+ BOOTBLOCK(0x4001A000, 20K)
+ VERSTAGE(0x4001F000, 60K)
+ ROMSTAGE(0x4002E000, 72K)
+ SRAM_END(0x40040000)
+
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80200000, 192K)
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h
new file mode 100644
index 0000000..6901bc3
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/verstage.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
+#define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__
+
+void verstage_mainboard_init(void);
+
+#endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c
new file mode 100644
index 0000000..ba3e183
--- /dev/null
+++ b/src/soc/nvidia/tegra132/verstage.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <console/console.h>
+#include <soc/verstage.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void __attribute__((weak)) verstage_mainboard_init(void)
+{
+ /* Default empty implementation. */
+}
+
+void main(void)
+{
+ console_init();
+ exception_init();
+
+ verstage_mainboard_init();
+
+ vboot2_verify_firmware();
+}