Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9445
-gerrit
commit 393f14b3c6a8333f718ca5023f2cb809bf04e22c
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Dec 1 13:11:52 2014 -0800
vboot2: Reduce minimum required work buffer size
Apparently our initial submission of 16K was a little too generous for
the vboot2 work buffer, and I hear that we should also be well within
bounds for 12K. This patch reduces the minimum asserted by memlayout so
some of our low-mem boards can get a few more kilobytes back for
discretionary spending. Also changes the required minimum alignment to 8
since that's what the current vboot code aligns it to anyway, and add a
warning comment to make it clearer that this is a dangerous number
people should not be playing with lightly.
BRANCH=None
BUG=None
TEST=Built and booted on Pinky.
Original-Change-Id: Iae9c74050500a315c90f5d5517427d755ac1dfea
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232613
Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 64e972f10363451cd544fdf8642bd484463703bc)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I362b8c33cf79534bb76bd7acda44d467563fe133
---
src/vendorcode/google/chromeos/vboot2/memlayout.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/vendorcode/google/chromeos/vboot2/memlayout.h b/src/vendorcode/google/chromeos/vboot2/memlayout.h
index 9e19200..7903dd2 100644
--- a/src/vendorcode/google/chromeos/vboot2/memlayout.h
+++ b/src/vendorcode/google/chromeos/vboot2/memlayout.h
@@ -22,9 +22,12 @@
#ifndef __CHROMEOS_VBOOT2_MEMLAYOUT_H
#define __CHROMEOS_VBOOT2_MEMLAYOUT_H
+/* Careful: required work buffer size depends on RW properties such as key size
+ * and algorithm -- what works for you might stop working after an update. Do
+ * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */
#define VBOOT2_WORK(addr, size) \
- REGION(vboot2_work, addr, size, 4) \
- _ = ASSERT(size >= 16K, "vboot2 work buffer must be at least 16K!");
+ REGION(vboot2_work, addr, size, 8) \
+ _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!");
#ifdef __VERSTAGE__
#define VERSTAGE(addr, sz) \
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9444
-gerrit
commit f906d904d1ef36a5554fb15d3fc71b26207c2248
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Thu Nov 13 11:35:52 2014 -0800
vboot: add physical recovery switch support
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy.
BUG=none
BRANCH=ToT
TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan,
blaze, parrot, rambi, samus, storm, pinky with default configuration.
panther and stumpy are not tested because they currently don't build on ToT.
Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227940
Original-Reviewed-on: https://chromium-review.googlesource.com/229602
Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe
---
src/mainboard/google/panther/Kconfig | 1 +
src/mainboard/samsung/stumpy/Kconfig | 1 +
src/vendorcode/google/chromeos/Kconfig | 6 ++++++
src/vendorcode/google/chromeos/vboot1/vboot_loader.c | 4 ++--
src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 5 +++--
5 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 607b690..5f2efb9 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
select INTEL_INT15
+ select PHYSICAL_REC_SWITCH
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 1b65eae..3f39e70 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_BD82X6X
select SUPERIO_ITE_IT8772F
+ select PHYSICAL_REC_SWITCH
# LPC47N207 selected for external LPC card
# not on board, should be made selectable.
select SUPERIO_SMSC_LPC47N207
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 29252a6..cb15d13 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -159,6 +159,12 @@ config NO_TPM_RESUME
boards, booting Windows will break if the TPM resume command
is sent during an S3 resume.
+config PHYSICAL_REC_SWITCH
+ bool "Physical recovery switch is present"
+ default n
+ help
+ Whether this platform has a physical recovery switch
+
source src/vendorcode/google/chromeos/vboot1/Kconfig
source src/vendorcode/google/chromeos/vboot2/Kconfig
diff --git a/src/vendorcode/google/chromeos/vboot1/vboot_loader.c b/src/vendorcode/google/chromeos/vboot1/vboot_loader.c
index 0353a3a..97ca902 100644
--- a/src/vendorcode/google/chromeos/vboot1/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot1/vboot_loader.c
@@ -226,10 +226,10 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff)
*iflags |= VB_INIT_FLAG_SW_WP_ENABLED;
if (CONFIG_VIRTUAL_DEV_SWITCH)
*iflags |= VB_INIT_FLAG_VIRTUAL_DEV_SWITCH;
- if (CONFIG_EC_SOFTWARE_SYNC) {
+ if (CONFIG_EC_SOFTWARE_SYNC)
*iflags |= VB_INIT_FLAG_EC_SOFTWARE_SYNC;
+ if (!CONFIG_PHYSICAL_REC_SWITCH)
*iflags |= VB_INIT_FLAG_VIRTUAL_REC_SWITCH;
- }
if (CONFIG_VBOOT_EC_SLOW_UPDATE)
*iflags |= VB_INIT_FLAG_EC_SLOW_UPDATE;
if (CONFIG_VBOOT_OPROM_MATTERS) {
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index 326a9bb..2dadffa 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -104,10 +104,11 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
/* TODO: Set these in depthcharge */
if (CONFIG_VIRTUAL_DEV_SWITCH)
vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH;
- if (CONFIG_EC_SOFTWARE_SYNC) {
+ if (CONFIG_EC_SOFTWARE_SYNC)
vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC;
+ if (!CONFIG_PHYSICAL_REC_SWITCH)
vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL;
- }
+
/* In vboot1, VBSD_FWB_TRIED is
* set only if B is booted as explicitly requested. Therefore, if B is
* booted because A was found bad, the flag should not be set. It's
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9438
-gerrit
commit c36932fc873ff333762bd028fae863f21047fbbc
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Mon Nov 3 17:42:09 2014 -0800
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Original-Reviewed-on: https://chromium-review.googlesource.com/227248
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
(cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b
---
src/Kconfig | 7 +++++++
src/include/boardid.h | 1 +
src/include/boot/coreboot_tables.h | 7 +++++++
src/lib/coreboot_table.c | 16 ++++++++++++++++
4 files changed, 31 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index f94fad4..5cc5485 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -253,6 +253,13 @@ config UPDATE_IMAGE
is a suitable file for further processing.
The bootblock will not be modified.
+config RAM_CODE_SUPPORT
+ bool "Discover RAM configuration code and store it in coreboot table"
+ default n
+ help
+ If enabled, coreboot discovers RAM configuration (value obtained by
+ reading board straps) and stores it in coreboot table.
+
endmenu
source "src/mainboard/Kconfig"
diff --git a/src/include/boardid.h b/src/include/boardid.h
index d1c6ad9..41c21d6 100644
--- a/src/include/boardid.h
+++ b/src/include/boardid.h
@@ -23,5 +23,6 @@
#include <stdint.h>
uint8_t board_id(void);
+uint32_t ram_code(void);
#endif /* __INCLUDE_BOARDID_H__ */
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 0efb8fd..d9df787 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -276,6 +276,13 @@ struct lb_macs {
struct mac_address mac_addrs[0];
};
+#define LB_TAG_RAM_CODE 0x0028
+struct lb_ram_code {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t ram_code;
+};
+
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index a8b5edf..a514bb9 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -297,6 +297,19 @@ static void lb_board_id(struct lb_header *header)
#endif
}
+static void lb_ram_code(struct lb_header *header)
+{
+#if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT)
+ struct lb_ram_code *code;
+
+ code = (struct lb_ram_code *)lb_new_record(header);
+
+ code->tag = LB_TAG_RAM_CODE;
+ code->size = sizeof(*code);
+ code->ram_code = ram_code();
+#endif
+}
+
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@@ -525,6 +538,9 @@ unsigned long write_coreboot_table(
/* Add board ID if available */
lb_board_id(head);
+ /* Add RAM config if available */
+ lb_ram_code(head);
+
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9436
-gerrit
commit 32e54f40194f76f51ac5fc3dd9b48df5858c5e45
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Tue Oct 28 18:26:12 2014 -0700
fmap: use CBFS for all other than x86 platforms
The architectiure check in fmap.c is in fact used to delineate between
platforms where SPI flash is mapped to memory address space and where
it needs to be accessed through CBFS.
In fact cosmos board uses an ARM SOC which also maps SPI flash to
processor address space, this will have to be addressed when that
SOC's support is introduced, for now let's just presume that all but
X86 platforms require CBFS layer to access fmap.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=none
Original-Change-Id: Id135dc63278555a7fc5039a568fb28864f7cb8d1
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226180
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit b3c04f84504380066c54a6dec93781a4f25a5fc6)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I3a0a70fe583b69b1c9cd8729817bd7062126e1a9
---
src/vendorcode/google/chromeos/fmap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c
index 7c1f626..7c256ce 100644
--- a/src/vendorcode/google/chromeos/fmap.c
+++ b/src/vendorcode/google/chromeos/fmap.c
@@ -41,7 +41,7 @@ const struct fmap *fmap_find(void)
/* wrapping around 0x100000000 */
const struct fmap *fmap = (void *)
(CONFIG_FLASHMAP_OFFSET - CONFIG_ROM_SIZE);
-#elif CONFIG_ARCH_ARM
+#else
struct cbfs_media default_media, *media;
media = &default_media;
init_default_cbfs_media(media);