the following patch was just integrated into master:
commit f3bc026aca860965e0964b014e6c89333bcd59a6
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Mon Dec 1 18:34:37 2014 -0800
pistachio: add SOC descriptor
With this descriptor added ramstage properly allocates memory
resources and creates entries in coreboot table. This also allows to
proceed to booting depthcharge, as it now can be loaded into the
existing memory.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the set of patches applied the firmware properly finds
depthcharge in CBFS, uncompresses it and attempts to start:
...
Booting payload fallback/payload from cbfs
Loading segment from rom address 0x9b000058
code (compression=1)
New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe
Loading segment from rom address 0x9b000074
Entry Point 0x80124038
Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
lb: [0x0000000080000000, 0x0000000080013858)
Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
using LZMA
[ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090
Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054
dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129
Jumping to boot code at 80124038
ERROR: dropped a timestamp entry
CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes
entry = 80124038
Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf
Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232571
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9192
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9192 for details.
-gerrit
the following patch was just integrated into master:
commit fe51cc4a8dc03f876a48c3014a2e20fe02bca9a3
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Tue Nov 11 20:14:47 2014 -0800
pistachio: modify memory layout
With the code now running on the FPGA board it makes sense to correct
the memory layout definitions to match the actual hardware.
Note that the latest FPGA board firmware introduced support of the
additional 128KB of SRAM (called GRAM) at base address of 0x9a000000.
These are still interim values, which will be tweaked when the actual
bring up board is available.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=the code put into SPI NOR flash boots all the way to ramstage.
Change-Id: I00aa5bc3aabba50df2187bb208cf2fcd11b26b3d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: a6378be5cd304744b40c57a34d7a276233d45779
Original-Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229203
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9337
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9337 for details.
-gerrit
the following patch was just integrated into master:
commit 40ff8a5b889f3cafbd561992f6e75b0d6320585c
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sat Nov 29 15:31:40 2014 -0800
pistachio: set correct CBMEM top address
This is required for proper dynamic CBMEM operation.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=urara ramstage does not crash anymore in CBMEM initialization
Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a
Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232292
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9191
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9191 for details.
-gerrit
the following patch was just integrated into master:
commit cbc44f70121ce1cb788974dd6042782cd8c8756e
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sat Nov 29 15:28:23 2014 -0800
pistachio: allow more room for bootblock
32K is a more appropriate room for Pistachio bootblock.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=there is no bootblock overflow even when compiled with -O0.
Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149
Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232291
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9190
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9190 for details.
-gerrit
the following patch was just integrated into master:
commit 52a887985300cf11fbc183f6a4a4408ff9a45ec6
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Wed Nov 5 17:50:09 2014 -0800
pistachio: implement timer support
C0_COUNT register is a free running counter clocked by the CPU
frequency divided by two. On the FPGA board it results in 25 MHz, on
real SOCs it will have to be figured out later.
Some magic addresses and numbers are used to find out if the code is
running on the FPGA board.
timestamp_get() and timer_monotonic_get() are kept in the same file.
The CPU initialization makes sure that CO COUNT is in fact enabled and
starts from zero.
BRANCH=none
BUG=chrome-os-partner:33595,chrome-os-partner:31438
TEST=with timer enabled, the startup code properly initializes UART
and prints the coreboot bootblock banner message on the serial
console.
Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05
Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227888
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9188
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9188 for details.
-gerrit
the following patch was just integrated into master:
commit 771819a3806b5e60e3db73b2779072ee0f23890f
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Wed Oct 15 18:19:03 2014 -0700
cosmos: rearrange configuration and makefile definitions
This is a no-op aesthetic change, arranging configurarion and makefile
lines alphanumerically.
BRANCH=none
BUG=none
TEST=cosmos still builds
Change-Id: I72b7defca722380dda3ef8453e625f28bdebfa2c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c55a7e9d5064edf5cac9498c8c6c377cbf705bb1
Original-Change-Id: I4498eef59fc20ea04b6ebadb451d0fe346824c05
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223597
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9353
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/9353 for details.
-gerrit
the following patch was just integrated into master:
commit 3df01265d506f1a3f7fd30bb6f19f10724fcc393
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Oct 8 11:38:52 2014 -0700
cosmos: add template for soc and board files
This adds board and soc files as a template for cosmos.
BUG=chrome-os-partner:32772
BRANCH=none
TEST=Built coreboot for cosmos and veyron_pinky.
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: I6e17058afaa629c6aa70c2d195230dba782af526
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fd9dbcf1023a79921c8501bbe09969d65ca9e742
Original-Change-Id: I676bdf460f5dd996dcce1fc422a69882798bc112
Original-Reviewed-on: https://chromium-review.googlesource.com/222050
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9351 for details.
-gerrit
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9447
-gerrit
commit 913152b9f4e89ae7353a97f24287194faf43f7c5
Author: Randall Spangler <rspangler(a)chromium.org>
Date: Thu Dec 4 12:58:54 2014 -0800
vboot: Remove unused 2lib header path
Before the change to use vb2_api.h, coreboot needed to know where to
find the vboot2 header files. Now those are all included by
vb2_api.h, so coreboot doesn't need to know about
firmware/2lib/include (and in fact, the 2lib directory is about to go
away).
BUG=chromium:423882
BRANCH=none
TEST=emerge-veyron_pinky coreboot
Original-Change-Id: I7f69ca9cf8d45c325219efceca0cb8d1340f7736
Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/233223
Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org>
(cherry picked from commit b4d4a2da1c8b5a5f8f8da51f009227d3a616b096)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I4006f38835ea0f927142a8133bc24caaf2b7a214
---
src/vendorcode/google/chromeos/Makefile.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index b42653a..a3747a8 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -52,5 +52,4 @@ endif
VB_SOURCE := vboot_reference
subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot1
subdirs-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += vboot2
-INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include
INCLUDES += -I$(VB_SOURCE)/firmware/include