Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9455
-gerrit
commit 078d9e5aa35200b262fcded2fe87d2b9c7bbaed0
Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Date: Mon Feb 2 15:35:44 2015 +0000
libpayload dwc2: sent address of buffer should be bus address
The address of the output buffer sent to the device should be
the bus address and not the virtual address.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board;
USB works properly after this change
BRANCH=none
Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438
Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245387
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
payloads/libpayload/drivers/usb/dwc2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 0830c9e..1102711 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -253,7 +253,8 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
memcpy(aligned_buf, data_buf, size);
writel(hctsiz.d32, ®->host.hchn[ch_num].hctsizn);
- writel((uint32_t)aligned_buf, ®->host.hchn[ch_num].hcdman);
+ writel((uint32_t)virt_to_bus(aligned_buf),
+ ®->host.hchn[ch_num].hcdman);
writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
ret = wait_for_complete(ep, ch_num);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9454
-gerrit
commit 25853b969f1180e532007af6007d4e308ad64213
Author: huang lin <hl(a)rock-chips.com>
Date: Thu Dec 4 18:25:47 2014 +0800
libpayload dwc2: Use a new FIFO allocation method
Total FIFO length is split into 512 byte blocks,
because the max packet size in coreboot is 512 byte.
Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids hardcoding and make the FIFO size value
work for dwc2 controllers that have a different FIFO ram size.
BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB
Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87
Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233119
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
payloads/libpayload/drivers/usb/dwc2.c | 23 +++++++++++++++++++----
payloads/libpayload/drivers/usb/dwc2_private.h | 16 ++++++++++++++--
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 7af7718..0830c9e 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -35,11 +35,12 @@ static void dwc2_reinit(hci_t *controller)
gintsts_t gintsts = { .d32 = 0 };
gahbcfg_t gahbcfg = { .d32 = 0 };
grxfsiz_t grxfsiz = { .d32 = 0 };
+ ghwcfg3_t hwcfg3 = { .d32 = 0 };
hcintmsk_t hcintmsk = { .d32 = 0 };
gnptxfsiz_t gnptxfsiz = { .d32 = 0 };
const int timeout = 10000;
- int i;
+ int i, fifo_blocks, tx_blocks;
/* Wait for AHB idle */
for (i = 0; i < timeout; i++) {
@@ -86,10 +87,24 @@ static void dwc2_reinit(hci_t *controller)
* The non-periodic tx fifo and rx fifo share one continuous
* piece of IP-internal SRAM.
*/
- grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH;
+
+ /*
+ * Read total data FIFO depth from HWCFG3
+ * this value is in terms of 32-bit words
+ */
+ hwcfg3.d32 = readl(®->core.ghwcfg3);
+ /*
+ * Reserve 2 spaces for the status entries of receive packets
+ * and 2 spaces for bulk an control OUT endpoints. Calculate how
+ * many blocks can be alloted, assume largest packet size is 512.
+ */
+ fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4);
+ tx_blocks = fifo_blocks / 2;
+
+ grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4;
writel(grxfsiz.d32, ®->core.grxfsiz);
- gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH;
- gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH;
+ gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep;
+ gnptxfsiz.nptxfdep = tx_blocks * (512 / 4);
writel(gnptxfsiz.d32, ®->core.gnptxfsiz);
/* Init host channels */
diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h
index 9bd8376..fc658bf 100644
--- a/payloads/libpayload/drivers/usb/dwc2_private.h
+++ b/payloads/libpayload/drivers/usb/dwc2_private.h
@@ -374,7 +374,6 @@ typedef union {
struct {
unsigned nptxfstaddr:16;
unsigned nptxfdep:16;
-#define DWC2_NPTXFIFO_DEPTH 0x80
};
} gnptxfsiz_t;
@@ -390,7 +389,6 @@ typedef union {
*/
struct {
unsigned rxfdep:16;
-#define DWC2_RXFIFO_DEPTH 0x200
unsigned reserved:16;
};
} grxfsiz_t;
@@ -438,6 +436,20 @@ typedef union {
} gintsts_t;
/**
+ * This union represents the bit fields of the User HW Config3 Register
+ * (GHWCFG3).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned reserved:16;
+ unsigned dfifodepth:16;
+ };
+} ghwcfg3_t;
+
+/**
* This union represents the bit fields in the Host Configuration Register.
*/
typedef union {
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9425
-gerrit
commit 36e1ad262dcbb82369c591f5bcc24f0f43e4bc09
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed Nov 12 16:23:00 2014 -0800
rtc: Add an RTC driver for the TI TPS65913 PMIC.
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39
Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229414
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/drivers/ti/Kconfig | 1 +
src/drivers/ti/Makefile.inc | 2 +
src/drivers/ti/tps65913/Kconfig | 35 ++++++++
src/drivers/ti/tps65913/Makefile.inc | 20 +++++
src/drivers/ti/tps65913/tps65913rtc.c | 155 ++++++++++++++++++++++++++++++++++
5 files changed, 213 insertions(+)
diff --git a/src/drivers/ti/Kconfig b/src/drivers/ti/Kconfig
index b3aded8..42ead03 100644
--- a/src/drivers/ti/Kconfig
+++ b/src/drivers/ti/Kconfig
@@ -18,3 +18,4 @@
##
source src/drivers/ti/tps65090/Kconfig
+source src/drivers/ti/tps65913/Kconfig
diff --git a/src/drivers/ti/Makefile.inc b/src/drivers/ti/Makefile.inc
index c0ed9c0..037da94 100644
--- a/src/drivers/ti/Makefile.inc
+++ b/src/drivers/ti/Makefile.inc
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2012 The Chromium OS Authors.
+## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -18,3 +19,4 @@
##
subdirs-$(CONFIG_DRIVER_TI_TPS65090) += tps65090/
+subdirs-$(CONFIG_DRIVERS_TI_TPS65913) += tps65913/
diff --git a/src/drivers/ti/tps65913/Kconfig b/src/drivers/ti/tps65913/Kconfig
new file mode 100644
index 0000000..bd24bae
--- /dev/null
+++ b/src/drivers/ti/tps65913/Kconfig
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config DRIVERS_TI_TPS65913
+ bool "TI TPS65913 support"
+ default n
+
+config DRIVERS_TI_TPS65913_RTC
+ bool "TI TPS65913 RTC support"
+ default n
+ select DRIVERS_TI_TPS65913
+
+config DRIVERS_TI_TPS65913_RTC_BUS
+ int "TI TPS65913 RTC bus"
+ depends on DRIVERS_TI_TPS65913_RTC
+
+config DRIVERS_TI_TPS65913_RTC_ADDR
+ hex "TI TPS65913 RTC chip address"
+ depends on DRIVERS_TI_TPS65913_RTC
diff --git a/src/drivers/ti/tps65913/Makefile.inc b/src/drivers/ti/tps65913/Makefile.inc
new file mode 100644
index 0000000..272b026
--- /dev/null
+++ b/src/drivers/ti/tps65913/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_DRIVERS_TI_TPS65913_RTC) += tps65913rtc.c
diff --git a/src/drivers/ti/tps65913/tps65913rtc.c b/src/drivers/ti/tps65913/tps65913rtc.c
new file mode 100644
index 0000000..46dd4f9
--- /dev/null
+++ b/src/drivers/ti/tps65913/tps65913rtc.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <bcd.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <rtc.h>
+#include <stdint.h>
+
+enum TPS65913_RTC_REG {
+ TPS65913_SECONDS_REG = 0x00,
+ TPS65913_MINUTES_REG = 0x01,
+ TPS65913_HOURS_REG = 0x02,
+ TPS65913_DAYS_REG = 0x03,
+ TPS65913_MONTHS_REG = 0x04,
+ TPS65913_YEARS_REG = 0x05,
+ TPS65913_WEEKS_REG = 0x06,
+ TPS65913_RTC_CTRL_REG = 0x10,
+ TPS65913_RTC_STATUS_REG = 0x11,
+ TPS65913_RTC_INTERRUPS_REG = 0x12,
+};
+
+enum {
+ TPS65913_RTC_CTRL_STOP = (1 << 0),
+ TPS65913_RTC_CTRL_GET_TIME = (1 << 6),
+
+ TPS65913_RTC_STATUS_RUN = (1 << 1),
+ TPS65913_RTC_RUNNING = (1 << 1),
+ TPS65913_RTC_FROZEN = (0 << 1),
+};
+
+static inline uint8_t tps65913_read(enum TPS65913_RTC_REG reg)
+{
+ uint8_t val;
+ i2c_readb(CONFIG_DRIVERS_TI_TPS65913_RTC_BUS,
+ CONFIG_DRIVERS_TI_TPS65913_RTC_ADDR, reg, &val);
+ return val;
+}
+
+static inline void tps65913_write(enum TPS65913_RTC_REG reg, uint8_t val)
+{
+ i2c_writeb(CONFIG_DRIVERS_TI_TPS65913_RTC_BUS,
+ CONFIG_DRIVERS_TI_TPS65913_RTC_ADDR, reg, val);
+}
+
+static void tps65913_rtc_ctrl_clear(uint8_t bit)
+{
+ uint8_t control = tps65913_read(TPS65913_RTC_CTRL_REG);
+
+ control &= ~bit;
+ tps65913_write(TPS65913_RTC_CTRL_REG, control);
+}
+
+static void tps65913_rtc_ctrl_set(uint8_t bit)
+{
+ uint8_t control = tps65913_read(TPS65913_RTC_CTRL_REG);
+
+ control |= TPS65913_RTC_CTRL_GET_TIME;
+ tps65913_write(TPS65913_RTC_CTRL_REG, control);
+}
+
+static int tps65913_is_rtc_running(void)
+{
+ uint8_t status = tps65913_read(TPS65913_RTC_STATUS_REG);
+ return ((status & TPS65913_RTC_STATUS_RUN) == TPS65913_RTC_RUNNING);
+}
+
+/*
+ * This function ensures that current time is copied to shadow registers. Then a
+ * normal read on TC registers reads from the shadow instead of current TC
+ * registers. This helps prevent the accidental change in counters while
+ * reading. In order to ensure that the current TC registers are copied into
+ * shadow registers, GET_TIME bit needs to be set to 0 and then to 1.
+ */
+static void tps65913_rtc_shadow(void)
+{
+ tps65913_rtc_ctrl_clear(TPS65913_RTC_CTRL_GET_TIME);
+ tps65913_rtc_ctrl_set(TPS65913_RTC_CTRL_GET_TIME);
+}
+
+static int tps65913_rtc_stop(void)
+{
+ /* Clearing stop bit freezes RTC */
+ tps65913_rtc_ctrl_clear(TPS65913_RTC_CTRL_STOP);
+
+ if (tps65913_is_rtc_running()) {
+ printk(BIOS_ERR, "Could not stop RTC\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static int tps65913_rtc_start(void)
+{
+ /* Setting stop bit starts RTC */
+ tps65913_rtc_ctrl_set(TPS65913_RTC_CTRL_STOP);
+
+ if (!tps65913_is_rtc_running()) {
+ printk(BIOS_ERR, "Could not start RTC\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int rtc_set(const struct rtc_time *time)
+{
+ /* Before setting the time, ensure that rtc is stopped */
+ if (tps65913_rtc_stop())
+ return 1;
+
+ tps65913_write(TPS65913_SECONDS_REG, bin2bcd(time->sec));
+ tps65913_write(TPS65913_MINUTES_REG, bin2bcd(time->min));
+ tps65913_write(TPS65913_HOURS_REG, bin2bcd(time->hour));
+ tps65913_write(TPS65913_DAYS_REG, bin2bcd(time->mday));
+ tps65913_write(TPS65913_MONTHS_REG, bin2bcd(time->mon));
+ tps65913_write(TPS65913_YEARS_REG, bin2bcd(time->year));
+
+ /* Re-start rtc */
+ if (tps65913_rtc_start())
+ return 1;
+
+ return 0;
+}
+
+int rtc_get(struct rtc_time *time)
+{
+ tps65913_rtc_shadow();
+
+ time->sec = bcd2bin(tps65913_read(TPS65913_SECONDS_REG) & 0x7f);
+ time->min = bcd2bin(tps65913_read(TPS65913_MINUTES_REG) & 0x7f);
+ time->hour = bcd2bin(tps65913_read(TPS65913_HOURS_REG) & 0x3f);
+ time->mday = bcd2bin(tps65913_read(TPS65913_DAYS_REG) & 0x3f);
+ time->mon = bcd2bin(tps65913_read(TPS65913_MONTHS_REG) & 0x1f);
+ time->year = bcd2bin(tps65913_read(TPS65913_YEARS_REG) & 0xff);
+
+ return 0;
+}