Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9457
-gerrit
commit 9d2cb122aea1153addb11768586e7e2b51a1344d
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Apr 9 18:15:09 2015 +0200
util/xcompile/xcompile: Allow to override `HOSTCC` variable
Currently `xcompile` generates `.xcompile` with the following at the
top.
# platform agnostic and host tools
IASL:=iasl
HOSTCC:=gcc
The assignment `:=` doesn’t allow to override the variable. So use `?=`
instead so the host compiler can be passed to coreboot.
HOSTCC=gcc-5 make
Note, that this is just a hack, as the existence of `gcc` is checked
beforehand.
Change-Id: Iebf3e43eb7eaffa7cf0efe97710d9feb3fe2a989
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
util/xcompile/xcompile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 5809ec0..6821533 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -63,7 +63,7 @@ fi
cat <<EOF
# platform agnostic and host tools
IASL:=${IASL}
-HOSTCC:=${HOSTCC}
+HOSTCC?=${HOSTCC}
EOF
the following patch was just integrated into master:
commit b95be26096d81832620e4768c223887f69de118b
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Apr 9 15:50:38 2015 +0200
bg4cd: drop init_timer() stub
It's already in delay.h.
Change-Id: I41087604439aa0bcb8310cf6465f1a3d563d0b58
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9456
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/9456 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9456
-gerrit
commit 54b3c343bf1db0e3f45a029e4be4df3c44d0d8e1
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Apr 9 15:50:38 2015 +0200
bg4cd: drop init_timer() stub
It's already in delay.h.
Change-Id: I41087604439aa0bcb8310cf6465f1a3d563d0b58
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/soc/marvell/bg4cd/monotonic_timer.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/soc/marvell/bg4cd/monotonic_timer.c b/src/soc/marvell/bg4cd/monotonic_timer.c
index a84b036..195a9c3 100644
--- a/src/soc/marvell/bg4cd/monotonic_timer.c
+++ b/src/soc/marvell/bg4cd/monotonic_timer.c
@@ -23,7 +23,3 @@
void timer_monotonic_get(struct mono_time *mt)
{
}
-
-void init_timer(void)
-{
-}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9454
-gerrit
commit 3b6403b7c9aef50762375cc55de0bd1aef55b97e
Author: huang lin <hl(a)rock-chips.com>
Date: Thu Dec 4 18:25:47 2014 +0800
libpayload dwc2: Use a new FIFO allocation method
Total FIFO length is split into 512 byte blocks,
because the max packet size in coreboot is 512 byte.
Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids hardcoding and make the FIFO size value
work for dwc2 controllers that have a different FIFO ram size.
BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB
Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87
Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233119
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
payloads/libpayload/drivers/usb/dwc2.c | 23 +++++++++++++++++++----
payloads/libpayload/drivers/usb/dwc2_private.h | 16 ++++++++++++++--
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 7af7718..0830c9e 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -35,11 +35,12 @@ static void dwc2_reinit(hci_t *controller)
gintsts_t gintsts = { .d32 = 0 };
gahbcfg_t gahbcfg = { .d32 = 0 };
grxfsiz_t grxfsiz = { .d32 = 0 };
+ ghwcfg3_t hwcfg3 = { .d32 = 0 };
hcintmsk_t hcintmsk = { .d32 = 0 };
gnptxfsiz_t gnptxfsiz = { .d32 = 0 };
const int timeout = 10000;
- int i;
+ int i, fifo_blocks, tx_blocks;
/* Wait for AHB idle */
for (i = 0; i < timeout; i++) {
@@ -86,10 +87,24 @@ static void dwc2_reinit(hci_t *controller)
* The non-periodic tx fifo and rx fifo share one continuous
* piece of IP-internal SRAM.
*/
- grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH;
+
+ /*
+ * Read total data FIFO depth from HWCFG3
+ * this value is in terms of 32-bit words
+ */
+ hwcfg3.d32 = readl(®->core.ghwcfg3);
+ /*
+ * Reserve 2 spaces for the status entries of receive packets
+ * and 2 spaces for bulk an control OUT endpoints. Calculate how
+ * many blocks can be alloted, assume largest packet size is 512.
+ */
+ fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4);
+ tx_blocks = fifo_blocks / 2;
+
+ grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4;
writel(grxfsiz.d32, ®->core.grxfsiz);
- gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH;
- gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH;
+ gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep;
+ gnptxfsiz.nptxfdep = tx_blocks * (512 / 4);
writel(gnptxfsiz.d32, ®->core.gnptxfsiz);
/* Init host channels */
diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h
index 9bd8376..fc658bf 100644
--- a/payloads/libpayload/drivers/usb/dwc2_private.h
+++ b/payloads/libpayload/drivers/usb/dwc2_private.h
@@ -374,7 +374,6 @@ typedef union {
struct {
unsigned nptxfstaddr:16;
unsigned nptxfdep:16;
-#define DWC2_NPTXFIFO_DEPTH 0x80
};
} gnptxfsiz_t;
@@ -390,7 +389,6 @@ typedef union {
*/
struct {
unsigned rxfdep:16;
-#define DWC2_RXFIFO_DEPTH 0x200
unsigned reserved:16;
};
} grxfsiz_t;
@@ -438,6 +436,20 @@ typedef union {
} gintsts_t;
/**
+ * This union represents the bit fields of the User HW Config3 Register
+ * (GHWCFG3).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned reserved:16;
+ unsigned dfifodepth:16;
+ };
+} ghwcfg3_t;
+
+/**
* This union represents the bit fields in the Host Configuration Register.
*/
typedef union {
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9455
-gerrit
commit bdface7422ed08658bf1552230fec7c3f7f2d942
Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Date: Mon Feb 2 15:35:44 2015 +0000
libpayload dwc2: sent address of buffer should be bus address
The address of the output buffer sent to the device should be
the bus address and not the virtual address.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board;
USB works properly after this change
BRANCH=none
Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438
Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245387
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
payloads/libpayload/drivers/usb/dwc2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 0830c9e..1102711 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -253,7 +253,8 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
memcpy(aligned_buf, data_buf, size);
writel(hctsiz.d32, ®->host.hchn[ch_num].hctsizn);
- writel((uint32_t)aligned_buf, ®->host.hchn[ch_num].hcdman);
+ writel((uint32_t)virt_to_bus(aligned_buf),
+ ®->host.hchn[ch_num].hcdman);
writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
ret = wait_for_complete(ep, ch_num);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9456
-gerrit
commit d506698beedcb70e57933cae947ab3a697dd4ecb
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Apr 9 15:50:38 2015 +0200
bg4cd: drop init_timer() stub
It's much better stubbed in a generic header.
Change-Id: I41087604439aa0bcb8310cf6465f1a3d563d0b58
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/soc/marvell/bg4cd/monotonic_timer.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/soc/marvell/bg4cd/monotonic_timer.c b/src/soc/marvell/bg4cd/monotonic_timer.c
index a84b036..195a9c3 100644
--- a/src/soc/marvell/bg4cd/monotonic_timer.c
+++ b/src/soc/marvell/bg4cd/monotonic_timer.c
@@ -23,7 +23,3 @@
void timer_monotonic_get(struct mono_time *mt)
{
}
-
-void init_timer(void)
-{
-}
the following patch was just integrated into master:
commit 7d186633170b78f7c83b154f41dc0f8336310715
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Oct 20 14:21:22 2014 -0700
bg4cd: Change all SoC headers to <soc/headername.h> system
This patch aligns bg4cd to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Cosmos.
Change-Id: I32a4407f7deb2b1752b6220a140352724f320637
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0b6bb6990417863010258632374c3f5ac19350c9
Original-Change-Id: Ia5299659ad186f2e7d698adfa7562396e747473f
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224506
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9358 for details.
-gerrit
the following patch was just integrated into master:
commit c8385ddd3b7c24d33fdf3f7d59674f143ce04b4c
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Oct 16 11:20:15 2014 -0700
bg4cd, cosmos: use SPI_WRAPPER configuration mode
The SOC code should include the SPI controller driver when configured.
Enable SPI support for cosmos.
BRANCH=none
BUG=chrome-os-partner:32631
TEST=cosmos builds
Change-Id: I8212f191b7d80f0bee86f746813edaf8e5ee6db1
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fd4853be5157247bb73fc22b9d4f8300228fe6ce
Original-Change-Id: If7e12e2fb04e63c36d9696d13e08397b91a77a8c
Original-Commit-Id: 7b1d095e5df6a864d3564bbf7a20cc211f75629a
Original-Change-Id: If9dd80cb96120d34a0865f7882cd62e45fed749d
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223750
Original-Reviewed-on: https://chromium-review.googlesource.com/223752
Reviewed-on: http://review.coreboot.org/9356
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9356 for details.
-gerrit