Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9436
-gerrit
commit 8220ba4ffedccf64d7c885f07848d484653527d5
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Tue Oct 28 18:26:12 2014 -0700
fmap: use CBFS for all other than x86 platforms
The architectiure check in fmap.c is in fact used to delineate between
platforms where SPI flash is mapped to memory address space and where
it needs to be accessed through CBFS.
In fact cosmos board uses an ARM SOC which also maps SPI flash to
processor address space, this will have to be addressed when that
SOC's support is introduced, for now let's just presume that all but
X86 platforms require CBFS layer to access fmap.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=none
Original-Change-Id: Id135dc63278555a7fc5039a568fb28864f7cb8d1
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226180
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit b3c04f84504380066c54a6dec93781a4f25a5fc6)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I3a0a70fe583b69b1c9cd8729817bd7062126e1a9
---
src/vendorcode/google/chromeos/fmap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c
index 7c1f626..7c256ce 100644
--- a/src/vendorcode/google/chromeos/fmap.c
+++ b/src/vendorcode/google/chromeos/fmap.c
@@ -41,7 +41,7 @@ const struct fmap *fmap_find(void)
/* wrapping around 0x100000000 */
const struct fmap *fmap = (void *)
(CONFIG_FLASHMAP_OFFSET - CONFIG_ROM_SIZE);
-#elif CONFIG_ARCH_ARM
+#else
struct cbfs_media default_media, *media;
media = &default_media;
init_default_cbfs_media(media);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9439
-gerrit
commit 7ea04497bb7a7f13185d9857130818796d2a590f
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Nov 12 14:01:23 2014 -0800
vboot: fix invalid check for the returned value from spi_flash->write
spi_flash->write returns non-zero on error and zero on success, not the
number of bytes written.
BUG=none
BRANCH=ToT
TEST=Booted storm. Verified successfully nvdata was saved.
Original-Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229389
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org>
(cherry picked from commit 1e8cdbdb07e99c3f72c35f76d68144f46107acd9)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I216e97f734da8d4b52c2da8329f4143b7b0656cd
---
src/vendorcode/google/chromeos/vbnv_flash.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c
index cf7c002..665c184 100644
--- a/src/vendorcode/google/chromeos/vbnv_flash.c
+++ b/src/vendorcode/google/chromeos/vbnv_flash.c
@@ -175,8 +175,7 @@ void save_vbnv(const uint8_t *vbnv_copy)
if (vbnv_flash_probe())
return; /* error */
- if (spi_flash->write(spi_flash, new_offset,
- BLOB_SIZE, vbnv_copy) != BLOB_SIZE) {
+ if (spi_flash->write(spi_flash, new_offset, BLOB_SIZE, vbnv_copy)) {
printk(BIOS_ERR, "failed to write nvdata\n");
return; /* error */
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9438
-gerrit
commit 6ead7102babfa0cc50c95f6ee6005c29eebf80f0
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Mon Nov 3 17:42:09 2014 -0800
cbtables: Add RAM config information
This adds the RAM config code to the coreboot tables. The purpose is
to expose this information to software running at higher levels, e.g.
to print the RAM config coreboot is using as part of factory tests.
The prototype for ram_code() is in boardid.h since they are closely
related and will likely have common code.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=tested w/ follow-up CLs on pinky
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Change-Id: Idd38ec5b6af16e87dfff2e3750c18fdaea604400
Original-Reviewed-on: https://chromium-review.googlesource.com/227248
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
(cherry picked from commit 77dd5fb9347b53bb8a64ad22341257fb3be0c106)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: Ibe7044cafe0a61214ac2d7fea5f7255b2c11829b
---
src/Kconfig | 7 +++++++
src/include/boardid.h | 1 +
src/include/boot/coreboot_tables.h | 7 +++++++
src/lib/coreboot_table.c | 16 ++++++++++++++++
4 files changed, 31 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index f94fad4..5cc5485 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -253,6 +253,13 @@ config UPDATE_IMAGE
is a suitable file for further processing.
The bootblock will not be modified.
+config RAM_CODE_SUPPORT
+ bool "Discover RAM configuration code and store it in coreboot table"
+ default n
+ help
+ If enabled, coreboot discovers RAM configuration (value obtained by
+ reading board straps) and stores it in coreboot table.
+
endmenu
source "src/mainboard/Kconfig"
diff --git a/src/include/boardid.h b/src/include/boardid.h
index d1c6ad9..41c21d6 100644
--- a/src/include/boardid.h
+++ b/src/include/boardid.h
@@ -23,5 +23,6 @@
#include <stdint.h>
uint8_t board_id(void);
+uint32_t ram_code(void);
#endif /* __INCLUDE_BOARDID_H__ */
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 0efb8fd..d9df787 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -276,6 +276,13 @@ struct lb_macs {
struct mac_address mac_addrs[0];
};
+#define LB_TAG_RAM_CODE 0x0028
+struct lb_ram_code {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t ram_code;
+};
+
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index a8b5edf..a514bb9 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -297,6 +297,19 @@ static void lb_board_id(struct lb_header *header)
#endif
}
+static void lb_ram_code(struct lb_header *header)
+{
+#if IS_ENABLED(CONFIG_RAM_CODE_SUPPORT)
+ struct lb_ram_code *code;
+
+ code = (struct lb_ram_code *)lb_new_record(header);
+
+ code->tag = LB_TAG_RAM_CODE;
+ code->size = sizeof(*code);
+ code->ram_code = ram_code();
+#endif
+}
+
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@@ -525,6 +538,9 @@ unsigned long write_coreboot_table(
/* Add board ID if available */
lb_board_id(head);
+ /* Add RAM config if available */
+ lb_ram_code(head);
+
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9447
-gerrit
commit ac69bdd47fa34d14bb9b0041f09a2b5c9eae9e62
Author: Randall Spangler <rspangler(a)chromium.org>
Date: Thu Dec 4 12:58:54 2014 -0800
vboot: Remove unused 2lib header path
Before the change to use vb2_api.h, coreboot needed to know where to
find the vboot2 header files. Now those are all included by
vb2_api.h, so coreboot doesn't need to know about
firmware/2lib/include (and in fact, the 2lib directory is about to go
away).
BUG=chromium:423882
BRANCH=none
TEST=emerge-veyron_pinky coreboot
Original-Change-Id: I7f69ca9cf8d45c325219efceca0cb8d1340f7736
Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/233223
Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org>
(cherry picked from commit b4d4a2da1c8b5a5f8f8da51f009227d3a616b096)
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I4006f38835ea0f927142a8133bc24caaf2b7a214
---
src/vendorcode/google/chromeos/Makefile.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 0908b45..649e1fd 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -52,5 +52,4 @@ endif
VB_SOURCE := vboot_reference
subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot1
subdirs-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += vboot2
-CPPFLAGS_common += -I$(VB_SOURCE)/firmware/2lib/include
CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include