Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9509
-gerrit
commit a758a7107a9f11e6cb338f723c9800b7348f1f6b
Author: Kane Chen <kane.chen(a)intel.com>
Date: Thu Feb 12 16:08:42 2015 +0800
baytrail: correct NC pin to GPO pin according to BYT platform design guide
According to BYT platform design guide chap 14.2.2, the NC GPIOs
need to be configured to GPO.
BRANCH=none
BUG=none
TEST=Test on rambi, boot to OS, and make sure NC pins config to GPO
Change-Id: Ida5ea89ee66e39b4fddea242dc918b314756d94f
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 998493566f5cf7abd9375583e12fe631b226e591
Original-Change-Id: Ieaf346d1c7bf3ecb47a71a6ee4afaa805235cc37
Original-Signed-off-by: Kane Chen <kane.chen(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/249060
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/include/soc/gpio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 413ade2..f312cdc 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -322,7 +322,7 @@
#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
#define GPIO_INPUT_PU GPIO_INPUT_PU_20K
#define GPIO_INPUT_PD GPIO_INPUT_PD_20K
-#define GPIO_NC GPIO_INPUT_PU_20K
+#define GPIO_NC GPIO_OUT_HIGH
#define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9508
-gerrit
commit c77b0187ec55ce2e5ea69fc28a1872bf655feb74
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Feb 23 15:14:54 2015 -0800
samus: Log EC panics to eventlog
Log the new EC panic host event.
BUG=chrome-os-partner:36985
TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in
previous boot" is seen in /var/log/eventlog.
BRANCH=Samus
Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36
Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7
Original-Reviewed-on: https://chromium-review.googlesource.com/252391
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg(a)chromium.org>
---
src/ec/google/chromeec/ec_commands.h | 3 +++
src/mainboard/google/samus/ec.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index bd94281..725a652 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -278,6 +278,9 @@ enum host_event_code {
/* Battery Status flags have changed */
EC_HOST_EVENT_BATTERY_STATUS = 23,
+ /* EC encountered a panic, triggering an reset */
+ EC_HOST_EVENT_PANIC = 24,
+
/*
* The high bit of the event mask is not used as a host event code. If
* it reads back as set, then the entire event mask should be
diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h
index 1ba1677..9b932ac 100644
--- a/src/mainboard/google/samus/ec.h
+++ b/src/mainboard/google/samus/ec.h
@@ -57,7 +57,8 @@
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#ifndef __ACPI__
extern void mainboard_ec_init(void);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9507
-gerrit
commit 75942656aff4e2e11a455f403cef1645dd203386
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 20 13:36:11 2015 -0800
cros_ec: Retry failed VBNV transactions
This patch adds a few retries to NVRAM read/write transactions with the
EC. Failing to read the NVRAM is not fatal to the boot, but it's still
pretty bad... especially since a single initial read failure will cause
vboot to blindly reinitialize the whole NVRAM with zeroes, destroying
important configuration bits like dev_boot_usb. The current EC
transaction timeout is one second, so the three retries added here can
potentially increase boot time by three seconds per transaction... but
this shouldn't happen in any normal case anyway, and if there are errors
a little extra wait is probably preferrable to nuking your NVRAM.
(Also, added a missing newline to an error message in the EC code.)
BRANCH=veyron
BUG=chrome-os-partner:36924
TEST=Booted a Jerry with the power button bug with a 2 second press,
noticed that the first two transactions failed but the third one
succeeded.
Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a
Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251694
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/ec/google/chromeec/crosec_proto.c | 2 +-
src/ec/google/chromeec/ec.c | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c
index 55a707d..1183e82 100644
--- a/src/ec/google/chromeec/crosec_proto.c
+++ b/src/ec/google/chromeec/crosec_proto.c
@@ -235,7 +235,7 @@ static int send_command_proto3(struct chromeec_command *cec_command,
rv = crosec_io(out_bytes, in_bytes, context);
if (rv != 0) {
- printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.",
+ printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.\n",
__func__, rv >= 0 ? rv : -rv);
return -EC_RES_ERROR;
}
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 83c22d3..bda88e4 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -232,11 +232,12 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
struct chromeec_command cec_cmd;
struct ec_params_vbnvcontext cmd_vbnvcontext;
struct ec_response_vbnvcontext rsp_vbnvcontext;
+ int retries = 3;
if (len != EC_VBNV_BLOCK_SIZE)
return -1;
-
+ retry:
cec_cmd.cmd_code = EC_CMD_VBNV_CONTEXT;
cec_cmd.cmd_version = EC_VER_VBNV_CONTEXT;
cec_cmd.cmd_data_in = &cmd_vbnvcontext;
@@ -251,7 +252,13 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
if (!is_read)
memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE);
- google_chromeec_command(&cec_cmd);
+ if (google_chromeec_command(&cec_cmd)) {
+ printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n",
+ is_read ? "read" : "write", (int)cec_cmd.cmd_code);
+ mdelay(10); /* just in case */
+ if (--retries)
+ goto retry;
+ }
if (is_read)
memcpy(data, &rsp_vbnvcontext.block, EC_VBNV_BLOCK_SIZE);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9505
-gerrit
commit 59d0f733bcec078874234e9cf2c9c5ae8ca50826
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 9 21:16:14 2015 -0800
Intel SOC Common: Reset
Move reset support into the Intel common branch. Prevent breaking of
existing platforms by using a Kconfig value to select use of the common
reset code.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248301
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/common/Kconfig | 4 +++
src/soc/intel/common/Makefile.inc | 2 ++
src/soc/intel/common/reset.c | 54 +++++++++++++++++++++++++++++++++++++++
3 files changed, 60 insertions(+)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index aadd64d..a67396e 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -21,3 +21,7 @@ config MRC_SETTINGS_PROTECT
endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
+
+config COMMON_RESET
+ bool
+ default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 0c39d80..1861ec3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -2,3 +2,5 @@ ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+ramstage-$(CONFIG_COMMON_RESET) += reset.c
+romstage-$(CONFIG_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
new file mode 100644
index 0000000..2046c3b
--- /dev/null
+++ b/src/soc/intel/common/reset.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <reset.h>
+
+/* Reset control port */
+#define RST_CNT 0xcf9
+#define FULL_RST (1 << 3)
+#define RST_CPU (1 << 2)
+#define SYS_RST (1 << 1)
+
+void hard_reset(void)
+{
+ /* S0->S5->S0 trip. */
+ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void soft_reset(void)
+{
+ /* PMC_PLTRST# asserted. */
+ outb(RST_CPU | SYS_RST, RST_CNT);
+ while (1)
+ hlt();
+}
+
+void cpu_reset(void)
+{
+ /* Sends INIT# to CPU */
+ outb(RST_CPU, RST_CNT);
+ while (1)
+ hlt();
+}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9504
-gerrit
commit 7993184a19bfb547f059cc1f50fec87496bb4519
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 9 21:09:49 2015 -0800
x86: Support reset routines in bootblock
Expand the boot block include file to allow for a file containing reset
routines to be added. Prevent breaking existing platforms by using a
Kconfig value to specify the path to this file, and have the code
include this file only if the Kconfig value is set.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I604f701057d7018f2ed9c3ba49a643c4bca13f00
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: c109481d9503916e19ed300c1a3f085e0d2b5c51
Original-Change-Id: I3214399f8156b5ea2ef709ce77e3915cea1523a3
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248300
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com>
---
src/arch/x86/Kconfig | 3 +++
src/arch/x86/include/bootblock_common.h | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index f7da89a..29f0514 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -84,6 +84,9 @@ config BOOTBLOCK_MAINBOARD_INIT
config BOOTBLOCK_NORTHBRIDGE_INIT
string
+config BOOTBLOCK_RESETS
+ string
+
config HAVE_CMOS_DEFAULT
def_bool n
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index b4100b7..939ba08 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -2,6 +2,10 @@
#include <cpu/x86/lapic/boot_cpu.c>
#include <pc80/mc146818rtc.h>
+#ifdef CONFIG_BOOTBLOCK_RESETS
+#include CONFIG_BOOTBLOCK_RESETS
+#endif
+
#ifdef CONFIG_BOOTBLOCK_CPU_INIT
#include CONFIG_BOOTBLOCK_CPU_INIT
#endif
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9503
-gerrit
commit 8cba03537fac8f27c041bbaf4067630e66e752e6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 5 12:55:45 2015 -0800
elog: Fix regression that caused elog to omit "System boot" event
CL:243671 moved the initialization of elog_initialized around, which is
now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted
because the code believes the log to be broken at that time. Good thing
we now have a FAFT test for these things that I had of course been too
lazy to run. -.-
The real reason for moving that line was to put it after any point in
elog_init() that could still error out. The problem is that we might add
the "cleared" event before we try to shrink (which can fail and cause an
error)... but those two things cannot happen at the same time, so it
should be okay to flip them around and mark the elog as initialized in
between.
BRANCH=none
BUG=chrome-os-partner:35940
TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once
again get "System boot" events.
Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9
Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246715
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/elog/elog.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 8bc8a07..6d32878 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -606,15 +606,17 @@ int elog_init(void)
" shrink size %d\n", total_size,
CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE);
- /* Log a clear event if necessary */
- if (event_count == 0)
- elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+ elog_initialized = ELOG_INITIALIZED;
/* Shrink the log if we are getting too full */
if (next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD)
if (elog_shrink() < 0)
return -1;
+ /* Log a clear event if necessary */
+ if (event_count == 0)
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+
#if !defined(__SMM__)
/* Log boot count event except in S3 resume */
#if CONFIG_ELOG_BOOT_COUNT == 1
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9502
-gerrit
commit c67986092bd1db221d8fdda4768f9374d282b17e
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 6 15:34:14 2015 -0800
broadwell: Correct XHCI offset for USB 3.0 ports
Looks like Intel has added two more USB 2.0 ports from LynxPoint to
Broadwell, which shifted the port offsets of the USB 3.0 ports behind
them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to
0x560 (at least according to what my kernel seems to think). The offset
of the first USB 3.0 port is hardcoded and seems to have been copied
over without accounting for this, meaning when we try to operate on all
USB 3.0 ports we actually operate on the last two 2.0 and the first two
3.0 ports instead.
This patch should fix the bug for now. In the future, we might want to
consider dynamically detecting port locations through the Protocol
Capability structures at the end of the XHCI register set instead.
BRANCH=samus
BUG=chrome-os-partner:35320
TEST=TODO
Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397
Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247351
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Todd Broch <tbroch(a)chromium.org>
---
src/soc/intel/broadwell/include/soc/xhci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index 3f4fb4e..2b899a3 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -39,7 +39,7 @@
#define XHCI_USB3PDO 0xe8
/* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
+#define XHCI_USB3_PORTSC(port) (0x530 + (port * 0x10))
#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9500
-gerrit
commit eae4a7e89de8a50c5fb580d4dfdc601f4bac40b6
Author: Ben Zhang <benzh(a)chromium.org>
Date: Wed Dec 10 17:44:18 2014 -0800
samus: Use codec internal 1.8V as DACREF source
This is needed for audio playback after we disconnect PP1800_CODEC
from DACREF to avoid noise coupled on PP1800_CODEC, which makes
recording noisy.
For recording, DACREF comes from mic vref pump voltage.
For playback, DACREF comes from internal 1.8V.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean
Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b
Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241179
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 287f595..2140898 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -178,6 +178,7 @@ Scope (\_SB.PCI0.I2C0)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
Name (MB1, 1) /* MICBIAS1 = 2.970V */
+ Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -195,6 +196,7 @@ Scope (\_SB.PCI0.I2C0)
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "realtek,micbias1", 1 },
+ Package () { "realtek,internal-dacref-en", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },