Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9481
-gerrit
commit 46e9c15d760da0aeb26857b5da26fa7967b7aac6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Dec 19 14:38:51 2014 -0800
TPM: Reduce buffer size to fix stack overflow
The TPM driver by default allocates a 4K transfer buffer on the stack,
which leads to lots of fun on boards with 2K or 3K stack sizes. On
RK3288 this ends up writing over random memory sections which dependent
on the memlayout of the day might contain timestamp data (no big deal)
or page tables (-> bad time).
This patch fixes the problem by reducing the buffer size to slightly
above 1K, which still seems to work as far as I can tell. There was
already some really odd code that #undef'ed this value and redefined it
with the lower number in one .c file (unfortunately not the one with the
buffer declaration), with no explanation whatsoever... I'm removing that
and just assume the smaller value will be fine for everything.
BRANCH=veyron
BUG=None
TEST=Booted Pinky and Falco.
Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81
Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236976
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/drivers/i2c/tpm/tpm.c | 6 ------
src/drivers/i2c/tpm/tpm.h | 4 ++--
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
index bc36e35..3af82db 100644
--- a/src/drivers/i2c/tpm/tpm.c
+++ b/src/drivers/i2c/tpm/tpm.c
@@ -45,12 +45,6 @@
#include <device/i2c.h>
#include "tpm.h"
-/* max. buffer size supported by our TPM */
-#ifdef TPM_BUFSIZE
-#undef TPM_BUFSIZE
-#endif
-#define TPM_BUFSIZE 1260
-
/* Address of the TPM on the I2C bus */
#define TPM_I2C_ADDR 0x20
diff --git a/src/drivers/i2c/tpm/tpm.h b/src/drivers/i2c/tpm/tpm.h
index 6d195a1..de88a66 100644
--- a/src/drivers/i2c/tpm/tpm.h
+++ b/src/drivers/i2c/tpm/tpm.h
@@ -42,8 +42,8 @@ enum tpm_timeout {
TPM_TIMEOUT = 1, /* msecs */
};
-/* Size of external transmit buffer (used in tpm_transmit)*/
-#define TPM_BUFSIZE 4096
+/* Size of external transmit buffer (used for stack buffer in tpm_sendrecv) */
+#define TPM_BUFSIZE 1260
/* Index of fields in TPM command buffer */
#define TPM_CMD_SIZE_BYTE 2
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9480
-gerrit
commit 55db3666f605f7349e717be4599acebc94660951
Author: Kevin L Lee <kevin.l.lee(a)intel.com>
Date: Fri Dec 12 14:02:43 2014 +0800
baytrail:fix the coding error on PCIe L1 exit lantency
The original code use L1EXIT_MASK to shift the bit for
PCIe L1 exist lantency, the code should be use
L1EXIT_SHIFT for bit shift.
BUG=chrome-os-partner:34037
BRANCH=None
TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15]
set to 010b. Correspond WIFI device performance got improvement.
Signed-off-by: Kevin L Lee <kevin.l.lee(a)intel.com>
Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be
Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92
Original-Reviewed-on: https://chromium-review.googlesource.com/234673
Original-Reviewed-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com>
Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com>
---
src/soc/intel/baytrail/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 1870158..e44ebc6 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev)
/* Exit latency configuration based on
* PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
REG_PCI_RMW32(LCAP, ~L1EXIT_MASK,
- 2 << (L1EXIT_MASK + pll_en_off)),
+ 2 << (L1EXIT_SHIFT + pll_en_off)),
REG_SCRIPT_NEXT(init_static_after_exit_latency),
/* Disable hot plug, set power to 10W, set slot number. */
REG_PCI_RMW32(SLCAP, ~(HPC | HPS),
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9495
-gerrit
commit f6a9d4a1c52b0bde7971f7c5f129fd224f98bda8
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:06:42 2015 -0800
broadwell: Preserve VbNv around cmos_init
To ensure that boot flags (legacy, usb, signed-only) are
properly restored from CMOS and used in the first boot after
a battery removal or RTC reset then the VbNv region needs to
be preserved around the cmos_init call.
When using vboot firmware selection and VbNv is stored in CMOS
then that region of CMOS will have been re-initialized by the
time we call cmos_init and reset CMOS if the chipset flag was
set indicating a problem.
BUG=chrome-os-partner:35240
BRANCH=broadwell
TEST=manual testing on samus:
1) boot in dev mode, enable dev_boot_legacy and ensure it works
2) on EC console pulse PCH_RTCRST_L low for a second
3) ensure first boot after RTC reset will still boot legacy mode
4) remove battery for a time
5) ensure first boot after battery is re-inserted will still
boot legacy mode
Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa
Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241529
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/lpc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 6ebc758..9a4c65c 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -49,6 +49,10 @@
#include <arch/acpigen.h>
#include <cpu/cpu.h>
+#if IS_ENABLED(CONFIG_CHROMEOS)
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
@@ -174,6 +178,25 @@ static void pch_power_options(device_t dev)
enable_alt_smi(config->alt_gp_smi_en);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+/*
+ * Preserve Vboot NV data when clearing CMOS as it will
+ * have been re-initialized already by Vboot firmware init.
+ */
+static void pch_cmos_init_preserve(int reset)
+{
+ uint8_t vbnv[CONFIG_VBNV_SIZE];
+
+ if (reset)
+ read_vbnv(vbnv);
+
+ cmos_init(reset);
+
+ if (reset)
+ save_vbnv(vbnv);
+}
+#endif
+
static void pch_rtc_init(struct device *dev)
{
u8 reg8;
@@ -187,7 +210,11 @@ static void pch_rtc_init(struct device *dev)
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
+#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+ pch_cmos_init_preserve(rtc_failed);
+#else
cmos_init(rtc_failed);
+#endif
}
static const struct reg_script pch_misc_init_script[] = {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9492
-gerrit
commit 1a72652c04a4bd54084330a998dcf6fe891635d2
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 15 13:24:38 2015 -0800
samus: Add clear_recovery_mode_switch function
In order for recovery request to be cleared with software sync disabled
we need to implement this function in the mainboard.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=boot in recovery with software sync disabled, ensure that the next
boot will not boot in recovery again.
Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9
Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241052
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/chromeos.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index fc7acff..fab06e8 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -92,6 +92,15 @@ int get_recovery_mode_switch(void)
#endif
}
+int clear_recovery_mode_switch(void)
+{
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+}
+
int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9490
-gerrit
commit 06ff504252ec8676560120692cf872d0231664e7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:33:00 2015 -0800
broadwell: Turn off panel backlight in S5 SMI handler
In order for some panels to meet spec when the system is put
into S5 by way of power button during firmware (i.e. not by
the OS) then it needs to turn off the backlight and give it
time to turn off before going into S5.
If the OS properly sequences the panel down then the backlight
enable bit will not be set in this step and nothing will happen.
BUG=chrome-os-partner:33994
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: Ic86f388218f889b1fe690cc1bfc5c3e233e95115
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: e3c9c131a87bae380e1fd3f96c9ad780441add56
Original-Change-Id: I43c5aee8e32768fc9e82790c9f7ceda0ed17ed13
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240852
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/smihandler.c | 43 ++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 5004a6a..0374d15 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -36,6 +36,7 @@
#include <soc/rcba.h>
#include <soc/smm.h>
#include <soc/xhci.h>
+#include <device/i915_reg.h>
static u8 smm_initialized = 0;
@@ -109,6 +110,45 @@ static void busmaster_disable_on_bus(int bus)
}
}
+/*
+ * Turn off the backlight if it is on, and wait for the specified
+ * backlight off delay. This will allow panel power timings to meet
+ * spec and prevent brief garbage on the screen when turned off
+ * during firmware with power button triggered SMI.
+ */
+static void backlight_off(void)
+{
+ uint32_t reg_base;
+ uint32_t pp_ctrl;
+ uint32_t bl_off_delay;
+
+ reg_base = pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf;
+
+ /* Check if backlight is enabled */
+ pp_ctrl = read32(reg_base + PCH_PP_CONTROL);
+ if (!(pp_ctrl & EDP_BLC_ENABLE))
+ return;
+
+ /* Enable writes to this register */
+ pp_ctrl &= ~PANEL_UNLOCK_MASK;
+ pp_ctrl |= PANEL_UNLOCK_REGS;
+
+ /* Turn off backlight */
+ pp_ctrl &= ~EDP_BLC_ENABLE;
+
+ write32(reg_base + PCH_PP_CONTROL, pp_ctrl);
+ read32(reg_base + PCH_PP_CONTROL);
+
+ /* Read backlight off delay in 100us units */
+ bl_off_delay = read32(reg_base + PCH_PP_OFF_DELAYS);
+ bl_off_delay &= PANEL_LIGHT_OFF_DELAY_MASK;
+ bl_off_delay *= 100;
+
+ /* Wait for backlight to turn off */
+ udelay(bl_off_delay);
+
+ printk(BIOS_INFO, "Backlight turned off\n");
+}
static void southbridge_smi_sleep(void)
{
@@ -170,6 +210,9 @@ static void southbridge_smi_sleep(void)
case SLP_TYP_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+ /* Turn off backlight if needed */
+ backlight_off();
+
/* Disable all GPE */
disable_all_gpe();
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9491
-gerrit
commit 1bd41d6ace54d744b4ccdf1716406a9815285c20
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:36:08 2015 -0800
samus: Set current backlight PWM value
With recent changes in the 3.14 kernel and the switch to not
using X the panel backlight is not geting turned on until
chrome is started which means the splash screen is not visible.
If we set the backlight PWM in coreboot then it will at least
turn on for the early boot process.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=boot on samus in normal mode and see the boot splash logo
Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b
Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240853
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 26b7b41..0ca7405 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/broadwell
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
+ register "gpu_pch_backlight" = "0x04000200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP