Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9489
-gerrit
commit 7d63630cfb3e31d3f55d5a905c4dc50cb2aec730
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Jan 14 17:30:20 2015 -0800
broadwell: Skip steps when disabling PCIe port
When disabling PCIe ports skip steps if no card is detected.
This prevents the loop from timing out on each empty slot.
BUG=chrome-os-partner:31424
BRANCH=broadwell
TEST=build and boot on samus, check that this code is
no longer timing out when disabling PCIe ports
Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240851
Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/soc/intel/broadwell/pcie.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 4476fe4..e217149 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -321,12 +321,12 @@ static void root_port_commit_config(void)
do {
reg32 = pci_read_config32(dev, 0x328);
n++;
- if (((reg32 & 0xff000000) == 0x01000000) || (n > 500))
+ if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
break;
udelay(100);
} while (1);
- if (n > 500)
+ if (n > 50)
printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
dev_path(dev));
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9502
-gerrit
commit 88d2e4cbfc77ce20b4c333091bd846962923979d
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 6 15:34:14 2015 -0800
broadwell: Correct XHCI offset for USB 3.0 ports
Looks like Intel has added two more USB 2.0 ports from LynxPoint to
Broadwell, which shifted the port offsets of the USB 3.0 ports behind
them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to
0x560 (at least according to what my kernel seems to think). The offset
of the first USB 3.0 port is hardcoded and seems to have been copied
over without accounting for this, meaning when we try to operate on all
USB 3.0 ports we actually operate on the last two 2.0 and the first two
3.0 ports instead.
This patch should fix the bug for now. In the future, we might want to
consider dynamically detecting port locations through the Protocol
Capability structures at the end of the XHCI register set instead.
BRANCH=samus
BUG=chrome-os-partner:35320
TEST=TODO
Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397
Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247351
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-by: Todd Broch <tbroch(a)chromium.org>
---
src/soc/intel/broadwell/include/soc/xhci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index 3f4fb4e..2b899a3 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -39,7 +39,7 @@
#define XHCI_USB3PDO 0xe8
/* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
+#define XHCI_USB3_PORTSC(port) (0x530 + (port * 0x10))
#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9503
-gerrit
commit f0d796d4313f416b8f89544a4b2663a5fd6fe9ae
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Feb 5 12:55:45 2015 -0800
elog: Fix regression that caused elog to omit "System boot" event
CL:243671 moved the initialization of elog_initialized around, which is
now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted
because the code believes the log to be broken at that time. Good thing
we now have a FAFT test for these things that I had of course been too
lazy to run. -.-
The real reason for moving that line was to put it after any point in
elog_init() that could still error out. The problem is that we might add
the "cleared" event before we try to shrink (which can fail and cause an
error)... but those two things cannot happen at the same time, so it
should be okay to flip them around and mark the elog as initialized in
between.
BRANCH=none
BUG=chrome-os-partner:35940
TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once
again get "System boot" events.
Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9
Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246715
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/elog/elog.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 8bc8a07..6d32878 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -606,15 +606,17 @@ int elog_init(void)
" shrink size %d\n", total_size,
CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE);
- /* Log a clear event if necessary */
- if (event_count == 0)
- elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+ elog_initialized = ELOG_INITIALIZED;
/* Shrink the log if we are getting too full */
if (next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD)
if (elog_shrink() < 0)
return -1;
+ /* Log a clear event if necessary */
+ if (event_count == 0)
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR, total_size);
+
#if !defined(__SMM__)
/* Log boot count event except in S3 resume */
#if CONFIG_ELOG_BOOT_COUNT == 1
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9500
-gerrit
commit dfa1c81d9ac48adf46161871b7005e886dd7994f
Author: Ben Zhang <benzh(a)chromium.org>
Date: Wed Dec 10 17:44:18 2014 -0800
samus: Use codec internal 1.8V as DACREF source
This is needed for audio playback after we disconnect PP1800_CODEC
from DACREF to avoid noise coupled on PP1800_CODEC, which makes
recording noisy.
For recording, DACREF comes from mic vref pump voltage.
For playback, DACREF comes from internal 1.8V.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean
Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b
Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241179
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 287f595..2140898 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -178,6 +178,7 @@ Scope (\_SB.PCI0.I2C0)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
Name (MB1, 1) /* MICBIAS1 = 2.970V */
+ Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -195,6 +196,7 @@ Scope (\_SB.PCI0.I2C0)
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "realtek,micbias1", 1 },
+ Package () { "realtek,internal-dacref-en", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9499
-gerrit
commit b1a464d47489b0601d42829365cf8a0310861bae
Author: Ben Zhang <benzh(a)chromium.org>
Date: Fri Nov 21 11:17:53 2014 -0800
samus: Set MICBIAS1 to 2.970V
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does
not match what's specified on the schematic. This patch sets
the voltage to 2.970V (3.3V * 0.90) according to the schematic.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus and verified with a scope
Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c
Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1
Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241178
---
src/mainboard/google/samus/acpi/mainboard.asl | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 54a46d5..287f595 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -177,6 +177,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_UID, 1)
Name (WAKE, 45) /* DSP_INT (use as codec wake) */
+ Name (MB1, 1) /* MICBIAS1 = 2.970V */
Name (DCLK, 0) /* RT5677_DMIC_CLK1 */
Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */
Name (IN1, 1) /* IN1 differential */
@@ -193,6 +194,7 @@ Scope (\_SB.PCI0.I2C0)
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
+ Package () { "realtek,micbias1", 1 },
Package () { "realtek,in1-differential", 1 },
Package () { "realtek,in2-differential", 0 },
Package () { "realtek,lout1-differential", 1 },
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9496
-gerrit
commit 129dc801198b43e8375c424fe94c971d1e6eb81c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sun Jan 18 14:14:17 2015 -0800
samus: Adjust SATA Gen3 TX voltage amplitude
Reduce the SATA Gen3 TX voltage amplitude by 210mV based
on the provided test results to help with SATA validation.
BUG=chrome-os-partner:34121
BRANCH=samus
TEST=build and boot on samus and ensure SATA is still working,
firmware image will be provided for full validation.
Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a
Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241800
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
---
src/mainboard/google/samus/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 0ca7405..3eaea40 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/broadwell
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
+ register "sata_port0_gen3_tx" = "0x72"
register "sio_acpi_mode" = "1"
# Set I2C0 to 1.8V